JP2002164777A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit provided with an output circuit of a CMOS configuration capable of suppressing a through-current even when the size of a CMOS FET is large and suppressing an increase in a consumption current. SOLUTION: This semiconductor integrated circuit is provided with first control circuit 10 to which a signal supplied from an internal circuit is inputted, a second control circuit 20 to which an output signal of the first control circuit is inputted and which generates two output signals in which their mutual rise timing and fall timing are different and the periods of their same logical level are also different, and an output buffer circuit 30 where the respective drains of a PMOS FET 31 for current discharge and an NMOS FET 32 for current absorption, whose gates two output signals of the second control circuit are supplied to in accordance with each other, are connected to its output terminal 52. The second control circuit controls so as to turn on one FET in an off mode between the COMOS FETs of the output buffer circuit after the other FET in an on mode is reversed to an off mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (L
SI), and particularly relates to an output control circuit that controls the through current of the output circuit to be reduced.
Used for SI.

[0002]

2. Description of the Related Art FIG. 8 shows an example of a conventional CMOS CMOS output circuit.

An input signal supplied from an LSI internal circuit to an input terminal 71 is input to a CMOS through two-stage CMOS inverters 73 and 74.
It is input to an output buffer circuit 70 having an inverter configuration. The output buffer circuit 70 includes a current source PM connected between the power supply node and the output terminal 72 between the source and the drain.
An OS FET 75 and a current sink NMOS FET 76 connected between the output terminal 72 and the ground node between the drain and the source, and the two FETs 75, the drains of which are commonly connected to the output terminal as described above, In the gate 76, each gate is connected in common and driven by push-pull.

In this push-pull drive, if one of the on-state FETs is turned on before the other on-state FET is inverted to the off state, there is a period in which the CMOS FETs are on at the same time. CMOS to ground node
A current flows through the FET. This will be described in detail below.

FIG. 9 shows an example of operation waveforms of the output circuit of FIG.

The input signal changes from "L" to "H" during the period A, and the output signal of the preceding stage of the two-stage CMOS inverter is changed to the period B.
And the output signal (input signal of the output buffer circuit) at the latter stage of the two-stage CMOS inverter is changed during the period C.
Changes from "L" to "H". As a result, the PMOS FET of the output buffer circuit changes from the on state to the off state, and the NMOS
Since the FET changes from the off state to the on state, the output signal of the output terminal changes from "H" to "L".

At this time, as shown in FIG. 10, during the transition (change) of the logic level of the input signal of the output buffer circuit from "L" to "H", the threshold voltage Vthn of the NMOS FET is changed.
At time t1 when the NMOS FET is turned on after
Since the OS FET is still in the ON state, the through current starts to flow, and the value of the through current reaches a peak at time t2.
Then, at time t3 when the input signal of the output buffer circuit exceeds the threshold voltage Vthp of the PMOS FET, the PMOS FET is turned off, and no through current flows.

Contrary to the above, when the level of the input signal of the output circuit changes from "H" to "L" and exceeds the threshold voltage Vthp of the PMOS FET and the PMOS FET is turned on, the NMOS is turned on. Since the FET is still in the ON state, the through current starts to flow, and the value of the through current eventually reaches a peak. Then, when the input signal of the output buffer circuit becomes lower than the threshold voltage Vthn of the NMOS FET, the NMOS FET is turned off, and no through current flows.

As described above, in the conventional output buffer circuit of a semiconductor integrated circuit, a through current flows during push-pull driving of a CMOS FET. The through current increases as the size of the FET increases, which leads to an increase in current consumption. .

[0010]

As described above, a conventional output buffer circuit having a CMOS configuration of a semiconductor integrated circuit is a CMOS-based output buffer circuit.
As the size of the FET increases, the through current increases, which causes a problem of increasing current consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has an output buffer circuit having a CMOS configuration capable of suppressing a through current even when the size of a CMOS FET is large and suppressing an increase in current consumption. It is an object to provide a semiconductor integrated circuit.

[0012]

A semiconductor integrated circuit according to the present invention has a first control circuit to which a signal supplied from an internal circuit is inputted, and an output signal of the first control circuit to be inputted, and a rising timing of each other. And a second control circuit for generating two output signals having different falling timings and different periods of the same logic level, and a current source for supplying the two output signals of the second control circuit to the corresponding gate. An output buffer circuit in which each drain of a PMOS FET and an NMOS FET for sinking current is connected to an output terminal, and wherein the second control circuit includes the PMOS for discharging current.
One of the FET and the current-sinking NMOSFET is controlled so that one of the on-state FETs is turned off and then the other off-state FET is turned on.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an example of a CMOS integrated output circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

An input signal supplied from the LSI internal circuit to an input terminal 51 is input to a first control circuit 10, and an output signal of the first control circuit 10 and a signal supplied from the internal circuit are supplied to a second control circuit 10. Enter 20. This second control circuit 20
The potentials of the two control output nodes 1 and 2 are connected to the first control circuit 10
To output two output signals from the two output nodes 3 and 4 having different rising timings and falling timings and different periods of the same logic level.

The output buffer circuit 30 is connected to the second control circuit.
Two output signals of 20 are supplied to the gate correspondingly, a PMOS FET 31 for current source and an NMOS F for current sink.
The drains of the ET 32 are commonly connected to the output terminal 52.

In other words, the output buffer circuit 30 has a source-drain PMOS FET 31 connected between a VCC (power supply potential) node and the output terminal 52, and a drain-source output terminal 52 connected between the source and drain. And a current sink NMOS FET 32 connected between the gate and the GND (ground potential) node.

The second control circuit 20 includes the CMOS FET described above.
When the push-pull drive is performed on the transistors 31 and 32, one of the CMOS FETs is controlled so that the on-state FET is inverted to the off-state and then the other off-state FET is turned on.

Hereinafter, the configurations of the first control circuit 10 and the second control circuit 20 will be described in detail.

In the first control circuit 10, the logic level of the signal supplied from the internal circuit and the logic level of the potential fed back from the two control output nodes 1 and 2 of the second control circuit 20 satisfy predetermined conditions. Is configured so that the logic level of the output signal is determined when the signal is output.

As a specific example, the first control circuit 10 has a first
It comprises a PMOS control circuit 10a and a first NMOS control circuit 10b. The first PMOS control circuit 10a includes a first PMOS FET 11 having a source connected to the VCC node, and a first PMOS FET 11 connected to the VCC node.
A second PMOS FET 12 having a source connected to the drain of the ET. The first NMOS control circuit 10b includes a first NMOS FET 14 having a source connected to the GND node, and a second NMOS FET 14 having a source connected to the drain of the first NMOS FET 14.
And an NMOS FET13.

The first PMOS FET 11 and the first NMOS F
In the ET14, each gate is connected in common, and the second
The drains of the PMOS FET 12 and the second NMOS FET 13 are commonly connected, and serve as output nodes of the first control circuit 10.

The second control circuit 20 comprises a second PMOS control circuit 20a, a second NMOS control circuit 20b and a connection node switching control circuit 20c.

The second PMOS control circuit 20a has a source
A third PMOSFET 21 connected to the VCC node;
The third NMOS FET 22 whose gate is connected to the PMOS FET and whose drain is connected to each other and whose source is the first control output node 1
A fourth NMOS FET 23 having a drain and a source connected between the VCC node and the first control output node 1;
The first control output node 1 and GN are connected between the drain and the source.
And a fifth NMOS FET 24 connected between the D node.

Then, the third PMOS FET 21 and the third NM
The signal of the output node of the first control circuit 10 is commonly input to each gate of the OS FET 22, and the gates of the fourth NMOS FET 23 and the fifth NMOS FET 24 connected to the first control output node 1 are connected to the respective gates. Signals separately supplied from the connection node switching control circuit 20c are separately input.

The second NMOS control circuit 20b has a source
A sixth NMOSFET 28 connected to the GND node;
A sixth PMOS FET 27 in which the NMOS FET and the gate are connected to each other and the drains are connected to each other and the source is the second control output node 2
A fourth PMOS FET 26 having a source and a drain connected between the VCC node and the second control output node 2;
The second control output node 2 is connected between the source and the drain with the GN
And a fifth PMOS FET 25 connected to the D node.

The sixth PMOS FET 27 and the sixth NM
The signal of the output node of the first control circuit 10 is commonly input to each gate of the OS FET 28, and the gates of the fourth PMOS FET 26 and the fifth PMOS FET 25 connected to the second control output node 2 Signals separately supplied from the connection node switching control circuit 20c are separately input.

The connection node switching control circuit 20c is
An input signal supplied from an LSI internal circuit is input, and this input signal is input to a fourth NMOS FET of the second PMOS control circuit 20a.
23 gate and the fifth PMOS of the second NMOS control circuit 20b
Supply directly to the gate of FET25. After the input signal is inverted by the inverter circuit 41, the gate of the fifth NMOS FET 24 of the second PMOS control circuit 20a and the second NM
It is supplied to the gate of the fourth PMOS FET 26 of the OS control circuit 20b.

Then, the potential of the first control output node 1 of the second PMOS control circuit 20a is changed to the first NMOS control circuit 20a.
10b becomes a feedback input of the gate of the second NMOS FET 13 and the potential of the second control output node 2 of the second NMOS control circuit 20b becomes the second PMOS FET 12 of the first PMOS control circuit 10a.
This is the feedback input for the gate of

The output signal of the output node 3 to which the drains of the third PMOS FET 21 and the third NMOS FET 22 of the second PMOS control circuit 20a are connected is output to the output buffer circuit 30.
The sixth PMOS FET 27 and the sixth NM of the second NMOS control circuit 20b are supplied to the gate of a PMOS FET 31 for discharging current.
The output signal of the output node 4 to which the drain of the OS FET 28 is connected is connected to the NMOS F
Input to the gate of ET32.

FIGS. 2 to 5 show the case where the logic level of the input signal of the output circuit of FIG.
FIG. 4 is a circuit diagram in which the source and the drain of the FET which is in the ON state when the FET is turned on are short-circuited with a thick line.

FIG. 2 shows that the input signal of the output circuit of FIG.
FIG. 4 is a circuit diagram in which the source and the drain of the FET that is in the ON state at the time of the short circuit are short-circuited with a thick line.

FIG. 3 shows that the input signal of the output circuit of FIG.
The source of the FET that is turned on when it changes from "H" to "H"
FIG. 3 is a circuit diagram showing a state in which drains are short-circuited by a thick line.

FIG. 4 shows that the input signal of the output circuit of FIG.
FIG. 4 is a circuit diagram in which the source and the drain of the FET that is in the ON state at the time of the short circuit are short-circuited with a thick line.

FIG. 5 shows that the input signal of the output circuit of FIG.
The source of the FET that is turned on when it changes from "L" to "L"
FIG. 3 is a circuit diagram showing a state in which drains are short-circuited by a thick line.

FIG. 6 is a waveform chart showing an example of the operation of the output circuit of FIG.

Hereinafter, an operation example of the output circuit of FIG. 1 will be described in detail with reference to FIG.

First, when the input signal is "L", as shown in FIG. 2, the two PMOS FETs 1 of the first PMOS control circuit 10a
Numerals 1 and 12 are on, respectively, and the signal of the output node of the first control circuit 10 is "H". Then, the NMOS FET 22 and the NMOS FET 24 of the second PMOS control circuit 20a are each in the ON state, the output signal of the second PMOS control circuit 20a is "L", and the PMOS FET 31 for discharging current of the output buffer circuit 30.
Are driven to the ON state.

At this time, the PMOS F of the second NMOS control circuit 20b
ET25 and NMOS FET28 are on respectively, and the second NM
The output signal of the OS control circuit 20b is "L", and the current-sinking NMOS FET 32 of the output buffer circuit 30 is off. Therefore, the output terminal 52 is at "H".

Next, as shown in period A, the input signal
When the signal changes from "L" to "H", as shown in FIG.
The PMOS FET 11 of the MOS control circuit 10a changes from on to off, and the NMOS FET 14 of the first NMOS control circuit 10b changes from off to on. The NMOS of the second PMOS control circuit 20a
The FET 23 changes from off to on, and the second PMOS control circuit 20
The NMOS FET 24a changes from on to off, the PMOS FET 25 of the second NMOS control circuit 20b changes from on to off,
The NMOS FET 26 of the NMOS control circuit 20b changes from off to on.

As a result, the output signal of the second PMOS control circuit 20a changes from "L" to "H", but the output signal of the second NMOS control circuit 20b remains "L". As a result, as shown in the period B, the current source PMOS FET 31 of the output buffer circuit 30 is driven to change from the on state to the off state, but the current sink NMOS FET 32 of the output buffer circuit 30 is turned off. Therefore, the output terminal 52 remains "H". At this time, no through current flows.

Next, as shown in a period C, the input signal is "
At the time of "H", as shown in FIG.
The potential “H” of the source node of the NMOS FET 22a is set to the first NMO
The feedback to the gate of the PMOS FET 13 of the S control circuit 10b
S FET13 changes from off to on. Also, the second NMOS
The potential “H” of the source node of the PMOS FET 27 of the control circuit 20b is fed back to the gate of the PMOS FET 12 of the first PMOS control circuit 10a, and the PMOS FET 12 changes from on to off.

As a result, the signal at the output node of the first control circuit 10 changes from "H" to "L", and the second PMOS control circuit 20
The NMOS FET 22 of a changes from on to off, and the PMOS FET 21 of the second PMOS control circuit 20a changes from off to on,
The output signal of the second PMOS control circuit 20a remains at "H", and the PMOS FET 31 for discharging current of the output buffer circuit 30.
Remain off.

As described above, when the signal at the output node of the first control circuit 10 changes from "H" to "L", the second NM
The NMOS FET 28 of the OS control circuit 20b changes from on to off,
The PMOS FET 27 of the second NMOS control circuit 20b changes from off to on, and the output signal of the second NMOS control circuit 20b changes from "L" to "H".

As a result, the current sink NMOS FET 32 of the output buffer circuit 30 is driven to change from the off state to the on state, and the output terminal 52 changes from "H" to "L". At this time, almost no through current flows.

Next, as shown in period D, the input signal
When the signal changes from "H" to "L", as shown in FIG.
The PMOS FET 11 of the MOS control circuit 10a changes from off to on, and the NMOS FET 14 of the first NMOS control circuit 10b changes from on to off. The NMOS of the second PMOS control circuit 20a
The FET 23 changes from on to off, and the second PMOS control circuit 20
The NMOS FET 24a changes from off to on, the PMOS FET 26 of the second NMOS control circuit 20b changes from on to off,
The NMOS FET 25 of the NMOS control circuit 20b changes from off to on.

As a result, the output signal of the second PMOS control circuit 20a remains "H", but the second NMOS control circuit 20b
Changes from “H” to “L”. Accordingly, as shown in the period E, the current discharging PMOS FET 31 of the output buffer circuit 30 remains in the off state, but the current sinking NMOS FET 32 of the output buffer circuit 30 changes from the on state to the off state. And the output terminal 52 remains "H". At this time, no through current flows.

Next, as shown in period F, the input signal
At the time of "L", as shown in FIG. 2, the potential "L" of the source node of the NMOS FET 22 of the second PMOS control circuit 20a becomes the first potential.
The feedback to the gate of the PMOS FET 13 of the NMOS control circuit 10b
The PMOS FET 13 changes from off to on. Also, the second NM
The potential “H” of the source node of the PMOS FET 27 of the OS control circuit 20b
Returns to the gate of the PMOS FET 12 of the first PMOS control circuit 10a, and this PMOS FET 12 changes from on to off.

As a result, the signal at the output node of the first control circuit 10 changes from "L" to "H", and the second NMOS control circuit 20
The PMOS FET 21 of a changes from on to off, and the NMOS FET 22 of the second NMOS control circuit 20a changes from off to on.
The output signal of the second NMOS control circuit 20a remains "L", and the NMOS FET 32 for sinking current of the output buffer circuit 30
Remain off.

When the signal at the output node of the first control circuit 10 changes from "L" to "H" as described above, the second PM
The NMOS FET 22 of the OS control circuit 20a changes from on to off,
The PMOS FET 21 of the second PMOS control circuit 20a changes from off to on, and the output signal of the second PMOS control circuit 20a changes from "H" to "L".

As a result, the PMOS FET 31 for discharging current of the output buffer circuit 30 is driven to change from the off state to the on state, and the output terminal 52 changes from "L" to "H". At this time, almost no through current flows.

As described above, when the first control circuit 10 and the second control circuit 20 push-pull drive the CMOS FET of the output buffer circuit 30, the FE in one of the ON states of the CMOS FET is turned on.
The control is performed so that the other off-state FET is turned on after T is turned off. At this time, when the logic level of the input signal changes to a fixed state after the transition, the second control circuit 20 performs feedback control of the first control circuit 10. As a result, there is no period during which the CMOS FETs of the output buffer circuit 30 are simultaneously ON, and no current flows through the CMOS FET between the VCC node and the GND node.

<Modification> In the output circuit shown in FIG. 1, the connection node switching control circuit 20c inverts the input signal by one inverter circuit 41 and then switches the second PMOS control circuit 20c.
a NMOS FET 24 and the PMOS F of the second NMOS control circuit 20b
Although a common supply is provided to each gate of the ET 26, a modified embodiment as shown in FIG. 7 is also possible.

That is, the connection node switching control circuit shown in FIG. 7 inverts the input signal by the first inverter circuit 42 and thereafter supplies the inverted signal to the gate of the NMOS FET 24 of the second PMOS control circuit 20a, and the input signal And then supplied to the gate of the PMOSFET 26 of the second NMOS control circuit 20b.

In FIG. 7, the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0056]

As described above, according to the present invention, the CMOS F
Even when the size of the ET is large, it is possible to provide a semiconductor integrated circuit including a CMOS-structure output circuit capable of suppressing a through current and suppressing an increase in current consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of an output circuit having a CMOS configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram in which the source and the drain of the FET which is turned on when the input signal of the output circuit of FIG. 1 is “L” are short-circuited with a thick line.

FIG. 3 is a circuit diagram in which the source and drain of the FET that is turned on when the input signal of the output circuit of FIG. 1 changes from “L” to “H” are short-circuited with a thick line.

FIG. 4 is a circuit diagram in which the source and the drain of the FET which is on when the input signal of the output circuit of FIG. 1 is “H” are short-circuited with a thick line.

FIG. 5 is a circuit diagram in which the source and drain of the FET that is turned on when the input signal of the output circuit of FIG. 1 changes from “H” to “L” are short-circuited with a thick line.

FIG. 6 is a waveform chart showing an operation example of the output circuit of FIG. 1;

FIG. 7 is a circuit diagram showing a modification of the connection node switching control circuit in FIG. 1;

FIG. 8 is a circuit diagram showing an example of a conventional CMOS CMOS output circuit.

9 is a waveform chart showing an operation example of the output circuit of FIG.

FIG. 10 is a waveform diagram showing a situation in which a through current flows in a process in which the level of the input signal of the output buffer circuit changes in the operation example shown in FIG. 9;

[Explanation of symbols]

 1 ... first control output node, 2 ... second control output node, 3,4 ... output node, 10 ... first control circuit, 10a ... first PMOS control circuit, 10b ... first NMOS control circuit, 11 ... first PMOS FET, 12 ... second PMOS FET, 14 ... first NMOS FET, 13 ... second NMOS FET, 20 ... second control circuit, 20a ... second PMOS control circuit, 20b ... 2nd NMOS control circuit, 20c ... connection node switching control circuit, 21 ... 3rd PMOS FET, 22 ... 3rd NMOS FET, 23 ... 4th NMOS FET, 24 ... 5th NMOS FET, 25 ... 5 PMOS FETs, 26 ... fourth PMOS FETs, 27 ... sixth PMOS FETs, 28 ... sixth NMOS FETs, 30 ... output buffer circuits, 31 ... PMOS FETs for discharging current, 32 ... for sinking current NMOS FET, 41… Inverter circuit, 51… Input terminal, 52… Output terminal.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J055 AX27 AX47 AX55 AX64 BX16 CX24 DX22 EX07 EY21 FX12 GX01 5J056 AA04 BB17 BB19 DD28 DD29 FF08 GG10 KK01

Claims (4)

[Claims] A first control circuit to which a signal supplied from an internal circuit is input; an output signal of the first control circuit and a signal supplied from the internal circuit being input; A second control circuit that feeds back to the first control circuit and outputs two output signals from two output nodes having different rising timings and falling timings and different periods of the same logic level from two output nodes; An output buffer circuit in which each drain of a current-sinking PMOS FET and a current-sinking NMOS FET in which two output signals of the control circuit are supplied to a gate corresponding to the two output signals is connected to an output terminal; The control circuit is configured so that the logic level of the signal supplied from the internal circuit and the logic level of the potential fed back from the two control output nodes of the second control circuit satisfy a predetermined condition. The logic level of the output signal when the plus is determined, the output signal of the second control circuit PM for discharging the current
A semiconductor integrated circuit characterized in that one of an OS FET and a current-sinking NMOS FET is controlled so that an on-state FET is inverted to an off-state and then the other off-state FET is turned on. 2. A first control circuit comprising: a first PMOS FET having a source connected to a power supply node; and a second PMOS FET having a source connected to a drain of the first PMOS FET. A PMOS control circuit, and a first NMOS control circuit including a first NMOS FET having a source connected to the ground node and a second NMOS FET having a source connected to the drain of the first NMOS FET; The gates of the first PMOS FET and the first NMOS FET are connected in common, and the second PMOS FET and the second NM
2. The semiconductor integrated circuit according to claim 1, wherein the drains of the OS FET are connected in common to form an output node. 3. The second control circuit includes: a third PMOS FET having a source connected to a power supply node; a gate connected to the third PMOS FET; a drain connected to the third PMOS FET; Third NMOS F to be a node
ET, a fourth NMOS FET connected between a power supply node between the drain and source and the first control output node, and a fourth NMOS FET connected between the drain and source between the first control output node and the ground node. A fifth NMOS FET connected to the first control circuit, the signal of the output node of the first control circuit being commonly input to each gate of the third PMOS FET and the third NMOS FET, and the first control output The potential of the node is the second potential of the first NMOS control circuit.
And the output signal of the drain connection node of the third PMOS FET and the third NMOS FET is input to the gate of the current-sinking PMOS FET of the output buffer circuit. A control circuit, a sixth NMOS FET having a source connected to the ground node, and a sixth PMOS FET having the sixth NMOS FET connected to the gate and the drain and the source being a second control output node.
ET, a fourth PMOS FET having a source / drain connected between the power supply node and the second control output node, and a source / drain having a connection between the second control output node and the ground node. And a fifth PMOS FET connected to the second control output terminal. The signal of the output node of the first control circuit is commonly input to each gate of the sixth PMOS FET and the sixth NMOS FET. The potential of the node is the second potential of the first PMOS control circuit.
And the output signals of the drain connection nodes of the sixth PMOS FET and the sixth NMOS FET are input to the gate of the current sink NMOS FET of the output buffer circuit. A control circuit, a signal supplied from the internal circuit is input, and the input signal is supplied to the gate of the fourth NMOS FET of the second PMOS control circuit and the gate of the fifth PMOS FET of the second NMOS control circuit. Connected to the gate of the fifth NMOS FET of the second PMOS control circuit and the gate of the fourth PMOS FET of the second NMOS control circuit. 3. The semiconductor integrated circuit according to claim 1, further comprising a control circuit. 4. The semiconductor integrated circuit according to claim 3, wherein a signal obtained by inverting the input signal by one inverter circuit is commonly used as the inverted signal of the input signal.