JP2003051741A - Buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buffer circuit that can reduce the power consumption by suppressing an unnecessary through-current flowing between a power supply and a GND during the transition period of an input signal. SOLUTION: Inverter sections N1, P1 for generating an output signal are provided with transistor (TR) circuits N2 to N5, and P2 to P5 for suppressing supply for power of a power supply or ground in a direction reverse to the direction of the output signal according to the transition direction of an input signal and with a delay circuit 10 that controls the supply of power only for a prescribed period during the input transition period. The delay circuit 10 is configured by using e.g. a Schmitt trigger circuit, which automatically detects the end of the input signal transition period and controls the supply of power so as to be restored to the usual power supply state as soon as the transition period is finished. Thus, an unnecessary through-current caused in the operation of the buffer circuit can effectively be suppressed and the power consumption of the buffer circuit can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit for generating an output signal for an input signal through an inverter section.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of LSIs, the internal delay of the LSI is such that the wiring delay accounts for a larger proportion of the gate delay of each circuit element. On the other hand, the wiring length is also increasing due to the increase in the chip size accompanying the higher integration of LSI, and in order to reduce the wiring delay, a buffer circuit with a larger driving capacity is used when driving a wiring with a large load. In many cases, the speed is increased.

[0003]

However, when a buffer circuit is provided in a conventional LSI, the current consumed by the circuit is the charge / discharge current of the wiring load and the power supply-GND of the buffer circuit during the transition period of the signal line. Unnecessary through current components flowing in the circuit also increase, which is an obstacle to lowering the power consumption of the circuit.

Therefore, an object of the present invention is to suppress unnecessary through current flowing between the power supply and GND during the transition period of the signal line,
It is an object of the present invention to provide a buffer circuit capable of reducing the power consumption of the circuit.

[0005]

In order to achieve the above object, the present invention is a buffer circuit for generating an output signal for an input signal through an inverter section, the operation of which is controlled by the input signal, And a transistor that limits the power supply of either the power supply or the ground, which is the opposite level to the output signal according to the transition direction of the input signal, and delays the input signal that matches the delay of signal transmission during the input transition period. As a result, an input signal delay circuit for controlling the operation of the transistor is provided.

In the buffer circuit of the present invention, the inverter section for generating the output signal is provided with the transistor for suppressing the power supply of either the power supply or the ground which is in the opposite direction to the output signal according to the transition direction of the input signal. By controlling the transistor with a delay circuit, the power supply is controlled only during a certain period of the input transition period, and the shoot-through current flowing between the power source and the ground during the transition period is suppressed. Therefore, it is possible to effectively suppress unnecessary shoot-through current that occurs during the operation of the buffer circuit,
Low power consumption is possible.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below are preferred specific examples of the present invention, and various technically preferable limitations are given. However, the scope of the present invention is not limited to the present invention in the following description. Unless otherwise stated, the present invention is not limited to these embodiments. The buffer circuit of this example is composed of CMOS, and receives a change in the transition state from an input signal and suppresses a through current that flows between the power supply and the ground during the transition period.
The inverter circuit that generates the output signal is provided with a transistor circuit that suppresses the power supply to either the power supply or the ground, which is in the opposite direction to the output signal according to the transition direction of the input signal. Only a delay circuit for controlling the power supply can be controlled.

FIG. 1 is a circuit diagram showing a concrete configuration example of a buffer circuit according to an embodiment of the present invention. This buffer circuit includes a plurality of CMOS transistors and a delay circuit 10.
And transistors N1, N2, N in the figure
3, N4, N5 are NMOS transistors, and the transistors P1, P2, P3, P4, P5 are PMOS transistors. And the two transistors N1 and P1
Is a first transistor circuit section that constitutes an inverter section similar to the conventional one, and includes four transistors N2, N3, and P.
Reference numerals 2 and P3 are second transistor circuit portions that operate so as to suppress a shoot-through current of the transistors N1 and P1.
Also, the four transistors N4, N5, P4, P5 are
Depending on the transition direction of the input signal, the transistors N2, N3,
It is a third transistor circuit unit that controls ON / OFF of P2 and P3. The delay circuit 10 outputs a delay signal having a predetermined delay time based on the input signal.

An input signal (IN) is connected to the gates of the two transistors N1 and P1 forming the inverter section, and the transistors N2 and N3 and the transistors P2 and P3 are connected in parallel to the sources of the transistors N1 and P1, respectively. , The sources of the transistors N2 and N3 are connected to the ground (GND), and the transistor P
A power source is connected to the sources of 2 and P3. here,
The current capability of the transistors N3 and P3 is the same as that of the transistor N.
It is smaller than the current capacity of the transistors 1, N2 and the transistors P1, P2. The gate of the transistor N2 is connected to the drains of the transistors N5 and P5, and the gate of the transistor P2 is connected to the drains of the transistors N4 and P4. Furthermore, the transistor N5,
The source of P4 is connected to the input signal (IN), and the gates of the transistors N3, N4, N5, P4 and P5 are connected to the output of the delay circuit (DCR) 10 which delays the input signal.

Next, the operation of the buffer circuit having the above configuration will be described. First, when the input is in the L level steady state, the transistors P1, P3, P4, P
5, N2 is ON, transistors N1, N3, N4, N5
Is off. Since the transistor P4 is interposed between the gate of the transistor P2 and the input signal, the transistor P2 has a voltage shifted from the L level of the input signal by the base effect of the transistor P4. is not. Similarly, when the input is in the H level steady state, the transistors N1, N3, N4, N5, and P2 are on, and the transistors P1, P3, P4, and P5 are off. Since the transistor N2 has the transistor N5 between the gate and the input signal,
The voltage has been shifted from the H level of the input signal by the base effect of the transistor N5, and has not been completely turned on.

Next, consider a state in which the input signal transits from the L level to the H level. At this time, the transistors P1 and P
2 changes from ON to OFF, and transistor N1 is OF
Change from F to ON. Here, the transistor P2 changes from the incomplete ON state to the OFF state, and the transistor P3 continues to be in the ON state for a certain period after the change of the input signal by the delay circuit 10, but the current capacity of the transistor P3 is the transistor. Since it is smaller than the current capacity of P1, the through current flowing from the transistor P1 side to the transistor N1 side during the switching period of the transistors P1 and N1 is limited by the transistors P2 and P3. The transistors P2 and P3 maintain this state in accordance with the delay time of the delay circuit 10 and, after transitioning to the H level,
The transistor P2 is turned on and the transistor P3 is turned off.

Next, similarly to this, consider a state in which the input signal transits from the H level to the L level. At this time, the transistors N1 and N2 change from ON to OFF, and the transistor P1 changes from OFF to ON. Transistor N
2 changes from an incomplete ON state to OFF, and the transistor N3 continues to be in the ON state for a certain period after the change of the input signal by the delay circuit 10, but since it is smaller than the current capacity of the transistor N1, P1,
The through current flowing from the transistor P1 side to the transistor N1 side during the switching period of N1 is the transistor N1.
2, limited by N3. The transistors N2 and N3 maintain this state in accordance with the delay time of the delay circuit 10 and, after transitioning to the L level, the transistor N2 is turned on.
And the transistor N3 is turned off. The delay time created by the delay circuit may be set so as to generate a delay longer than the transition period of the input signal received by the buffer circuit.

As described above, in the buffer circuit of this example,
It is possible to suppress an unnecessary shoot-through current flowing between the power supply and the ground during the transition period in response to a change in the transition state from the input signal without affecting the speedup. Therefore, the power consumption of the buffer circuit can be reduced.
It should be noted that the addition of such a configuration does not affect the speedup, and is particularly effective when the waveform of the input signal is largely rounded.

As another example of the present invention, a delay circuit for suppressing the power supply for a certain period is constituted by using a Schmitt trigger circuit, and automatically detects the end of the transition period of the input signal. Then, at the same time as the end of the transition period, control may be performed so as to return to the normal power supply state. FIG. 2 is a circuit diagram showing a configuration example of a Schmitt trigger circuit that can be used as the delay circuit described above. Here, the transistors N11, N12, and N13 are NMOS transistors, and the transistors P11, P12, and P1.
3 indicates a PMOS transistor. Further, the transistor N11 has a larger current capacity than the transistors N12 and N13, and the transistor P11 also has a larger current capacity than the transistors P12 and P13.

Further, the portions surrounded by broken lines A and B respectively constitute an inverter section, and the inverter section A is composed of transistors P11 and N11, and the inverter section B.
Is composed of transistors P12, P13, N12 and N13. The transistors P12 and P13 are connected in series between the power source and the output of the inverter unit B, only the gate of the transistor P13 is connected to the input of the inverter unit B, and the gate of the transistor P12 is grounded.
It is connected to the. Also, the transistors N12 and N13
Are connected in series between the ground GND and the output of the inverter section B, only the gate of the transistor N13 is connected to the input of the inverter section B, and the gate of the transistor N12 is connected to the power supply. The two inverter units A and B form a latch circuit. The input of the inverter unit A is connected to the input signal (IN), the output is connected to the output signal (OUT), and the input of the inverter unit B is It is connected to the output signal (OUT) and the output is connected to the input signal (IN).

In the circuit having the above configuration, the input / output characteristic has the hysteresis characteristic as shown in FIG. 3, and when the input signal changes from the L level to the H level, the logical threshold value is a normal value. It is higher than 1/2 of the power supply voltage which is the logic threshold of the inverter circuit, and conversely, when changing from the H level to the L level, the logic threshold becomes lower than 1/2 of the power supply voltage. Further, the logical threshold level of this circuit can be freely adjusted by adjusting the relationship between the drive capacity of the inverter section A and the drive capacity of the inverter section B.

By using the Schmitt trigger circuit having such a configuration so that the end of the transition period can be detected, it is possible to realize a circuit that suppresses the shoot-through current in conjunction with the waveform of the input signal. In particular, in such a configuration, since the input level of the input signal is automatically detected, when the transition time of the input signal is not constant, that is,
By applying it to the portion where the slope of the input waveform of the input signal changes arbitrarily, there is an advantage that the suppression of the shoot-through current can be controlled more reliably. The buffer circuit according to the present invention is not limited to the configuration shown in FIG. 1 and FIG. 2, and various modifications can be made without departing from the gist of the present invention.

[0018]

As described above, according to the buffer circuit of the present invention, either the power supply or the power supply, which is in the opposite direction to the output signal according to the transition direction of the input signal, is supplied to the inverter section for generating the output signal. A transistor that suppresses power supply is provided, and by controlling this transistor with a delay circuit, the power supply is controlled only for a certain period of the input transition period, and the power supply generated during the transition period is controlled.
The through current flowing between the grounds is suppressed. Therefore, there is an effect that an unnecessary shoot-through current generated during the operation of the buffer circuit can be effectively suppressed and the power consumption of the buffer circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a buffer circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a Schmitt trigger circuit that can be used in a buffer circuit according to another embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of input signals and output signals of the Schmitt trigger circuit shown in FIG.

[Explanation of symbols]

N1, N2, N3, N4, N5 ... NMOS transistor, P1, P2, P3, P4, P5 ... PMOS transistor, 10 ... Delay circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5J055 AX27 AX55 AX64 BX16 CX24                       DX22 DX56 DX72 DX83 EX01                       EX07 EX21 EY22 EZ07 EZ50                       FX12 FX17 FX35 GX01                 5J056 AA04 BB19 CC05 CC11 DD13                       DD29 EE03 EE07 EE11 FF08                       GG03

Claims (6)

[Claims] 1. A buffer circuit for generating an output signal with respect to an input signal through an inverter unit, the operation of which is controlled by the input signal, and the level of which is opposite to that of the output signal according to the transition direction of the input signal to the inverter unit. A transistor circuit that limits the supply of either power or ground, and a delay of the input signal that controls the operation of the transistor circuit by delaying the input signal that matches the delay in signal transmission during the input transition period. A buffer circuit comprising: a circuit; 2. The delay circuit is a circuit that automatically detects the end of a transition period of an input signal and controls to return to a normal power supply state at the same time as the end of the transition period. The buffer circuit according to item 1. 3. The buffer circuit according to claim 2, wherein a Schmitt trigger circuit is used as the delay circuit. 4. A first transistor circuit portion constituting the inverter portion, a second transistor circuit portion for suppressing a through current of the first transistor circuit portion, and an input signal for the second transistor circuit portion. 3. The buffer circuit according to claim 1, further comprising a third transistor circuit section that performs on / off control in accordance with the transition direction of the. 5. The buffer circuit according to claim 4, wherein each of the transistors forming each of the transistor circuit portions is a MOS transistor. 6. The buffer circuit according to claim 1, wherein the delay circuit generates a delay longer than a transition period of an input signal.