JP2002151701A - Thin-film transistor and liquid-crystalline display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the characteristics of a polycrystalline silicon thin-film transistor. SOLUTION: The internal stress of a gate insulating film is set at -100 to 500 Mpa. Thus, the interface defect with a polycrystalline silicon, which is a semiconductor layer, is reduced, and a thin-film transistor with improved on-characteristics is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor applied to a liquid crystal display device, an image sensor and the like,
And a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, a liquid crystal display device is mounted on a viewfinder of a home video camera, a notebook computer, and the like. Of these liquid crystal display devices,
Active matrix type liquid crystal display devices capable of high image quality display have received particular attention. In the active matrix type liquid crystal display device, a thin film transistor (hereinafter, also referred to as “TFT”) is often used as a switching element of a pixel electrode. Such a conventional TFT is described in, for example, “AM-LCD94 DIGEST”.
OF TECHNICAL PAPERS "
It is described on page 0 to page 103. Below, the conventional T
FIG. 1 is a schematic sectional view showing an example of the structure of the FT. FIG.
The structure shown in is called a top gate type coplanar structure,
First, a source / drain region 3 and a semiconductor layer 2 are formed on a glass substrate 1, and a gate insulating film 4 is formed thereon. Further, a gate electrode 5 is formed thereon, and source / drain regions are formed in connection with the semiconductor layer 2.
A TFT is formed by forming an interlayer insulating film 6, a contact hole (not shown), and a source / drain electrode 7. In addition, for example, there is a top-gate type staggered structure.

[0003]

In the conventional TFT having the above-mentioned structure, SiO ₂ or the like formed by the LPCVD method is used particularly as the gate insulating layer. However, the transistor having the above configuration has a problem that required transistor performance such as sub-threshold characteristics, mobility, and on-current may not be obtained in some cases. Although the detailed cause of such a problem is not well understood, it is considered that the cause is largely due to an interface defect between the semiconductor layer and the gate insulating film. Accordingly, an object of the present invention is to provide a thin film transistor having improved sub-threshold characteristics and on-state characteristics such as on-state current in view of the conventional problems.

[0004]

According to the present invention, a semiconductor layer made of polycrystalline silicon and an internal stress of -100 to 50 are provided.
The present invention relates to a thin film transistor having a gate insulating film of 0 MPa. In this thin film transistor, it is particularly effective that the internal stress of the gate insulating film located within 50 nm from the semiconductor layer is -100 to 500 MPa. Further, the internal stress of the semiconductor layer is 0 to 2000MPa.
a is effective. Further, the gate insulating film is made of S
It is effective to consist of iO ₂ . Further, the present invention relates to a liquid crystal display device using the above-mentioned thin film transistor.

[0005]

The present invention solves the above-mentioned problems by using a polycrystalline silicon TFT in which the internal stress of the gate insulating film is in the range of -100 to 500 MPa.
Here, the internal stress in the present invention is a compressive stress when its value is negative, and a tensile stress when its value is positive. Further, the internal stress is:
It can be obtained by a conventionally known method, for example, in the case of forming a film on a substrate having known properties such as Young's modulus,
It can be obtained by measuring the amount of change in the warpage of the substrate before and after forming a film. The present invention controls the internal stress of the gate insulating film as described above,
This is to improve the characteristics of the TFT by reducing the interface defect between the semiconductor layer and the gate insulating film. Hereinafter, the operation will be described.

The conventional TFT has a problem that required transistor performance may not be obtained in subthreshold characteristics, mobility, threshold voltage, and the like. The exact cause of this problem is not well understood,
This is considered to be largely due to interface defects between the semiconductor layer and the gate insulating film. That is, the mismatch between the internal stress of the semiconductor layer and the internal stress of the gate insulating film induces interface defects and causes the TFT to fail.
It is considered that the characteristics of Because internal stress is usually tensile stress of polycrystalline silicon used as a semiconductor layer (-) a is whereas, since the internal stress of the SiO ₂ used for the gate insulating film is generally compressive stress (+) It is.

For example, in the case of polycrystalline silicon formed by crystallization by laser irradiation, molten silicon is rapidly cooled by laser irradiation and polycrystallized in a non-thermal equilibrium state. For example, it is considered to have a tensile stress of about 1000 MPa. Also, for example, even when amorphous silicon is crystallized in a solid phase by a heat treatment at about 600 ° C., polycrystalline silicon has a tensile strength due to a difference in thermal expansion coefficient between silicon and a base material such as glass or quartz. It will have internal stress. On the other hand, a dense film with few defects is required as the gate insulating film in order to emphasize the reliability of the obtained TFT and the like. In the case of a gate insulating film made of SiO ₂ , for example, about 300 MPa Often has compressive stress.

That is, at the interface between the semiconductor layer and the gate insulating film, it is considered that an interface defect is induced due to a difference in internal stress between the two and the TFT characteristics are degraded. Also,
Usually, since polycrystalline silicon is composed of crystal grains and crystal grain boundaries which are interfaces between the grains, it is conceivable that local defects in the polycrystalline silicon are induced by the influence of stress. Therefore, the present inventors have found that by controlling the internal stress of the gate insulating film, interface defects between the semiconductor layer and the gate insulating film can be reduced and the characteristics of the TFT can be improved. It has been reached.

The TFT according to the present invention is characterized in that the internal stress of the gate insulating film is in the range of -100 to 500 MPa, and the semiconductor layer and the gate insulating film are controlled by controlling the stress of the gate insulating film. Has the effect of reducing the interface defects and improving the characteristics of the thin film transistor. Further, the present invention provides that the internal stress of the gate insulating film within 50 nm from the polycrystalline silicon side is -100 to 500 MPa.
And has a function of improving the characteristics of the thin film transistor by controlling stress in the vicinity of the interface between the particularly important semiconductor layer and the gate insulating film.

The TFT according to the present invention as described above can be manufactured by a conventional method. (1) Formation of Precursor of Semiconductor Layer First, in order to manufacture a TFT according to the present invention, a film of a precursor of a semiconductor layer (for example, amorphous silicon) is formed on a substrate. There is no particular limitation on the method used to form a predetermined silicon film, and examples thereof include a plasma CVD method, a low pressure CVD method, a sputtering method, a vacuum evaporation method, and a photo CVD method. The substrate used in the present invention is not particularly limited as long as it has an insulating surface, and examples thereof include a glass substrate, a plastic substrate, a crystalline silicon substrate having silicon oxide formed on the surface, and a metal plate. If necessary, the film made of the precursor is processed into a desired shape by photolithography and / or etching.

(2) Heat Treatment Next, it is preferable that the precursor of the semiconductor layer is subjected to a heat treatment before crystallization. This is to reduce the hydrogen content in the amorphous silicon and prevent the silicon film from being damaged due to bumping of hydrogen in the subsequent crystallization step. As a method of this heat treatment, for example, a heat treatment by laser irradiation can be mentioned, but the hydrogen concentration in the precursor is sufficiently low from the beginning,
If there is no damage to the silicon film during laser irradiation, there is no need to perform heat treatment.

(3) Polycrystallization In order to crystallize a precursor made of amorphous silicon into a semiconductor layer made of polycrystalline silicon, there is no particular limitation as long as the precursor can be crystallized. However, for example, a XeCl laser beam irradiation method, an Ar ion laser beam irradiation method, an annealing method in a furnace, and the like can be given. (4) Formation of gate insulating film Next, a gate insulating film is manufactured. In the present invention, the gate insulating film has an internal stress of -100 to 500 MPa.
The insulating film is not particularly limited as long as the insulating film is, for example, SiO ₂ or SiNx. Further, such a gate insulating film can be formed by, for example, plasma CVD, low-pressure CVD, sputtering, ECR-CVD, plasma oxidation, high-pressure oxidation, or the like. In particular, the internal stress can be controlled by controlling various parameters relating to film forming conditions such as a substrate temperature, a discharge power, and a distance between electrodes.

For example, when a film made of SiO ₂ is formed by decomposing and reacting a mixed gas of tetraethoxysilane and oxygen by a plasma CVD method as a gate insulating film, it is necessary to increase the distance between electrodes, By reducing and / or increasing the gas pressure, the internal stress can be made positive. Specifically, the internal stress can be changed from -300 MPa to 100 MPa by setting the distance between the electrodes from 13 mm to 25 mm. Above all, in order to control the internal stress, at least tetraethoxysilane (Si (OC
₂ H _{5) 4,} preferably constituted by SiO ₂ formed by plasma CVD using a gas containing tetraethoxysilane). By forming the gate insulating film with SiO ₂ formed from tetraethoxysilane using such a method, it is possible to form SiO ₂ on a large-area substrate at low temperature, This is because there is a reason that the stress of the obtained gate insulating film can be controlled by adjusting various parameters.

(5) Formation of Gate Electrode The gate electrode is not particularly limited and may be a conventional one. For example, Ta, Al, Mo, Ti or Cr, or an alloy metal containing these as a main component Is raised. If necessary, the film made of the precursor is processed into a desired shape by photolithography and / or etching. (6) Formation of Source / Drain Region Next, using the gate electrode as a mask, a predetermined element is introduced into at least a part of the semiconductor layer to form a source / drain region. This method is not particularly limited as long as it can introduce a predetermined element, and examples thereof include an ion doping method, an ion implantation method, and a plasma doping method. As an element to be introduced for forming the source / drain regions, an n-channel thin film transistor may be used as long as it functions as a donor such as phosphorus or arsenic. May be used as long as it works as an acceptor such as aluminum or boron.

(7) Formation of interlayer insulating film Next, an interlayer insulating film is provided to insulate the gate electrode from the source / drain electrodes. Interlayer insulating film, for example, atmospheric pressure CVD, low pressure CVD method, a plasma CVD method, can be formed by a film formation method such as sputtering, or ECR-CVD method, as the material, SiO _2, silicon nitride or oxide Tantalum and the like can be mentioned. (8) Formation of Source / Drain Electrodes Next, a source electrode and a drain electrode are provided in portions corresponding to the source / drain regions. Examples of a material forming these electrodes include metals such as titanium, chromium, tantalum, molybdenum, and aluminum, polycrystalline silicon doped with a large amount of impurities, and ITO. (9) Annealing treatment In order to reduce defects in the semiconductor layer, annealing treatment is performed. Examples of the annealing method include a heat treatment in a hydrogen atmosphere, a plasma treatment in a hydrogen atmosphere, and the formation of a protective film made of SiNx and a subsequent heat treatment.

In the above steps (1) to (9) for fabricating the TFT according to the present invention, the substrate temperature and the like are heated as necessary. In the present invention, the maximum temperature in each step is set to 700 ° C. The following may be sufficient, but 600
C. or lower is preferred. This is because the practical heat-resistant temperature of a low-cost glass substrate is about 600 ° C., and the change in the internal stress of the gate insulating film due to the thermal process can be reduced by lowering the maximum temperature of the process. . Further, by using the thin film transistor according to the present invention, an excellent liquid crystal display device can be obtained. In this case, the thin film transistor may be used as a switching element of a pixel, or a circuit necessary for driving the thin film transistor of the pixel may be formed using the thin film transistor.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the drawings by using embodiments, but the present invention is not limited to these embodiments. Example 1 In this example, a thin film transistor having the structure shown in FIG. 1 was manufactured. First, on the glass substrate 1,
As a precursor of the semiconductor layer 2, an amorphous silicon film having a thickness of 50 nm was formed by a plasma CVD method, and processed into an island shape using photolithography and etching. Next, heat treatment was performed at 450 ° C. for 1 hour to reduce the hydrogen content in the amorphous silicon. This is to prevent the silicon film from being damaged due to bumping of hydrogen in the next crystallization step. Then, XeCl laser having a wavelength of 308 nm was irradiated at an energy density of about 300 mJ / cm ² to crystallize the amorphous silicon to form polycrystalline silicon as the semiconductor layer 2. Further, as a gate insulating film 4, tetraethoxysilane = 2 is formed by plasma CVD.
00 sccm, oxygen = 2700 sccm, pressure 2 Torr
r, distance between electrodes 25 mm, discharge power density = 0.4 W / c
By forming a film under the conditions of m ² and a substrate temperature of 330 ° C., a 100 nm thick Si film having a tensile stress of about 100 MPa
O ₂ was formed.

Next, as the gate electrode 5, a film thickness of 200 n
m of Ta was formed by a sputtering method and processed by photolithography and etching. Using the gate electrode 5 as a mask, phosphorus serving as a donor was introduced into a partial region of the semiconductor layer 2 to form the source / drain region 3. At this time, for example, a method in which a gas is decomposed by high-frequency discharge plasma to generate ions containing at least an element to be introduced, and the ions are accelerated by an accelerating voltage without mass separation and introduced into the active semiconductor thin layer (ion Doping method) to introduce phosphorus as a donor using a phosphine gas diluted with hydrogen gas to obtain about 4
The impurities were sufficiently activated by the heat treatment at 50 ° C.
Then, a 300 nm-thick SiO ₂ film was formed as the interlayer insulating film 6 by a normal pressure CVD method, and then a contact hole was formed by photolithography and etching. Further, the source / drain electrode 7 has a thickness of 70
A 0 nm Ti film was formed and processed. Then, the semiconductor layer 2
In order to reduce the defects, a thin film transistor according to the present invention was completed by performing a heat treatment at 300 ° C. for 1 hour in a hydrogen atmosphere of 1 Torr.

[Evaluation] The thin-film transistor obtained as described above was evaluated for its effect of improving thin-film transistor characteristics. The results are shown in FIG. Here, the gate insulating film has a two-layer structure, and by adjusting the above conditions, the first gate insulating film having an internal stress of +100 MPa is formed on the gate electrode 5 side, and the internal stress is formed on the semiconductor layer 2 side. -300M
A second gate insulating film of Pa was formed. That is, FIG.
Shows the relationship between the configuration of the gate insulating film (the thickness of the first gate insulating film and the thickness of the second gate insulating film) and the subthreshold characteristics of the thin film transistor. FIG. 2 shows that the subthreshold characteristics are improved when the thickness of the second gate insulating film having an internal stress of −300 MPa is increased. Further, the internal stress of the gate insulating film located within 50 nm from the semiconductor layer 2 is increased by +100 MP
It can be seen that by setting a, the subthreshold characteristic can be improved. That is, when the SiO ₂ film is formed in a laminated shape, for example, 50 n from the polycrystalline silicon side
It can be seen that the sub-threshold characteristic is improved by controlling the internal stress of the gate insulating film within m.
FIG. 3 shows a case where the gate insulating film is constituted by a single layer.
4 shows the relationship between internal stress and subthreshold characteristics. FIG.
As shown in (1), by setting the internal stress of the gate insulating film of the thin film transistor in the range of -100 to 500 MPa, there is an effect that the subthreshold characteristic is improved.

Example 2 Using the thin film transistor manufactured in Example 1, the thin film transistors were arranged in a matrix on a glass substrate so as to function as a switching element of a pixel electrode of a liquid crystal display device. Next, a liquid crystal was sealed between the glass substrate and the opposing substrate to produce a liquid crystal display device. According to the liquid crystal display device according to Example 2 manufactured as described above, the characteristics of the thin film transistor are improved by setting the internal stress of the gate insulating film of the thin film transistor to the range of -100 to 500 MPa. , A liquid crystal display device with little change was obtained.

[0021]

According to the present invention, by setting the internal stress of the gate insulating film in the range of -100 to 500 MPa, interface defects with the polycrystalline silicon as the semiconductor layer are reduced, and the characteristics of the thin film transistor are improved. An effective effect is obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a thin film transistor.

FIG. 2 is a graph showing a relationship between a configuration of a gate insulating film and a subthreshold characteristic of a thin film transistor.

FIG. 3 is a graph showing a relationship between internal stress of a gate insulating film and subthreshold characteristics of a thin film transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Semiconductor layer 3 Source / drain area 4 Gate insulating film 5 Gate electrode 6 Interlayer insulating film 7 Source / drain electrode

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Ikunori Kobayashi 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Term (Reference) 2H092 JA25 KA04 KA12 MA08 MA29 MA30 MA35 NA21 5F058 BB04 BC02 BF03 BF07 BF25 BF29 5F110 AA01 AA17 AA26 BB02 CC02 DD01 DD02 DD05 DD13 EE03 EE04 EE06 FF02 FF03 GG30 FF02 FF30 FF22 HJ01 HJ12 HJ13 HJ18 HJ23 HL03 HL04 HL07 HL08 NN02 NN04 NN22 NN23 NN24 NN34 NN35 PP01 PP03 PP35 QQ11 QQ24 QQ25

Claims (5)

[Claims] 1. A thin film transistor comprising a semiconductor layer made of polycrystalline silicon and a gate insulating film having an internal stress of -100 to 500 MPa. 2. The thin film transistor according to claim 1, wherein an internal stress of the gate insulating film located within 50 nm from the semiconductor layer is -100 to 500 MPa. 3. An internal stress of the semiconductor layer is 0 to 2000.
The thin film transistor according to claim 1, wherein the thin film transistor is MPa. 4. The thin film transistor according to claim 1, wherein said gate insulating film is made of SiO ₂ . 5. A liquid crystal display device using the thin film transistor according to claim 1.