JP2002141787A - Pulse train generating method and device and motor rotation speed command generator employing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a conventional device using a command voltage employing a fundamental triangle wave to decide a motor rotation speed cannot control a final motor rotation speed with high accuracy because the device includes an analog error due to the circuit itself, the changeover aging and ambient temperature. SOLUTION: In the method and the device for generating a pulse train, two counter means that provide an output of output signals when reaching a preset count-up setting value, and a means that properly rewrites the preset count-up setting value of the two counters as required, are provided, and the output signals of the two counters is used to generate a pulse train with an optional duty factor and an optional frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse train generating method and apparatus for generating a pulse train having an arbitrary duty and frequency, and a motor rotational speed command generating apparatus using the same.

[0002]

2. Description of the Related Art Conventionally, a threshold voltage level + Va is arbitrarily changed with respect to a time axis based on a basic triangular wave shown in FIG. 9 and, for example, at a point where the basic triangular wave and the threshold voltage level coincide with each other, for example, a window comparator ( (Not shown)) to generate a desired pulse train having a pulse width corresponding to the coincidence point.

A method of using such a pulse train is as follows.
This pulse train is input to a PWM circuit used for controlling the motor, converted into a voltage by the PWM circuit to generate a motor rotation speed command voltage, the rotation amount is determined by the number of pulses in the pulse train, and the rotation is performed at the frequency of the pulse train. The rotation of the motor is controlled by determining the speed.

[0004]

However, the conventional configuration has the following problems.

That is, since the amount of rotation is determined by the number of pulses of the pulse train and the rotation speed is determined by the frequency of the pulse train, the rotation of the stepping motor cannot be controlled.

Also, when a pulse is generated at the intersection of a basic triangular wave and a threshold voltage value, a comparison is often made.
When the basic triangular wave and the threshold voltage value are used as inputs to the comparator to detect coincidence of both input signals and to generate a pulse train,
Normally, two input signals are analog signals and noise is superimposed. Due to this effect, a dead zone is created so that unnecessary output inversion of the comparator does not occur, and a hysteresis is provided. Could not be controlled accurately.

In addition, since the basic triangular wave and the threshold voltage level, which are pulse train generation factors, are analog signals, they include analog errors due to the circuit itself, aging, and ambient temperature. Could not be obtained, and the final motor rotation speed could not be accurately controlled.

The present invention solves the above problems, and provides a pulse train generation method and a pulse train generation method capable of reducing the influence of an annual change and an ambient environment temperature and generating a pulse train with high accuracy.

[0009]

According to the present invention, in order to solve the above-mentioned problems, a reference clock signal, which is a digital signal from a reference clock generating means, is counted up to a preset set value and set. Two counter means for outputting an output signal when the value becomes a value and initializing the count value are used. The set values of the two counters are made different and rewritable, and the output signal from the counter means having a small set value is used. This is a pulse train generation method for generating a pulse train having an arbitrary duty and frequency by setting the start timing of one pulse generation and the output signal from the counter means having a large set value as the end timing of one pulse generation.

The present invention according to claim 2 is the pulse train generating method according to claim 1, wherein the set values of the two counter means are set to a ratio of 1: 2.

Next, according to a third aspect of the present invention, there is provided a reference clock generating means for outputting a reference clock signal which is a digital signal, and inputting the reference clock signal and counting up to respective preset values. Two counter means for outputting an output signal when each set value is reached and initializing the count value; and rewriting means for changing and rewriting the set values of the two counter means, the output of the counter means being provided. Signal to the reset and set inputs of the flip-flop circuit
A pulse train generation device connected in a one-to-one manner and using the output signal of the flip-flop circuit as a pulse train.

According to a fourth aspect of the present invention, there is provided the pulse train generating apparatus according to the third aspect, wherein a CPU is used as the rewriting means.

According to a fifth aspect of the present invention, there is provided the pulse train generating apparatus according to the third or fourth aspect, wherein the preset count target set values of the two counter means are set to a ratio of 1: 2.

According to a sixth aspect of the present invention, after a preset count-up set value of the counter means is rewritten to the next count-up set value, the current counter integrated value and the rewritten count-up set value are rewritten. 4. The pulse train generation device according to claim 3, wherein the current counter integrated value is reset to a value greater than or equal to the rewritten count-up set value and the counter means performs an up-count process. It is.

Further, according to the present invention, after the preset countdown set value of the counter means is rewritten to the next countdown set value, the present counter integrated value is compared with the rewritten countdown set value. 4. The pulse train generation device according to claim 3, wherein the current counter integrated value is reset when the current counter integrated value is equal to or less than the rewritten countdown set value and when the counter means performs a down-counting process.

The present invention according to claim 8 has, as a PWM circuit for controlling electric power to a motor, a PWM conversion means for converting an input signal into a voltage, and a polarity adding means for adding a polarity to a signal, 8. A motor rotation speed command generation device for inputting an output signal of the flip-flop circuit according to claim 3 to said PWM conversion means.

[0017]

According to the present invention, since the set values of the two counter means are made different, a pulse at a reference clock signal interval which is a digital signal corresponding to the difference between these set values can be generated. By rewriting the set value as needed, a pulse train having an accurate frequency and duty can be generated.

Further, since the count target set value is set to a ratio of 1: 2, the duty can be accurately controlled to 50%.

By using the pulse train according to the present invention, the rotational position (angle) and speed of the stepping motor can be controlled, and the speed command voltage is generated by using a conventional basic triangular wave. Control can be performed more reliably and accurately.

Further, since the generated pulse train having an arbitrary duty is processed by the PWM conversion means and the polarity adding means to generate the command voltage, the speed command voltage is generated by using the conventional basic triangular wave. Since the analog error can be reduced, the rotation speed of the motor can be controlled with higher accuracy.

(Embodiment) Next, an embodiment of the present invention will be described.

The first embodiment will be described with reference to FIGS. 1, 3 and 4. FIG.

First, in FIG. 4, a CPU (not shown)
Uses the latch circuit 7 and activates the gate at the WRITEM terminal when a LOW signal is applied (active LOW)
Signal is set, and a predetermined bit of the data bus is set to HIGH.
(1) Set to LOW (0) and write the direction of motor rotation.

An output corresponding to the above-mentioned bit of the latch circuit 7 is transmitted to a servo amplifier (not shown) to determine the direction of motor rotation.

In this motor rotation direction setting state, it is not necessary to change the setting until the rotation direction of the motor is changed.

Next, one cycle (t1 + t) as shown in FIG.
2) A case where a pulse train having a width of t1 = t2 seconds in seconds, that is, a pulse train having a duty of 50% will be described.

First, as shown in FIG.
And a second counter 2.

The CPU (not shown) has a first counter 1
Is selected as a count target set value of the first counter on the data bus, and a value obtained by dividing the pulse OFF time t1 second by one cycle time of the reference clock which is a digital signal (if this value includes a value below the decimal point) In this case, the value is rounded to an integer value), and then WRITE
The signal is written into the first counter by converting the signal into a LOW (active LOW) signal in a pulsed manner.

Next, the second counter 2 is chip-selected by the CPU in the same manner, and the pulse ON time t is set as a count target set value of the second counter 2 on the data bus.
Set 2 seconds, then pulse WRITE signal LO
By writing a W (active LOW) signal, data is written to the second counter.

In the case of the present embodiment, a pulse train having a width of t1 = t2 seconds, that is, a duty of 50% is generated, so that the count target set value of the first counter 1 is 2
The double value is written as the count target set value of the second counter 2.

As described above, when a pulse having a pulse period of (t1 + t2) seconds is generated, the first counter produces a pulse width of t1 seconds, and the second counter generates a pulse period of (t1 + t2) seconds. Becomes

At this time, the CPU sets the START signal in FIG. 3 to active LOW.

At this instant, the first counter 1 and the second counter 1 shown in FIG.
Counter 2 simultaneously starts the counting operation of the number of reference clocks, and the final output OUT starts from the LOW level state.

Always (count target set value of first counter 1) <(count target set value of second counter 2)
After the count operation of the reference clock number is started, when the target set value is reached, the first counter 1 enters the count completed state and outputs the count completed output O1.

This output signal becomes the set input S of the RS flip-flop 3 and the output OU of the RS flip-flop 3
The logic of T switches from the LOW state to the HIGH state.

Next, since the target set value of the second counter 2 is larger than the target set value of the first counter 1, it corresponds to the difference between the respective target set values from the count completion output O1 from the first counter 1. When the number of reference clocks
That is, when the count operation is performed up to the target set value of the second counter 2, the second counter 2 also enters the count completed state, and outputs the count completed output O2.

This output signal becomes the reset input R of the RS flip-flop 3 and the output O of the RS flip-flop 3
The logic of the UT switches from a HIGH state to a LOW state.

At this time, the count completion output O2, which has switched the logic of the output OUT of the RS flip-flop 3 from the HIGH state to the LOW state, starts the counting operation of the first counter 1 and the second counter 2 (each of them). The signal also serves as a signal for resetting the current count value of the counter), and the operation for generating a pulse train matching the above-described pulse cycle (t1 + t2) seconds is started again.

Here, for example, when the motor is continuously rotated at a constant speed, the value of the pulse period (t1 + t2) seconds may be the same value in each pulse, so that the CPU does not intervene.
With this hardware, the motor can be continuously rotated at a constant speed.

On the other hand, when it is desired to accelerate or decelerate the motor from the stop state or the constant-speed rotation state, the ratio of the pulse duty time t1 second to t2 second is not changed and the motor or its motor is not changed. A value matching the acceleration / deceleration characteristic data table (not shown) or the value obtained by the acceleration / deceleration characteristic equation (not shown) matched to the mechanism using the data is set as the target set value for counting up each counter. Therefore, after the CPU controls the bus and the WRITE signal in FIG. 3 and rewrites the count target set value of the second counter 2, a half of the obtained value is used as the count target set value of the first counter 1. Rewritten as

Thereafter, the CPU sets the START signal of FIG. 3 to active LOW.

At this moment, the first counter 1 and the second counter 1 shown in FIG.
Counter 2 starts counting operation of the number of reference clocks at the same time.

The subsequent circuit operation of FIG. 3 is the same as that described above, and will not be described.

A model that matches the acceleration / deceleration characteristic table (not shown) or the acceleration / deceleration characteristic equation (not shown)
The CPU determines in real time that (the target set value of the first counter 1) <(second
The count target set value of the counter 2) is rewritten, and thereafter, the step of the CPU making the START signal pulse-active LOW in FIG. 3 is continued until the motor rotation speed becomes equal.

When reversing the rotation direction of the motor, the motor speed is always set to 0, that is, almost stopped, and then a predetermined output bit of the latch circuit of FIG. 4 is reversed. (Embodiment 2) Embodiment 2 of the present invention will be described below.

In this embodiment, in the above description, a set value smaller than the count target set value of the second counter 2 at the desired one pulse period (t1 + t2) seconds as shown in FIG. The pulse duty is made variable only under the condition that the count target set value is 1.

The other operation contents are the same as those of the above-described detailed description according to the first embodiment, and therefore, the description thereof is omitted. (Embodiment 3) (Embodiment 3) Next, Embodiment 3 of the present invention will be described.

In the third embodiment, the case of a count-up operation will be described as the counting operation of the counter.

First, in the first or second embodiment, when the count target set values of the first counter 1 and the second counter 2 are rewritten, the CPU
The signal is set to active LOW, the first counter 1 and the second counter 2 in FIG. 3 are simultaneously reset, and the counting operation of the reference clock number is restarted.

In this case, forcibly resetting the count integrated value of the counter 1 or the counter 2 by the CPU causes the pulse output to stop or become erratic.

Embodiment 3 of the present invention for solving this problem will be described with reference to FIGS. 3, 5, 6, and 7. FIG.

In FIG. 3, since the target set value of the second counter 2 is larger than the target set value of the first counter 1,
When the reference clock number corresponding to the difference between the respective target set values has elapsed from the count-up output O1 from the first counter 1, that is, when the count operation has been performed up to the target set value of the second counter 2, The second counter 2 is also in a count-up state, and outputs a count-up output O2.

This output signal becomes the reset input R of the RS flip-flop 3 and the output O of the RS flip-flop 3
The logic of the UT switches from a HIGH state to a LOW state.

At this time, the count-up output O2, which has switched the logic of the output OUT of the RS flip-flop 3 from the HIGH state to the LOW state, is supplied to the first counter 1
And a signal for starting the counting operation of the second counter 2 (also resetting the current count value of each counter), and the operation for generating a pulse matching the above-described pulse period (t1 + t2) seconds is started again.

The third embodiment of the present invention does not forcibly reset the count integrated value of the counter 1 or the counter 2 by the CPU, but only the hardware system.
That is, only the above-mentioned count-up output O2 is used as a signal for starting the counting operation of the first counter 1 and the second counter 2 (also serving as a reset of the current count value of each counter), and in the above-mentioned pulse period (t1 + t2) seconds. The operation for generating a matched pulse train is continued.

However, in FIG. 5, the current counter value during the count-up, that is, the counter value is tcl in FIG.
In the section k (for convenience) and the section a and b, the CPU
Instantly writes the set value of the second counter to the counter 2 as the next set value of the second counter as the next set value of the second counter, the current counter (integrated) value becomes the target set value of the second counter ( (The next set value of the second counter).

In this case, the reset state is set only after the current counter (integrated) value reaches a finite count value based on the number of hardware bits of the second counter, that is, until the count overflows. .

That is, in the section (for convenience) A and C in FIG. 5, a state in which the pulse train output operation is stopped occurs.

In order to avoid this situation, according to the third embodiment of the present invention, when the target set value of the counter is updated as shown in the algorithm of FIG. By comparison, if the counter integrated value is large, the integrated counter value is reset.

Thus, the section of FIG. 5 (for convenience)
The section in which the pulse train output operation is stopped in the section between A and C does not occur.

Next, when the counting operation of the counter is a count-down operation, the same technical idea as in the third embodiment of the present invention can be realized, and the target set value of the counter is updated according to the algorithm shown in FIG. In this case, the current counter integrated value is read and compared. If the counter integrated value is smaller, the integrated counter value is reset.

Thus, in the countdown operation as described above, the countdown operation (not shown) is the same as the countdown operation similar to the section in which the pulse train output operation is stopped in the section A and the section C shown in FIG. No section is generated. (Embodiment 4) Next, an embodiment in which the present invention is applied to a motor control device will be described with reference to FIGS.

FIG. 8 shows the configuration of the fourth embodiment.

The output OUT shown in FIG. 2 is taken out as the OUT output of FIG. 3, and the OUT output of FIG.
(Which is also an output) is used as an input signal of the PWM converter 4 shown in FIG.

In this embodiment, since a pulse duty proportional to the speed is required, the OU shown in FIG.
T output is used.

That is, the pulse width t2 shown in FIG. 2 is subjected to PWM conversion and used as a speed voltage command.

When the speed command is implemented by voltage, the output signal of the PWM conversion unit 4 shown in FIG. 8 is input to the polarity adding unit 5 and the CPU is used to determine the rotation direction of the motor based on the polarity of the voltage.
Is to generate a speed command voltage CV in a desired rotation direction by switching a switch 6 in the polarity adding unit 5.

The switching of the switch 6 is performed when the speed command voltage is substantially 0, that is, after the speed command voltage is substantially stopped, and then the predetermined output bit of the latch circuit 7 shown in FIG. 4 is inverted.

As described above, the respective count target set values set in the first counter 1 and the second counter 2 are the desired pulse period (t1 + t2) seconds and the desired pulse duration.
(T1 / t2).

In the first embodiment (the case where the present invention is applied to an apparatus for controlling the rotation of a stepping motor in which the amount of rotation is determined by the number of pulses of the pulse train and the rotation speed is determined by the frequency of the pulse train), the pulse duty is used. Is set to an ideal pulse duty of 50% since it does not directly affect the motor control.

Therefore, in one cycle (t1 + t2) seconds, t1 =
It is t2 seconds, and the count target set value of the second counter 2 is twice the count target set value of the first counter 1.

In the second embodiment, since the pulse duty is variable, the count target set value of the second counter 2 is larger than the count target set value of the first counter 1 in one cycle (t1 + t2) seconds. Value.

Further, in Embodiment 4, Embodiment 2
The pulse train having an arbitrary pulse duty generated in step (1) is processed by the PWM converter unit and the polarity adding unit to generate the command voltage, so that the analog error is smaller than in the case where the speed command voltage is generated using the conventional basic triangular wave. So you can
The rotation speed of the motor can be controlled with higher accuracy.

[0074]

As is apparent from the above description, according to the present invention, a pulse train having an arbitrary frequency and duty (for example, 50% duty) can be generated.
Therefore, if this is used for the rotation control of the stepping motor, the rotation can be performed with high precision and smoothness, and the positioning can be performed more reliably and more accurately than the conventional one.

Further, according to the present invention, there are provided a PWM conversion means for inputting an output signal of the flip-flop circuit and converting it into a voltage, and a polarity adding means for adding a polarity. A pulse train having a tee can be generated, and this pulse train is processed by the PWM converter unit and the polarity adding unit to generate a command voltage. Therefore, an analog error can be reduced as compared with a case where a speed command voltage is generated using a conventional reference triangular wave. , The rotation speed of the motor can be controlled with higher accuracy.

[Brief description of the drawings]

FIG. 1 is a timing chart illustrating pulse train generation in an embodiment of the present invention.

FIG. 2 is a timing chart illustrating pulse train generation in the embodiment of the present invention.

FIG. 3 is an explanatory diagram of a pulse train generation circuit according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a circuit for controlling a motor rotation direction in the embodiment of the present invention.

FIG. 5 is a timing chart for explaining the updating of the counter target set value.

FIG. 6 is a main part flowchart for updating a counter target set value at the time of up-counting

FIG. 7 is a main part flowchart at the time of updating the counter target set value at the time of down-counting;

FIG. 8 is an explanatory diagram of a PWM circuit unit according to the embodiment of the present invention.

FIG. 9 is a diagram showing a conventional example of generating a pulse train using a basic triangular wave.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st counter 2 2nd counter 3 RS flip-flop circuit 4 PWM converter part 5 Polarity addition part 6 Switch 7 Latch circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tatsuya Ikeda 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5H580 BB05 BB09 EE01 FA13 FA22 FB03 GG03 5J039 GG02 GG07 KK05 KK23 MM06

Claims (8)

[Claims] A counter means for counting a reference clock signal, which is a digital signal from a reference clock generating means, to a preset set value, outputting an output signal when the count value reaches the set value, and initializing the count value. Use two,
The set values of the two counters are made different and rewritable, an output signal from the counter means having a small set value is used as a start timing of one pulse generation, and an output signal from the counter means having a large set value is terminated. A pulse train generation method for generating a pulse train having an arbitrary duty and frequency as a timing. 2. A pulse train generating method according to claim 1, wherein the set values of said two counter means are set to a ratio of 1: 2. 3. A reference clock generating means for outputting a reference clock signal which is a digital signal, and counting the reference clock signal to each set value set in advance and outputting when each set value is reached. Two counter means for outputting a signal and initializing a count value; and rewriting means for rewriting and changing the set values of the two counter means, wherein an output signal of the counter means is set to a reset input of a flip-flop circuit. A pulse train generation device connected to the inputs one-to-one, and using the output signal of the flip-flop circuit as a pulse train. 4. The pulse train generating apparatus according to claim 3, wherein a CPU is used as the rewriting means. 5. A pulse train generating apparatus according to claim 3, wherein said preset count target set values of said two counter means are set to a ratio of 1: 2. 6. Rewriting the preset count-up value of the counter means to the next count-up value, and comparing the current counter integrated value with the rewritten count-up value. 4. The pulse train generating apparatus according to claim 3, wherein the current counter integrated value is reset when the value of the counter is equal to or larger than the rewritten count-up set value and when the counter means performs an up-count process. 7. After the preset countdown set value of the counter means is rewritten to the next countdown set value, the current counter integrated value is compared with the rewritten countdown set value, and the current counter integrated value is rewritten. 4. The pulse train generation device according to claim 3, wherein the current counter integrated value is reset when the count value is equal to or less than the countdown set value and when the counter means performs a downcount process. 8. A PWM circuit for controlling electric power to a motor, comprising: a PWM conversion means for converting an input signal into a voltage; and a polarity adding means for adding a polarity to a signal.
A motor rotation speed command generation device for inputting an output signal of the flip-flop circuit according to any one of the above to the PWM conversion means.