JP2002141422A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which improves the retention characteristics of a DRAM. SOLUTION: The semiconductor device comprises a DRAM part A and a logic part B on a semiconductor substrate with gate electrodes formed on element regions. A gate electrode 45 in the DRAM part A has no side wall but gate electrodes 27, 28 in the logic part B have side walls 35.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a DRAM unit and a method for manufacturing the semiconductor device, and more particularly to an improvement in retention characteristics of the DRAM unit.

[0002]

2. Description of the Related Art FIGS. 6 to 8 are sectional views showing a conventional method of manufacturing a semiconductor device. A conventional method for manufacturing a semiconductor device will be described with reference to these drawings. First, a DRAM part A and a logic part (hereinafter, referred to as a Logic part) B are present on the semiconductor substrate 1.
the Nch transistor part B ₁ and the Pch transistor part B ₂ is present in the c unit B. Then, N of the semiconductor substrate 1
The channel transistor portion B ₁ and the DRAM portion A have a PW
Ell2, the Pch transistor part B ₂ N-Well
3. The bottom of P-Well2 of the DRAM part A is Bott.
om N-Well 4 are respectively formed. Further, isolation oxide films 5 for isolating the respective element regions are formed.

Next, a DRAM section A and a Logic section B
A gate insulating film 6 is formed thereon, and a conductive film 7 made of polysilicon is laminated on the gate insulating film 6 (FIG. 6).
(A)). Next, a resist film 8 patterned to form a gate electrode is applied to the DRAM part A and the Logi.
Both are formed on the portion c (FIG. 6B). Then, the conductive film 7 is patterned by the resist film 8 to form a DRAM.
Gate electrodes 9, 10, 1 on the part A and the Logic part B
1 are formed (FIG. 6C).

[0004] Next, a resist film 12 covering the Pch transistor part B _2, by implanting n-type impurity 13 of low concentration in the DRAM portion A and the Nch transistor part B _1,
First N ⁺ source / drain regions 14 are formed (FIG. 7)
(A)). Next, a resist film 15 covering the DRAM section A and the Nch transistor section B ₁ is formed, and a p-type impurity 16 having a low concentration is implanted into the Pch transistor section B ₂ to form a first P ⁺ source / drain region 17. (Figure 7
(B)).

Next, a DRAM section A and a Logic section B
An insulating film is laminated so as to cover the respective gate electrodes 9, 10 and 11, and sidewalls 18 are formed on the side walls of the respective gate electrodes 9, 10 and 11 by anisotropic etching (FIG. 7 (c)). )). Next, Pch transistor section B ₂ to form a resist film 19 covering the, DRAM portion A and the Nch transistor section B ₁ to the highly concentrated n-type impurity 2
0 is implanted to form a second N ⁺ source / drain region 21 (FIG. 8A).

[0006] Next, a resist film 22 covering the DRAM portion A and the Nch transistor part B _1, by implanting p-type impurities 23 dark concentration Pch transistor part B _2,
A second P ⁺ source / drain region 24 is formed (FIG. 8).
(B)). Next, a refractory metal silicide film 25 is formed on each source / drain region and each gate electrode exposed in the DRAM part A and the Logic part B (FIG. 8C).

[0007]

The conventional semiconductor device is constructed as described above, and the source / drain region is formed with a lightly doped impurity diffusion layer and a heavily doped impurity diffusion layer as described above. Thereby, it is possible to form an LDD structure which is excellent in measures against hot carriers. In order to form an LDD structure, it is necessary to form a sidewall on a side wall of the gate electrode.

However, when the sidewall is formed, there is a problem that the semiconductor substrate is damaged, and in the DRAM portion, the retention characteristic (refresh characteristic) is deteriorated by the damage. Thus, a method is conceivable in which the impurity diffusion layer has a single structure and no sidewall is formed. However, in such a case, there is a problem that the hot carrier has a large amount of operating current, so that measures against hot carriers become insufficient.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is intended to manufacture a semiconductor device and a semiconductor device capable of improving the retention characteristics of a DRAM portion without deteriorating the performance of other portions. The aim is to provide a method.

[0010]

Means for Solving the Problems Claim 1 according to the present invention.
In a semiconductor device having a first element region portion and a second element region portion on a semiconductor substrate, and a gate electrode formed on each element region portion, a first element region portion is provided. No sidewall is formed on the gate electrode of No. 1, and a sidewall is formed on the gate electrode of the second element region.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the impurity diffusion layer in the gate electrode of the first element region is formed in a single structure.
The impurity diffusion layer in the gate electrode in the second element region has an LDD structure.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, an upper portion of the gate electrode in the first element region portion and an upper portion of the gate electrode in the second element region portion are provided. Further, a silicide film is formed on each of the impurity diffusion layers in the second element region, and no silicide film is formed on the impurity diffusion layers in the first element region.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the first element region portion is a DRAM portion, and the second element region portion is a logic portion. belongs to.

According to a fifth aspect of the present invention, in a method of manufacturing a semiconductor device having a first element region and a second element region on a semiconductor substrate, Forming a gate insulating film over the element region and the second element region, laminating a conductive film over the gate insulating film, patterning the conductive film over the first element region and over the second element region; Forming an insulating film on the conductive film and the second element region portion and performing anisotropic etching, forming a sidewall on a side wall of the gate electrode in the second element region portion; A gate electrode is formed by covering the second element region and patterning the conductive film in the first element region.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, the step of forming the impurity diffusion layer in the second element region includes forming a side wall of the gate electrode in the second element region. The impurity diffusion layer has an LDD structure by implanting impurities before and after forming a sidewall.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the impurity diffusion layer in the second element region is formed before forming the gate electrode in the first element region. After the formation, a silicide film is laminated on the gate electrode and the impurity diffusion layer on the conductive film and the second device region, and the conductive film on which the silicide film is formed is patterned to form the first device. A gate electrode provided with a silicide film on the upper part in the region is formed.

According to a eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the fifth to seventh aspects, the gate electrode covers the second element region and is formed on the first element region. Is used as a mask to form an impurity diffusion layer.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described. 1 to 5 are sectional views showing the structure of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. A method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. First, as in the conventional case, the semiconductor substrate 1 has a D element as a first element isolation region.
There are a RAM section A and a Logic section B as a second element isolation region, and the Logic section B has an Nch transistor section B ₁ and a Pch transistor section B ₂ .

The N-channel transistor portion B ₁ and the DRAM portion A of the semiconductor substrate 1 have P-Well 2,
ch transistor portion B ₂ is N-Well3, DRAM
Bottom N-W is located at the bottom of P-Well2 of part A.
cell4 is formed. Further, isolation oxide films 5 for isolating the respective element regions are formed.

Next, the DRAM section A and the Logic section B
A gate insulating film 6 is formed on the semiconductor substrate 1 of FIG. 1, and a conductive film 7 made of, for example, polysilicon is laminated on the gate insulating film 6 (FIG. 1A). Next, a patterned resist film 26 for forming a gate electrode on the Logic section B is formed (FIG. 1B). Then, the conductive film 7 is patterned by the resist film 26,
Gate electrodes 27 and 28 on the part B are respectively formed (FIG. 1C).

Next, a resist film 29 covering the DRAM portion A and the Pch transistor part B _2, by implanting n-type impurity 30 of low concentration on the Nch transistor part B _1,
A first N ⁺ source / drain region 31 is formed (FIG. 2)
(A)). Next, a resist film 32 covering the DRAM portion A and the Nch transistor part B _1, by implanting p-type impurity 33 of low concentration in the Pch transistor section B _2, form a first P ⁺ source / drain regions 34 (Figure 2
(B)).

Next, an insulating film is laminated so as to cover the gate electrodes 27 and 28 on the DRAM section A and the Logic section B, and is anisotropically etched to form the Logic section B.
Sidewalls 35 on the side walls of the respective gate electrodes 27 and 28.
Are formed respectively (FIG. 2C). At this time, DRAM
Since the conductive film 7 is formed on the entire surface of the portion A, the DRA
The semiconductor substrate 1 is not damaged in the M section A. Next, a resist film 36 covering the DRAM portion A and the Pch transistor part B _2, by implanting n-type impurity 37 dark concentration Nch transistor part B _1, forming a second N ⁺ source / drain regions 38 (Figure 3
(A)).

Next, a resist film 39 covering the DRAM portion A and the Nch transistor part B _1, by implanting p-type impurities 40 dark concentration Pch transistor part B _2,
A second P ⁺ source / drain region 41 is formed (FIG. 3)
(B)). As described above, the Logic part B includes the gate electrode 2
By forming the sidewalls 35 on the side walls 7 and 28, the impurity diffusion layer can be formed with the LDD structure including the first and second source / drain regions. Next, a refractory metal silicide film 42 is formed on each of the source / drain regions exposed on the DRAM section A and the Logic section B, on each of the gate electrodes, and on the conductive film (FIG. 3C).

Next, a patterned resist film 44 for forming a gate electrode on the DRAM section A is formed (FIG. 4A). Then, the conductive film 7 having the silicide film 42 formed thereon is patterned by the resist film 44, and a gate electrode 45 having the silicide film 42 formed thereon is formed on the DRAM part A (FIG. 4B).

Next, a resist film 4 covering the Logic part B
6 is formed, and a high concentration n-type impurity
Is implanted to form N ⁺ source / drain regions 48 (FIG. 4C). Next, the resist film 46 is removed, and D
In the RAM section A, a gate electrode having a single-structured impurity diffusion layer having no sidewall is provided.
A gate electrode having an impurity diffusion layer having an LDD structure can be formed on the optic portion B with a sidewall.

In the semiconductor device according to the first embodiment configured as described above, a sidewall is not provided in a region where a sidewall is not required on a side wall of a gate electrode, such as the DRAM portion A, in each element isolation region. A gate electrode that is not formed can be formed, and a gate electrode having a sidewall formed can be formed in a region that requires a sidewall on the side wall of the gate electrode, such as the Logic portion B.

Thus, in the DRAM section A, damage to the semiconductor substrate 1 can be minimized, and the retention characteristics of the DRAM section A can be improved. In the Logic part B, an impurity diffusion layer having an LDD structure can be formed on the gate electrode, so that an excellent countermeasure against hot carriers can be obtained.

Further, since the silicide film can be formed only on the gate electrode of the DRAM section A and on the gate electrode and the impurity diffusion layer of the Logic section B, the retention characteristics can be further improved.

[0029]

As described above, according to the first aspect of the present invention, the semiconductor substrate is provided with the first element region and the second element region, and the gate electrode is formed on each element region. In each of the formed semiconductor devices, the sidewall is not formed on the gate electrode of the first element region, and the sidewall is formed on the gate electrode of the second element region. Providing a semiconductor device capable of separately forming an element region having a gate electrode with a sidewall and an element region having a gate electrode without a sidewall. Becomes possible.

According to a second aspect of the present invention, in the first aspect, the impurity diffusion layer in the gate electrode in the first element region is formed in a single structure, and the gate electrode in the second element region is formed. Is formed in an LDD structure, the element region in which the impurity diffusion layer of the gate electrode is formed in a single structure and the impurity diffusion layer of the gate electrode are formed in the LDD structure in each element region. It is possible to provide a semiconductor device which can be formed separately from the formed element region.

According to a third aspect of the present invention, in the first or second aspect, the upper part of the gate electrode in the first element region part, the upper part of the gate electrode in the second element region part, and Since a silicide film is formed on the impurity diffusion layer in the second element region and no silicide film is formed on the impurity diffusion layer in the first element region, the gate electrode and the gate electrode in each element region are formed. It is possible to provide a semiconductor device that can be formed separately from a portion requiring a silicide film and a portion not requiring a silicide film in the impurity diffusion layer.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the first element region is a DRAM unit and the second element region is a logic unit. Therefore, it is possible to provide a semiconductor device in which a sidewall is not formed in a gate electrode of a DRAM portion and a sidewall is formed in a gate electrode of a logic portion.

According to a fifth aspect of the present invention, in a method of manufacturing a semiconductor device having a first element region and a second element region on a semiconductor substrate, the first element region and the second element region are provided. Forming a gate insulating film on the device region of
A conductive film is stacked over the gate insulating film, the conductive film over the first element region is covered and the conductive film over the second element region is patterned to form a gate electrode, and over the conductive film and over the second element region. An insulating film is laminated on the substrate and anisotropically etched to form a sidewall on the side wall of the gate electrode in the second element region, and to cover the second element region and pattern the conductive film in the first element region. In each element region, an element region having a gate electrode with a sidewall and an element region with a gate electrode without a sidewall are formed separately in each element region. It is possible to provide a method of manufacturing a semiconductor device that can perform the above.

According to a sixth aspect of the present invention, in the fifth aspect, the impurity diffusion layer in the second element region is formed by forming a sidewall on the side wall of the gate electrode in the second element region. Before and after the implantation, the impurity diffusion layer is formed by the LDD structure by implanting the impurity. Therefore, the impurity diffusion layer of the gate electrode having the sidewall is formed by the LDD structure in a desired element region in each element region. A method for manufacturing a semiconductor device that can be formed can be provided.

According to a seventh aspect of the present invention, in the sixth aspect, before forming the gate electrode in the first element region and after forming the impurity diffusion layer in the second element region, A silicide film is stacked on the conductive film, on the gate electrode in the second element region, and on the impurity diffusion layer, and the conductive film on which the silicide film is formed is patterned to form an upper layer in the first element region. Since the gate electrode including the silicide film is formed, a portion requiring the silicide film and a portion not requiring the silicide film can be formed separately from the gate electrode and the impurity diffusion layer in each element region. A method for manufacturing a semiconductor device can be provided.

According to an eighth aspect of the present invention, in any one of the fifth to seventh aspects, the impurity diffusion using the gate electrode as a mask covers the second element region and covers the first element region. Since the layers are formed, it is possible to provide a method of manufacturing a semiconductor device in which an impurity diffusion layer of a gate electrode having no sidewall can be formed in a single structure in a desired element region in each element region. Becomes

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a configuration of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing a configuration of a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention;

FIG. 3 is a sectional view illustrating a configuration of a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention;

FIG. 4 is a sectional view illustrating a configuration of a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention;

FIG. 5 is a sectional view showing a configuration of the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a cross-sectional view illustrating a configuration of a conventional method for manufacturing a semiconductor device.

FIG. 7 is a cross-sectional view illustrating a configuration of a conventional method for manufacturing a semiconductor device.

FIG. 8 is a cross-sectional view illustrating a configuration of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 6 gate insulating film, 7 conductive film, 2
7, 28, 45 gate electrode, 31, 34 first source / drain region, 38, 41 second source / drain region, 35 sidewall, 42 silicide film,
48 source / drain region, A DRAM section, BL
omic part.

Claims (8)

[Claims] A first element region formed on a semiconductor substrate;
Wherein the gate electrode of the first element region has no sidewall, and the gate electrode of the first element region has no sidewall. A semiconductor device, wherein a sidewall is formed on a gate electrode in an element region. 2. The semiconductor device according to claim 1, wherein the impurity diffusion layer in the gate electrode of the first element region has a single structure, and the impurity diffusion layer in the gate electrode of the second element region has an LDD structure. The semiconductor device according to claim 1, wherein: 3. A silicide film is formed on the gate electrode in the first device region, on the gate electrode in the second device region, and on the impurity diffusion layer in the second device region. 3. The semiconductor device according to claim 1, wherein a silicide film is not formed on the impurity diffusion layer in the first element region. 4. The first element region part is a DRAM part,
The semiconductor device according to claim 1, wherein the second element region is a logic unit. 5. A method for manufacturing a semiconductor device having a first element region and a second element region on a semiconductor substrate, wherein a gate insulating layer is provided on the first element region and the second element region. Forming a film, laminating a conductive film on the gate insulating film, and covering the first element region with the second
Forming a gate electrode by patterning the conductive film on the element region portion of, and laminating an anisotropic film on the conductive film and the second device region portion and performing anisotropic etching;
Forming a sidewall on the side wall of the gate electrode in the second element region, and patterning the conductive film in the first element region to cover the second element region to form a gate electrode And a method for manufacturing a semiconductor device. 6. An impurity diffusion layer in the second element region is formed by implanting impurities before and after forming a sidewall on the side wall of the gate electrode in the second element region. 6. The method according to claim 5, wherein the impurity diffusion layer has an LDD structure. 7. An upper portion of the conductive film and an upper portion of the gate electrode of the second element region portion after the impurity diffusion layer of the second element region portion is formed before the gate electrode of the first element region portion is formed. A step of laminating a silicide film on the impurity diffusion layer, patterning the conductive film on which the silicide film is formed, and forming a gate electrode having a silicide film on the upper part in the first element region; The method for manufacturing a semiconductor device according to claim 6, wherein: 8. The method according to claim 5, further comprising the step of forming an impurity diffusion layer on the first element region by covering the second element region with the gate electrode as a mask. 13. A method for manufacturing a semiconductor device according to