JP2002141415A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is suitable for formation of a circuit for applications using a plurality of supply voltages, and is programmable according to I/O cell allocation and therefore is flexible and can provide protection against ESD/EOS. SOLUTION: The semiconductor device comprises either N type or P type first guard ring and a second guard ring which is formed adjacently to the first guard ring and is N type when the first guard ring is P type or vice versa. The first ring guard is formed as a collection of many insular well regions so divided that each well region may correspond to each I/O cell or to a plurality of I/O cells. At least one of the well regions is connected to a first power line and at least one of the remaining well regions is connected to a second power line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a gate array LS.
A plurality of power supply voltages can be easily used at the stage of application processing to an LSI base chip such as an embedded array LSI, an embedded array LSI, a full custom LSI, and the like.
Flexible and flexible E depending on O-cell assignment
SD (electrostatic discharge; ELECTRO-STATIC DISCHARGE) / EOS
The present invention relates to a semiconductor device that can easily form a protection circuit for (ELECTRICAL OVER-STRESS).

[0002]

2. Description of the Related Art Conventionally, a base chip of an LSI such as a gate array LSI, an embedded array LSI, a full custom LSI, etc. (a virtual LSI in a design stage in which program writing for forming a specific circuit is not performed) is performed. In (1), the core portion and the I / O portion are formed separately. The base chip, or an LSI for which an application is designed using the base chip and manufactured according to the base chip, has a structure as shown in FIG. Various functional circuits (normal logic circuits) in the core
Is formed. The I / O unit is provided with an ESD / EOS protection circuit for protecting the semiconductor device against an electric stress such as an electrostatic induction voltage or an overcurrent from the outside.

FIG. 5 shows an example of this type of LSI base chip or an LSI manufactured according to this base chip (these will be described below with reference to a base chip). In FIG. Is a gate array LSI, embedded array LSI, full custom LS
A base chip such as I, 2 is an I / O section formed around the base chip, 3 is a core section provided therein, and between the I / O section 2 and the core section 3, A guard ring 4 of a dummy collector is formed. This dummy collector is a region which acts as a collector of a parasitic transistor (a dummy transistor which is not originally intended to operate) formed via a substrate for a transistor in a CMOS circuit formed in the I / O unit 2 and the core unit 3. It is. 5, 5, 5... Are normal power supply voltages, for example, 3
The I / O cells used in the circuit for the V power supply, and 6, 6, 6,... Shown by oblique lines are, for example, the I / O cells used in the circuit for the 5 V power supply. Reference numeral 7 denotes a pin provided on the package 9 (case) for external connection. In the I / O section 2, pads 8, 8, 8.
Each I / O cell is usually provided with an input protection circuit or an output protection circuit using a CMOS buffer amplifier and a diode, and further, ESD / EOS protection using a diode, a capacitor, and the like. Although circuits are formed, they are omitted in the figure.

In the case where a plurality of power supply voltages are used in the application processing stage for the base chip, the I / O cell 6 indicated by oblique lines uses a 5V power supply as a power supply other than the normal 3V power supply. This is an I / O cell selected from among the I / O cells 5 for use with a 5V power supply. As this type of LSI, an LSI incorporating an analog signal processing circuit operating at a power supply voltage of 5 V is used.
And the like. In a circuit incorporating a DSP, the DSP is operated at a power supply voltage of about 1.8 V.
By the way, the guard ring 4 of the dummy collector has an I / O
The unit 2 and the core unit 3 are provided between them to separate them, and are usually connected to a power supply line corresponding to a single power supply to form an ESD / EOS protection circuit. Therefore, it is possible to use this as a protection circuit for one power supply line. However, when a plurality of power supply voltages are used, in the I / O section 2 of the base chip 1, a corner or dead space is used. It is necessary to separately form an ESD / EOS protection circuit. The I / O cell 6 is a region where such a protection circuit is formed, and is generally used for a high voltage of about 5 V when a 3 V power supply is mainly used. In the figure, if a region 3a (a large rectangular block on the right side in the center of the drawing) of the core portion 3 is a circuit region operated by a 3V power supply, a region 3b (small vertically long block on the left side in the center of the drawing) will have a 5V Is formed, and this is usually as small as about 10% of the whole.

[0005]

An LS having such a structure
In an I base chip, each I / O cell corresponds to a pin on the package. Therefore, base chip 1
If the corner portion or dead space is used, the position of the pin 7 of the package to be used is restricted. In general, the power supply pin side of the power supply pin is preferentially selected according to different power supply voltages. Therefore, the I / O cell 6 using a corner portion or dead space is independent of the power supply pin 7 selected. They will be connected by wiring. Moreover, in this case, as the power supply voltage is higher, it is necessary to increase the number of protection elements or to form a protection element having a larger area. Therefore, wiring design, pin assignment, selection of I / O cells, and the like must be performed for each application, thereby increasing the number of steps in the actual LSI manufacturing process.

Therefore, a plurality of power supply lines and a plurality of ground lines are provided in the I / O section 2 in a ring shape corresponding to a plurality of power supply voltages, and the ESs formed in each I / O cell are provided.
D / EOS protection circuits are assigned to respective corresponding power supply lines and connected. However, in this case, the line width per power supply line becomes narrow, and there is a problem that the number of protection elements of the power supply system cannot be sufficiently arranged corresponding to the power supply voltage. In order to solve this kind of problem, the applicant has provided a wide power supply line and a ground line in parallel to the I / O section and the core section, respectively, and provided an ESD / EOS protection circuit to the I / O section and the core section. The technology for forming the / O portion and the core portion has been filed as "Semiconductor Integrated Circuit" in Japanese Patent Application No. 11-2597 (Japanese Patent Application Laid-Open No. 12-208706). However, in this case, the area of the core portion is limited, and it is necessary to design a layout specifically for different power supply systems. It increases manufacturing man-hours at the stage of application processing. The purpose of this invention is
In order to solve such problems of the prior art,
It is an object of the present invention to provide a semiconductor device which is suitable for forming a circuit corresponding to an application using a plurality of power supply voltages and which can protect a programmable and flexible ESD / EOS according to an I / O cell allocation. Another object of the present invention is to manufacture a semiconductor device which can easily use a plurality of power supply voltages at the stage of application processing and can protect programmable and flexible ESD / EOS according to I / O cell allocation. It is to provide a method.

[0007]

In order to achieve the above object, a semiconductor device according to the present invention has a structure in which an I / O region in which a large number of I / O cells are formed in a peripheral portion and various types of I / O regions are provided inside. In a semiconductor device having a core region in which a functional circuit is formed, and a guard ring provided between the I / O region and the core region, the guard ring may be a first one of an N-type and a P-type. And a second guard ring of the other of the N-type and the P-type formed adjacent to the first guard ring. It is formed as an O-cell unit or as a set of a large number of island-shaped well regions divided corresponding to a plurality of I / O cells, and at least one of the well regions is connected to the first power supply line and the remaining At least one of the well regions Are those connected to the second power supply line. Further, the invention of the method of manufacturing a semiconductor device according to the present invention is further characterized in that the connection between at least one of the well regions and the first power supply line and the connection between at least another well region and the second power supply line , Or a contact process in an LSI manufacturing process or a subsequent manufacturing process.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the semiconductor device of the present invention having such a structure, the first guard ring is formed of an I / O cell unit or a large number of island-shaped corresponding to a plurality of I / O cells. It is divided into well regions. Therefore, it is possible to selectively connect the island-shaped well regions. The selective connection can be performed by application-level processing during the manufacture of the semiconductor integrated circuit. That is, the contact processing can be performed in the manufacturing process of the LSI manufactured according to the base chip, or can be performed in accordance with the pin positions of different power supply voltages in the subsequent manufacturing processes. At this time, the divided island-shaped regions of the first guard ring are selectively connected to the I / O cell positions corresponding to the positions of the power supply pins having different voltages, thereby connecting the divided island-shaped regions. ESD / EOS
Can be used corresponding to each power supply voltage. Furthermore, protection circuits such as diodes of necessary current capacity corresponding to different power supply voltages can be formed independently of each other by connecting a plurality of surrounding divided island regions in parallel according to the required current capacity. Can be. Specifically, the selection and connection of the divided island-shaped well regions of the first guard ring can be performed, for example, by simply processing the connection wiring in the metal wiring layer above the first guard ring. Is possible. Therefore, it is not necessary to design a special layout. As a result, a plurality of power supply voltages can be used at the stage of application processing, and the programmable and flexible ESD / E
A semiconductor device capable of OS protection can be easily realized.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, reference numeral 10 denotes a gate array LS.
I, an embedded array LSI, a full-custom LSI, or other base chip (or an LS manufactured in accordance therewith)
I), and the view shown in FIG. 1 corresponds to the enlarged view at the position of the lower left corner in FIG. Reference numeral 12 denotes a large number of island-shaped well regions (island-shaped regions) 12a, 12b, having an N ⁺ layer extraction region formed between the I / O unit 2 and the core unit 3.
, 12n,... Are first guard rings. A large number of well regions formed in the shape of an island are arranged at predetermined intervals, and are collectively arranged on the base chip 10 in a rectangular ring shape as a whole like the card ring 4 shown in FIG. . Then, as shown in the island-shaped region 12i of FIG. 1, the protrusions 15a and 15b which are alternately provided at both ends.

[0010] Along the guard ring 12, similarly, a take-out area 16 of one P ⁺ layer is formed in a rectangular ring shape (see FIG. 2).
Are provided on the inner side (on the side of the core portion 3) at a predetermined interval. As a result, P along the extraction region 16 of the P ⁺ layer
The second guard ring 11 of the mold is a P-type substrate (P
-Sub) 13 is formed on and adjacent to the first guard ring 12 on the surface thereof. The second guard ring 11 is formed as a part of a P-type substrate (P-sub) 13 between the guard ring 12 and the core portion 3, and the first and second guard rings 12, 11 is
Each is a dummy collector of a parasitic transistor formed in relation to the substrate 13. Note that I
A large number of CMOS circuits are formed in the / O section 2 and the core section 3, respectively. By the way, in the embodiment described below,
The same components as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 1, island-like regions 12a, 12b,.
.. Among the island-shaped regions 12a, 12b, 12n
Are formed in I / O cell units with a length corresponding to each outer I / O cell 5. In addition, for example, the island-shaped region 12h at the corner portion is formed as an island-shaped region divided by a length corresponding to the two I / O cells 5. The formed island-shaped region substantially corresponds to an I / O cell unit or a plurality of lengths thereof. Hereinafter, the island-shaped regions 12a, 12b,..., 12n,. As shown in the cross-sectional view of FIG. 2, the island-shaped region 12i has a length corresponding to an I / O cell unit or an island-shaped N having a length substantially corresponding to a plurality of I / O cells. The N well region 14i includes an N ⁺ layer 15i provided on the surface side of the N well region 14i as an extraction region thereof. As shown in FIG. 2, a P ⁺ layer 16 is formed as a P ⁺ extraction region of a P-type guard ring (dummy collector guard ring) 11 adjacent to N-well region 14i forming guard ring 12 with a predetermined width. ing. Thereby, as described above, the region between the N well region 14i and the P ⁺ layer 16, and the P ⁺ layer 1
A guard ring 11 is formed around 6. The P-type guard ring 11 extends to a space while dividing each of the island regions 12i.

As shown in FIG. 3, if the power supply pins of different voltages, for example, power supply pins of 3 V and 5 V exist, as shown in FIG. A plurality of N ⁺ layers 15i adjacent to each other at a voltage of 3V are formed by wiring lines 20 formed in the upper metal wiring layer, and a plurality of N ⁺ layers 15i adjacent to each other at 5V.
Are respectively connected by wiring lines 21 formed in the upper metal wiring layer. Then, P ⁺ which is an area where the guard ring 11 of the dummy collector is taken out is used ^.
The layer 16 is also connected to the ground GND via the upper metal wiring line 22. As a result, the guard ring area 17 corresponding to the power supply voltage of 3 V and the guard ring area 18 corresponding to the power supply voltage of 5 V are connected to the assigned power supply voltage pin 7.
It can be selectively formed corresponding to the positions of the I / O cell 5 and the I / O cell 6 corresponding to a and 7b, respectively. At this time, a diode protection circuit can be formed at the same time. That is, the guard ring 11 of the dummy collector and the N
A divided well region 14 is formed between the well region 14i and the well region 14i.
Since PN junctions are individually formed corresponding to i, they become protection diodes. Further, as shown in FIG. 3, capacitors are simultaneously formed by the respective PN junctions. In addition, the protection current capacity of the protection diode can be set to be as large as the number of selected island regions 12i. The capacity of the capacitor can be increased at the same time. Therefore, a protection diode having a capacity corresponding to a high power supply voltage can be secured. Further, at this time, since a P-type region is formed between the adjacent island-shaped N-well region 14i, a parasitic NPN transistor is also formed, which functions as a protection circuit.

In FIG. 3, a wiring line 20 is located at a position corresponding to a 3V power supply pin 7a for supplying a power of 3V to the base chip 10 from the outside as a 3V power supply line.
N well region 14 connected to power supply pin 7a via pad 8 of / O cell 5 and corresponding to I / O cell 5
i ⁺ N ⁺ layer 15i. Then, it is also connected to the ^{N +} layer 15i of the plurality of N-well region 14i adjacent to the ^{N +} layer 15i of the N-well region 14i. The wiring line 21 is connected as a 5V power supply line to the power supply pin 7b via the pad 8 of the I / O cell 6 at a position corresponding to the 5V power supply pin 7b for supplying 5V power to the base chip 10 from outside. And is connected to the N ⁺ layer 15i of the N well region 14i corresponding to the I / O cell 6. The N ⁺ layer 15 of the N well region 14i
N ⁺ layer 15i of a plurality of N well regions 14i adjacent to i
Is also connected.

The wiring lines 20, 21, and 22 in the upper metal wiring layer are connected at the application level during the manufacture of a semiconductor integrated circuit manufactured according to the base chip 10 (or at the design stage using the base chip 10). I just need. As a result, it is only necessary to easily perform selective wiring connection corresponding to the power supply voltage pins without performing a contact process in an LSI manufacturing process or a layout design in a subsequent manufacturing process. In particular, for a pin having a high power supply voltage, a large number of adjacent island regions 12i may be connected in parallel to increase the necessary current capacity or area. Thereby, an appropriate protection circuit corresponding to the power supply voltage can be formed. As a result, as shown in FIG. 3, the diode D1 as the protection circuit and the capacitor C1 are connected to the power supply voltage 3V
, And the diode D2 and the capacitor C2 form a protection circuit with a power supply voltage of 5V. In this manner, a protection circuit can be formed corresponding to each power supply voltage and corresponding to the position of an I / O cell. For higher power supply voltages, a larger area is allocated and multiple diodes D
The current capacity and capacitance of the protection circuit including the capacitor 2 and the capacitor C2 can be made large. As a result, ESD / EOS can be protected according to the power supply voltage. As an example, in the corner of FIG. 1, one island-shaped region 12h is formed corresponding to the two I / O cells 5 at the corner.

FIG. 4 shows the gar 5 ring 11 corresponding to the island regions 12a, 12b,.
⁺ Island-like P-type well region 11a with extraction area, 11
.., 11i, 11j,... By dividing the second guard ring 11 side in this manner, each island-shaped region
i, the divided island-like region 1 of the guard ring 11
1i,... 11i,. Thus, the ground GND can be divided into each. For example, the ground GND of the digital signal circuit and the ground G of the analog signal system
ND and ND. Alternatively, the ground GND of the device can be separated from the ground GND of the specific circuit by dividing the ground GND in this way. Further, when forming a protection diode, one of the divided island regions 11a,... 11i,... Of the guard ring 11 corresponds to each N ⁺ layer 15i.
By selecting one or several as regions to be connected to the ground, protection diodes can be formed individually for each.

Therefore, each island-shaped region 12i and each corresponding island-shaped region 11i (the island-shaped region 11i
a, 11b,..., 11i, 11j,...) are connected in parallel with each other as necessary. It can be used as a protection diode. The structure of the island-shaped P-type well region 11i is the same as that of the N-well region 14i shown in FIG.
For example, a P-well region is formed on the surface of No. 3 and adjacent to the N-well region 14i, with the buried layer serving as the bottom surface and the periphery surrounded by an insulating region. Then, the island-shaped P ⁺ extraction region 16 (P ⁺ layer) is formed therein. Further, in FIG. 1 described above, only a part of the guard ring having the divided island-shaped regions is shown, but all of the island-shaped regions of the entire rectangular guard ring are respectively connected to power supply lines of different specific voltages. It does not need to be connected. Further, needless to say, there may be an I / O cell 5 or an I / O cell 6 provided in the I / O region 2 in which a protection circuit is not formed.

As described above, in the embodiment, the I / O cells 5 and I / O cells 6 corresponding to the positions of the power supply pins 7a and 7b are selected, and these I / O cells 5 and I / O cells 6 are selected. Are connected to the power supply pins 7a and 7b via the power supply lines 20 and 21, respectively. However, the power supply pins 7a, 7
The positions of b and the well region connected to them are
It is not necessary to correspond. The positional relationship with at least one island-shaped well region connected to the power supply pins 7a and 7b via the power supply line is preferably as close as possible. In the embodiment, the guard ring 12 of the N-type dummy collector is formed outside the guard ring 11 of the P-type dummy collector (on the I / O unit 2 side). Guard ring 12
May be formed at a position inside the guard ring 11 (on the side of the core portion 3). further,
In the embodiment, the example of the P-sub is used as the semiconductor substrate. However, it goes without saying that an N-sub semiconductor substrate may be used. In the case of the N-sub, the well region in FIG. The guard rings are N-type and N-type, respectively.

[0018]

As can be understood from the above description, according to the present invention, the first guard ring is an I / O cell unit or a large number of island-shaped regions corresponding to a plurality of I / O cells. , The I / O cell position corresponding to the pin position of the power supply voltage which differs at the application level during the manufacture of the semiconductor integrated circuit, and the divided island region of the first guard ring. Can be selected, and the divided island-shaped regions can be respectively used as ESD / EOS protection circuits. Moreover, only by connecting the surrounding divided island-shaped regions, protection circuits of necessary capacitance can be independently formed corresponding to different power supply voltages. In this case, selection and connection of the divided island regions of the first guard ring can be performed, for example, only by simple connection wiring processing in the upper metal wiring layer, and it is not necessary to design a special layout. Absent. As a result, a plurality of power supply voltages can be used at the stage of application processing, and I
And flexible E according to / O cell allocation
A semiconductor device capable of SD / EOS protection can be easily realized.

[Brief description of the drawings]

FIG. 1 is a partially enlarged view of a configuration of a semiconductor device to which a semiconductor device of the present invention is applied.

FIG. 2 is an explanatory diagram of a sectional structure of a divided first guard ring portion.

FIG. 3 is an explanatory diagram of a connection state of a guard ring area according to a power supply voltage.

FIG. 4 is an explanatory diagram of a case where a second guard ring is further divided.

FIG. 5 is an explanatory diagram illustrating an example of a conventional LSI or a base chip thereof in which a core unit and an I / O unit are formed separately.

[Explanation of symbols]

1, 10: Description of an LSI base chip LSI base chip, 2: I / O unit, 3: Core unit, 4, 11, 12 ... Guard ring, 5: I / O used for a circuit for 3V power supply
Cell, an I / O cell used in a circuit for a 6 ... 5 V power supply,
7 ... pins provided on the package, 8 ... pads, 13 ...
P-type substrate (P-sub), 14 ... N well region, 15 ... Guard ring layer 16 ... P ⁺ extraction region, 17, 18 ... Guard ring area, 20, 21, 22 ... Wiring line.

Claims (11)

[Claims] An I / O cell having a large number of I / O cells formed in a peripheral portion.
In a semiconductor device having an / O region, a core region in which various functional circuits are formed inside the / O region, and a guard ring provided between the I / O region and the core region, an N-type guard ring is used as the guard ring. A first guard ring of one of the P-type and a second guard ring of the other of the N-type and the P-type formed adjacent to the first guard ring; And the first
Is formed as an I / O cell unit or as a set of a large number of island-shaped well regions divided corresponding to a plurality of the I / O cells, and at least one of the well regions is a first Wherein at least one of the remaining well regions is connected to a second power supply line. 2. The well region is a dummy collector having a take-out region, a set of which is formed as a whole as a rectangular ring, and wherein said at least one well region is formed through said take-out region through said take-out region. 2. The semiconductor device according to claim 1, wherein said semiconductor device is connected to one of said first and second power supply lines in a wiring line of an upper layer. 3. The well region is of an N-type formed on a P-type substrate, the extraction region is formed as an N ⁺ layer, and the second guard ring is formed in the well region. 3. The semiconductor device according to claim 2, wherein the semiconductor device is formed adjacently as a part of the P-type substrate region, and the well region and the second guard ring form a diode protection circuit. 4. The second guard ring is a dummy collector having an extraction region formed of a P ⁺ layer formed as a rectangular ring adjacent to the well region, wherein the P ⁺ layer is grounded. The well region connected to a line and connected to one of the first and second power supply lines corresponds to a position of a power supply pin of the power supply line connected to the one of the wells, or a region near the power supply pin. 4. The semiconductor device according to claim 3, which is selected. 5. The plurality of well regions are connected to the first power supply line via an extraction region formed of the N ⁺ layer, and the remaining well regions are connected to an extraction region formed of the N ⁺ layer. 4. The semiconductor device according to claim 3, wherein the second guard ring is connected to the second power supply line via the first power supply line, and the second guard ring is formed between the first guard ring and the core region. 5. 6. The first power supply line has a higher voltage than the second power supply line, and the core region includes a circuit that operates with the voltage of the first power supply line and the second power supply line.
4. The semiconductor device according to claim 3, further comprising a circuit that operates with the voltage of the power supply line. 7. The semiconductor device according to claim 2, wherein said second guard ring comprises a plurality of divided island-shaped P-type well regions. 8. An I / O cell having a large number of I / O cells formed in a peripheral portion.
In a method for manufacturing a semiconductor device having an I / O region, a core region in which various functional circuits are formed inside the I / O region, and a guard ring provided between the I / O region and the core region, A first guard ring of one of N-type and P-type and a second guard ring of the other are formed adjacent to each other, and the first guard ring is either the I / O cell unit or A plurality of island-shaped well regions divided corresponding to the plurality of I / O cells; a connection between at least one of the well regions and the first power supply line; A method of manufacturing a semiconductor device, wherein the connection between at least one of the semiconductor devices and the second power supply line is performed in a contact process in an LSI manufacturing process or in a subsequent manufacturing process. 9. The well region is a dummy collector having a take-out region, a set of which is formed as a rectangular ring as a whole, and a diode protection circuit is formed by the well region and the second guard ring. 9. The method for manufacturing a semiconductor device according to claim 8, wherein 10. The well region is an N-type well formed on a P-type substrate, and the extraction region is N ⁺
The second guard ring is formed as a part of the P-type substrate region adjacent to the well region, and is connected to one of the first and second power supply lines. 10. The method of manufacturing a semiconductor device according to claim 9, wherein said well region corresponds to a position of a power supply pin of a power supply line connected to one of said well regions, or a region in the vicinity thereof is selected. 11. The plurality of well regions are connected to the first power supply line, the remaining well regions are connected to the second power supply line, and the second guard ring is connected to the first power supply line. 11. The method of manufacturing a semiconductor device according to claim 10, wherein said semiconductor device is formed between said guard ring and said core region.