JP2002141358A - Thin film transistor and liquid crystal display unit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a reduction in an area of an element is difficult though a reducing effect of a leakage current of a thin film transistor connected in series with a thin film transistor having a plurality of LDD structures is large. SOLUTION: The reduction in size of the element and a decrease in the leakage current are made compatible by connecting gate electrodes 15 of the plurality of thin film transistors therebetween only by a region 13b in which an impurity is implanted in a low concentration in a polycrystal semiconductor thin film used for an active layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LDD structure for reducing leakage current of a polycrystalline silicon thin film transistor (hereinafter abbreviated as TFT) and a method of manufacturing the same, and is a technique applicable to a liquid crystal display device and the like. is there.

[0002]

2. Description of the Related Art Hitherto, an LDD (Lightly-Doped-Drain) structure has been proposed in order to reduce a leakage current of a polycrystalline silicon TFT. Further, a structure in which LDD structures are connected in series has been proposed in order to further reduce leakage current. For this technology, for example, International Display
Research Conference '93, p.465.

FIG. 5 shows a method for manufacturing a thin film transistor in which a conventional LDD structure is connected in series. As shown in FIG. 5A, an amorphous silicon thin film is formed on a light-transmitting glass substrate 11 (high heat-resistant glass substrate) by a plasma vapor deposition method (P).
The amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film 13 serving as an active layer by performing a heat treatment at 600 ° C. in a nitrogen atmosphere.

This polycrystalline silicon thin film is processed into an island shape,
A silicon oxide thin film serving as the gate insulating film 14a is formed thereon to a thickness of 85 nm. Two gate electrodes 15 are formed on the silicon oxide thin film. After forming the gate electrode,
Using the gate electrode 15 as a mask, a first impurity is implanted by an ion implantation method to form a low-concentration impurity implantation region (n-region) 13b.

For the implantation of the first impurity, phosphorus (P) ions were implanted at an acceleration voltage of 80 KV and a dose of 1 × 10 ¹³ / cm ² . At this time, the polycrystalline silicon thin film under the gate electrode 15 becomes the channel region 13a of the thin film transistor.

After the implantation of the first impurity, as shown in FIG.
After forming an implantation mask using a photoresist on the DD region, a second impurity is implanted to form a high-concentration impurity implantation region (n + region) 13c to be a source and drain region of the thin film transistor.

At this time, the shape of the resist mask is shown in FIG.
As shown in (b), an opening is also provided on the polycrystalline silicon region between the gate electrodes, and the polycrystalline silicon thin film between the gate electrodes is formed between the low concentration impurity implantation region 13b and the high concentration impurity implantation region 13c. It is formed in a shape that is connected via both.

For the implantation of the second impurity, phosphorus (P) ions are implanted at an acceleration voltage of 80 KV and a dose of 1 × 10 ¹⁵ / cm ² . After the implantation of the second impurity, the photoresist mask is removed, and activation of the implanted impurity is performed. The activation treatment was performed at 900 ° C. for 2 hours.

After the activation process, an interlayer insulating film 16 is formed as shown in FIG. Finally, as shown in FIG. 5D, after opening a contact hole, source / drain electrodes 21 and 22 are formed to complete a thin film transistor.

[0010]

The thin film transistor described in the prior art has a high-purity impurity implantation region 13c of the same concentration as the source and drain regions between each gate electrode. For this reason, as shown in FIG. 5B, it is necessary to form the opening 25 in the doping mask for forming the source / drain regions of the two thin film transistors connected in series, that is, in the photoresist.

The smaller the length of the opening, the finer the element can be made, but it is limited by the pattern accuracy of the exposure machine, that is, the minimum exposure line width. Further, the length of the low-concentration impurity implantation region 13b between each gate electrode is limited to a value obtained by adding the mask alignment accuracy of the exposure apparatus to the design size.

Accordingly, in a thin film transistor having a configuration in which thin film transistors having an LDD structure are connected in series, the minimum dimension between the thin film transistors is such that the minimum exposure width of the exposure device is Wa (μm), and the designed low-concentration impurity implantation region length Ld (Μm), and when the alignment accuracy of the exposure machine is La (μm), it is difficult to reduce the value to Wa + 2Ld + La or less.

In a large plate exposure apparatus generally used for manufacturing a liquid crystal display device, the above value is typically Wa =
It is about 5 μm and La = 1 μm, and when Ld = 2 μm, it is difficult to reduce the gate electrode interval to 10 μm or less.

When such an element is used as a switching element of a liquid crystal display device, the aperture ratio of the liquid crystal display device is reduced, causing problems such as a decrease in brightness and an increase in power consumption.

An object of the present invention is to provide a thin film transistor capable of miniaturizing elements while reducing a leak current of the thin film transistor in a configuration in which thin film transistors having an LDD structure are connected in series, a manufacturing method thereof, and a liquid crystal display device. And

[0016]

According to the present invention, there is provided a thin film transistor, comprising: a channel region; a source and drain region into which an impurity is implanted at a first concentration; A polycrystalline silicon thin film provided with a low-concentration impurity region into which an impurity having a concentration lower than the first concentration is implanted, and a gate insulating film formed on the polycrystalline silicon thin film; A thin film transistor including a plurality of gate electrodes provided on the gate insulating film, wherein the polycrystalline silicon thin film between the gate electrodes is formed only of the low concentration impurity region.

In the thin film transistor of the present invention, when forming an LDD structure having a low-concentration impurity region between a channel region and a source / drain region, after implanting a first impurity using a gate electrode as a mask, The semiconductor device can be manufactured by forming an implantation mask over a region to be an LDD region including over a polycrystalline silicon region between gate electrodes and implanting a second impurity.

In the thin film transistor of the present invention, when forming an LDD structure having a low concentration impurity region between a channel region and a source / drain region, a different type of insulating film is laminated on a polycrystalline silicon thin film, and a gate is formed. After the upper insulating film on the gate electrode side of the insulating film is removed at least on the source and drain regions, and processed so as to leave the low-concentration impurity regions and the polycrystalline silicon between the gate electrodes, the gate electrode is masked. As described above, it can be manufactured by implanting impurities once.

Further, in the liquid crystal display device according to the present invention, the first concentration between the channel region and the source and drain regions into which the impurity is implanted at the first concentration is lower than the first concentration. A polycrystalline silicon thin film provided with a low-concentration impurity region into which a low-concentration impurity is implanted, a gate insulating film formed on the polycrystalline silicon thin film, and a plurality of thin films provided on the gate insulating film. A liquid crystal display using an active matrix array, comprising: a thin film transistor for driving a pixel electrode having a gate electrode; and a driving circuit integrated on the same substrate as the substrate on which the thin film transistor for driving the pixel electrode is formed. The device, wherein the polycrystalline silicon thin film between each gate electrode of the thin film transistor driving the pixel electrode has the low concentration. It is formed only in pure object region.

[0020]

2. The thin film transistor according to claim 1, wherein the first region is formed between the channel region and the source and drain regions. A low-concentration impurity region into which an impurity having a concentration lower than 1 is implanted;
A thin film transistor comprising: a polycrystalline silicon thin film provided with: a gate insulating film formed on the polycrystalline silicon thin film; and a plurality of gate electrodes provided on the gate insulating film. The polycrystalline silicon thin film between the electrodes is formed only of the low concentration impurity region.

Thus, the size between the gate electrodes can be defined only by the minimum line width of the exposure device, and it is possible to reduce the element size while reducing the leak current.

Further, the thin film transistor according to the second aspect is characterized in that the gate insulating film on the channel region is formed of a laminated film of different types of gate insulating films. Further, in the thin film transistor according to the third aspect, the gate insulating film on the channel region is formed of a two-layer film of different types of gate insulating films,
In addition, the gate insulating film over the low-concentration impurity region is constituted by a single-layer film. The thin film transistor according to claim 4, wherein the gate insulating film on the channel region is a two-layer film of a tantalum oxide film located on the gate electrode side and a silicon oxide film or silicon nitride film located on the polycrystalline silicon thin film side. It is characterized by comprising. It is characterized by having been done. Thereby, the OF of the thin film transistor
The F current can be greatly reduced.

In the thin film transistor according to the first to fourth aspects, it is preferable that the sheet resistance of the low concentration impurity region of the polycrystalline silicon thin film is in a range of 5 kΩ to 150 kΩ.

Further, the thin film transistor according to claim 6 is characterized in that the dose of the low concentration impurity region of the polycrystalline silicon thin film is 1/10 or more and 1/2 or less of the dose of the source and drain regions. .

Further, in the thin film transistor according to the present invention, the sum of the lengths along the channel length direction of all the low-concentration impurity regions included between the source and drain regions is at least 6 μm in the channel length direction of the thin film transistor;
It is characterized in that it is 12 μm or less.

A liquid crystal display device using an active matrix array according to claim 8, wherein the channel region, the source and drain regions into which impurities are implanted at the first concentration, and the region between the channel region and the source and drain regions. A polycrystalline silicon thin film provided with a low-concentration impurity region into which an impurity having a concentration lower than the first concentration is implanted; a gate insulating film formed on the polycrystalline silicon thin film; An active matrix, comprising: a thin film transistor for driving a pixel electrode having a plurality of provided gate electrodes; and a driving circuit integrated in the same substrate as the substrate on which the thin film transistor for driving the pixel electrode is formed. A liquid crystal display device using an array, wherein each of the thin film transistors that drive the pixel electrodes has a gate electrode. Serial polycrystalline silicon thin film, wherein said formed only at a low concentration impurity region.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 shows a manufacturing process of a thin film transistor having an LDD structure according to (Embodiment 1) of the present invention.

First, as shown in FIG. 1A, an amorphous silicon thin film is formed with a thickness of 50 nm by a plasma CVD method on a glass substrate 11 coated with silicon oxide.

Amorphous silicon is heated at 450 ° C.
After performing a heat treatment for 0 minutes to reduce the hydrogen concentration in the film, the amorphous silicon thin film is crystallized by excimer laser irradiation to form a polycrystalline silicon thin film 13 serving as an active layer.

This polycrystalline silicon thin film 13 is processed into the shape of a thin film transistor, and 85 nm of silicon oxide to be a gate insulating film 14a is formed thereon. Two electrically connected gate electrodes 15 are formed on the silicon oxide. Each electrode interval is formed at 5 μm which is the minimum line width of the exposure machine. The gate electrode 15 is made of 80 nm titanium (Ti) so as to be in contact with the silicon oxide, and 100 nm of an alloy containing 7.4% zirconium (Zr) in aluminum (Al) on titanium, with a total thickness of 180 nm. It is configured.

After forming the gate electrode, phosphorus (P) is accelerated by ion doping using the gate electrode 15 as a mask.
A first impurity is implanted at 0 KV and at an implantation dose of 1 × 10 ¹⁴ / cm ² to form a low-concentration impurity implantation region (n-region) 13b.

In the ion doping method, a gas obtained by mixing hydrogen gas with PH ₃ at a concentration of 5% is plasma-decomposed by high-frequency discharge, and generated ions are injected into a thin film transistor without a mass separation step. At this time, the polycrystalline silicon thin film under the gate electrode 15 is a thin film transistor channel region 13a.
Becomes

After the implantation of the first impurity, as shown in FIG.
After forming an implantation mask using a photoresist on the DD region, a second impurity is implanted to form a high-concentration impurity implantation region (n + region) 13c to be a source and drain region of the thin film transistor.

At this time, the resist mask is shown in FIG.
As described above, the polysilicon region between the two gate electrodes
All are formed so as to be masked. This allows both gates
Polycrystalline silicon thin film between electrodes is a low concentration impurity implanted region
13b is formed in such a shape as to be connected only through
You. Second impurity after forming photoresist mask
Of phosphorus (P) ions at an acceleration voltage of 80 KV and a dose of
Dose 1 × 10^Fifteen/ Cm ^TwoWas injected.

After the implantation of the second impurity, the photoresist mask is removed as shown in FIG. 1C, and the implanted impurity is activated. After the activation process, an interlayer insulating film 16 is formed as shown in FIG. Finally, after opening the contact holes, the source / drain electrodes 21, 2
2 is formed to complete the thin film transistor.

According to the thin film transistor formed as described above, the size between the respective gate electrodes is determined only by the minimum line width of the exposure device, so that the electrode interval can be reduced to 5 μm. It became possible to reduce the element size to 50% as compared with 10 μm.

(Embodiment 2) FIG. 2 shows a manufacturing process of a thin film transistor having an LDD structure according to (Embodiment 2) of the present invention.

First, as shown in FIG. 2A, an amorphous silicon thin film is formed with a thickness of 50 nm by a plasma CVD method on a glass substrate 11 coated with silicon oxide. After the amorphous silicon is heat-treated at 450 ° C. for 90 minutes in nitrogen to reduce the hydrogen concentration in the film, the film is crystallized by excimer laser annealing to form a polycrystalline silicon thin film 13 serving as an active layer.

This polycrystalline silicon thin film 13 is processed into the shape of a thin film transistor, and a silicon oxide film to be a gate insulating film 14a is formed thereon to a thickness of 85 nm. Tantalum oxide to be the second gate insulating film 14b is formed to a thickness of 50 nm on the silicon oxide. Next, two gate electrodes 15 are formed on tantalum oxide. The gate electrode 15 is made of titanium (Ti) of 80 nm so as to be in contact with tantalum oxide, and 100 nm of an alloy containing 7.4% of zirconium (Zr) in aluminum (Al) on titanium.
m.

After the dual gate electrode is formed, only the LDD region of the thin film transistor and the space between both gate electrodes of the thin film transistor are covered with tantalum oxide, and the tantalum oxide on the source and drain regions is selectively removed.

After processing the tantalum oxide thin film into the above-described shape, as shown in FIG. 2 (b), phosphorus (P) is ion-doped with an acceleration voltage of 80 KV and an implantation dose of 1 × 10 ¹⁵ /.
Impurities are implanted at cm ² . In the ion doping method, a gas obtained by mixing hydrogen gas with PH ₃ at a concentration of 5% is plasma-decomposed by high-frequency discharge, and the generated ions are injected into a sample without a mass separation step.

Therefore, the source and drain regions of the thin film transistor are formed of a single layer of silicon oxide,
The D region and the region between both gate electrodes are implanted through a laminated film of tantalum oxide and silicon oxide, and the source and drain regions of the high concentration impurity implantation region 13c and the low concentration impurity implantation region 13b are formed by a single impurity implantation process. LDD regions are formed simultaneously.

Further, at this time, the two gate electrodes of the thin film transistor are connected only by the low-concentration impurity implantation region 13b made of a polycrystalline silicon thin film into which the same concentration of the low-concentration impurity is implanted as the LDD region.

Incidentally, the polycrystalline silicon thin film under the gate electrode 15 becomes the channel region 13a of the thin film transistor. After the impurity is injected into the thin film transistor, FIG.
As shown in (1), the tantalum oxide thin film on the LDD region is removed.

Thereafter, as shown in FIG. 2D, an interlayer insulating film 16 made of silicon oxide is formed. Silicon oxide is formed at 430 ° C. by using a normal pressure CVD method,
It is possible to activate the impurities implanted simultaneously in this step.
Finally, after opening a contact hole, source / drain electrodes 21 and 22 are formed, and a thin film transistor is completed.

According to the thin film transistor formed as described above, the size between the respective gate electrodes is determined only by the minimum line width of the exposing machine, as in the first embodiment. The size can be greatly reduced, and the OFF current of the thin film transistor can be significantly reduced by performing the tantalum oxide removing step.

(Embodiment 3) FIG. 3 is a diagram showing a manufacturing process of an active matrix array used in a liquid crystal display device according to (Embodiment 3) of the present invention.

First, as shown in FIG. 3A, an amorphous silicon thin film is formed with a thickness of 50 nm by a plasma CVD method on a glass substrate 11 whose surface is coated with silicon oxide. Amorphous silicon is heat-treated in nitrogen at 450 ° C. for 90 minutes to reduce the hydrogen concentration in the film, and then crystallized by excimer laser annealing to form a polycrystalline silicon thin film 1.
Form 3

The polycrystalline silicon thin film 13 is processed into the shape of a thin film transistor, and 85 nm of silicon oxide to be the gate insulating film 14a is formed. A 50 nm tantalum oxide to be the second gate insulating film 14b is formed over the silicon oxide.

Next, a gate electrode 15 is formed on the p-channel thin film transistor. The gate electrode 15 is formed by forming titanium (Ti) to 80 nm so as to be in contact with tantalum oxide, and forming 150 nm of an alloy containing zirconium (Zr) in aluminum (Al) on titanium to a total of 230 n.
m. At this time, the top of the n-channel thin film transistor is covered with a gate electrode material.

Thereafter, boron is implanted into the source and drain regions of the p-channel thin film transistor. Boron was implanted using an ion doping method at an acceleration voltage of 60 KV and a dose of 5 × 10 ¹⁵ / cm ² .

After boron ion implantation, a gate electrode 15 is formed on the n-channel thin film transistor as shown in FIG.
To form The gate electrode of the pixel TFT has a dual gate structure, and the tantalum oxide film on the LDD region and between the two gate electrodes of the pixel TFT is left, and the tantalum oxide on the source and drain regions is selectively removed. After processing the tantalum oxide thin film into the above-mentioned shape, phosphorus (P) is ion-doped at an acceleration voltage of 80 KV and an implantation dose of 1 ×.
Inject at 10 ¹⁵ / cm ² .

In the ion doping method, a gas obtained by mixing hydrogen gas with PH ₃ at a concentration of 5% is plasma-decomposed by high-frequency discharge, and the generated ions are injected into a sample without a mass separation step. Therefore, the impurity profile at the time of implantation is broader than that of the conventional ion implantation method.

In this manufacturing method, utilizing this feature, the LDD region and the source and drain regions are formed by one-time impurity implantation. At this time, the two gate electrodes of the pixel TFT are connected by a polycrystalline silicon thin film into which a low concentration impurity of the same concentration as the LDD region is implanted. After injecting impurities into the thin film transistor, LD is
The tantalum oxide thin film on the D region and between the two gate electrodes is removed. By performing the tantalum oxide removing step, the OFF current of the thin film transistor can be significantly reduced.

Next, as shown in FIG. 3C, a first interlayer insulating film 16 made of silicon oxide is formed. The silicon oxide is formed at 430 ° C. using a normal pressure CVD method, and the impurities implanted at the same time in this step can be activated. ITO (Indium-Tin-
Oxide) film, and a second interlayer insulating film 17 is formed.

After opening the contact holes, source / drain electrodes 21 and 22 are formed as shown in FIG. Further, after forming silicon nitride to be the protective film 23 by plasma CVD and performing annealing at 350 ° C. in a hydrogen atmosphere, the silicon nitride / silicon oxide laminated film on the pixel electrode 18 is selectively removed to form an active matrix. The array is completed.

FIG. 4 is an example of a configuration sectional view of a liquid crystal display device manufactured using the active matrix array of FIG. 3, in which a pixel portion is enlarged and displayed. Glass substrate 11
Active matrix and counter substrate 43 formed on
A liquid crystal 47 is held via an alignment film 46 between them.
Pixel electrode 1 with thin film transistor as switching element
8 is driven to charge the liquid crystal and display an image.

In this liquid crystal display device, elements can be miniaturized as compared with the case where a conventional double LDD thin film transistor is used for a pixel, and the aperture ratio of the liquid crystal display device is improved.
Here, 41 is a black matrix, 42 is a polarizing plate,
44 is a color filter and 45 is a transparent conductive layer.

In this embodiment, the case where the pixel driving thin film transistor has the LDD structure is described. However, the LDD structure may be used for at least a part of the n-channel thin film transistor in the driving circuit portion, and particularly, the reliability is improved. Is effective.

[0061]

As described above, according to the thin film transistor of the present invention, the size between the respective gate electrodes is determined only by the minimum line width of the exposure device. And it is possible to greatly reduce the element size.

According to the liquid crystal display device using the active matrix array of the present invention, since the element size of the thin film transistor for driving the pixel electrode can be reduced, the resolution can be improved, and the brightness due to the improvement of the aperture ratio can be improved. The effect of increase and power consumption reduction is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a thin film transistor according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a thin film transistor according to Embodiment 2 of the present invention.

FIG. 3 is a diagram showing a manufacturing process of an active matrix array for a liquid crystal display device according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view of a liquid crystal display device using an active matrix array according to Embodiment 3 of the present invention.

FIG. 5 is a diagram showing a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

Reference Signs List 11 glass substrate 13 polycrystalline silicon thin film 13b low-concentration impurity implantation region (LDD region) 13c high-concentration impurity implantation region (source and drain regions) 14a gate insulating film (silicon oxide thin film) 14b second gate insulating film (oxidation Tantalum thin film) 15 gate electrode 16, 17 interlayer insulating film 18 pixel electrode 21, 22 source and drain electrode 23 protective insulating film (silicon nitride)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 617N 612B F-term (Reference) 2H092 HA06 JA25 JA41 JA46 KA04 KA05 KA12 KA18 KB04 MA08 MA15 MA27 MA30 NA07 NA21 NA25 NA26 5C094 AA25 AA43 BA03 BA43 CA19 DA15 EA04 EA07 FB04 JA01 JA08 5F110 AA04 AA09 BB02 CC02 DD02 DD13 EE04 EE06 EE14 EE28 FF01 FF02 FF09 FF12 GG02 GG13 GG25 GG45 HJ01 HJ23 NN12 NN

Claims (8)

[Claims] An impurity having a lower concentration than the first concentration is implanted between a channel region, a source and a drain region into which an impurity is implanted at a first concentration, and between the channel region and the source and the drain region; A low-concentration impurity region, a polycrystalline silicon thin film provided with, a gate insulating film formed on the polycrystalline silicon thin film, and a plurality of gate electrodes provided on the gate insulating film. A thin film transistor comprising: the polycrystalline silicon thin film between each gate electrode is formed only by the low concentration impurity region. 2. The thin film transistor according to claim 1, wherein the gate insulating film on the channel region is formed of a laminated film of different types of gate insulating films. 3. The gate insulating film on the channel region is formed of a two-layer film of different types of gate insulating films, and the gate insulating film on the low-concentration impurity region is formed of a single-layer film. The thin film transistor according to claim 1. 4. A gate insulating film on a channel region is composed of a two-layer film of a tantalum oxide film located on a gate electrode side and a silicon oxide film or a silicon nitride film located on a polycrystalline silicon thin film side. The thin film transistor according to claim 3, wherein: 5. The thin film transistor according to claim 1, wherein the low-concentration impurity region of the polycrystalline silicon thin film has a sheet resistance of 5 KΩ to 150 KΩ. 6. The dose of the low concentration impurity region of the polycrystalline silicon thin film is 1 / th of the dose of the source and drain regions.
The thin film transistor according to claim 1, wherein the number is 10 or more and 以下 or less. 7. The thin film transistor according to claim 1, wherein the total length along the channel length direction of all the low-concentration impurity regions included between the source and drain regions is 6 μm or more and 12 μm or less. Thin film transistor. 8. An impurity having a lower concentration than the first concentration is implanted between the channel region and the source and drain regions into which impurities are implanted at a first concentration, and between the channel region and the source and drain regions. A pixel electrode comprising: a polycrystalline silicon thin film provided with a low-concentration impurity region; a gate insulating film formed on the polycrystalline silicon thin film; and a plurality of gate electrodes provided on the gate insulating film. A liquid crystal display device using an active matrix array, comprising: a thin film transistor for driving the pixel electrode; and a driving circuit integrated on the same substrate as the substrate on which the thin film transistor for driving the pixel electrode is formed. The thin film transistor that drives
8. A liquid crystal display device, which is the thin film transistor according to any one of 7.