JP2002135253A - Control device for distribution of atm cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the application efficiency of a buffer memory for input cells. SOLUTION: The ATM cell distribution control device 100 is provided with a data memory 104 for storing inputted cells, an address managing part 108 for managing the addresses of the data memory 104 in each sort of cells, an input interface 102, and an output interface 106. The input interface 102 sends the sort of an input cell to the address management 108, requires the address for storing the cell in the data memory 104 and writes the cell in the address of the data memory 104. The output interface 106 sends the sort of an output cell to the address managing part 108, requires the address storing the cell in the data memory 104, and reads out the cell from the address of the data memory 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a multiplexed A
The present invention relates to a distribution control device for selecting and distributing TM cells.

[0002]

2. Description of the Related Art ATM (Asynchronous Transfer mode)
In transmission, it is necessary for a device arranged at the end of the network to select cells multiplexed and to distribute the selected cells. FIG. 3 shows a conventional ATM.
It is a block diagram showing a schematic structure as an example of a cell distribution control device. As shown in FIG. 3, the conventional data distribution device includes an input interface unit 300 and buffer memories 302-1 and 302-2 each including n FIFO memories corresponding to the number of cell types (for example, VCI and VPI). ,
, 302-n, and an output interface unit 304.

The input interface unit 300 is supplied with a control signal from a device adjacent on the upstream side, and is supplied with an ATM cell via a main transmission line. The input interface unit 300 performs a receiving operation based on the control signal,
The TM cell is identified according to cell identification information such as VPI and VCI. Then, based on the identification information, each ATM cell is stored in a buffer memory 302 prepared for each cell identification information.
, 302-2,..., 302-n. The output interface unit 304 is supplied with a control signal from a downstream device adjacent to the transmission destination. The output interface unit 304 performs a transmission operation in response to a control signal, reads out a predetermined ATM cell in accordance with the status or request of a device adjacent on the downstream side, and transmits the ATM cell to the main transmission path.

[0004]

However, in the conventional distribution control device, when some failure occurs in the transmission destination of the cell and the transmission is temporarily stopped,
Buffer memory 302-prepared for each cell identification information
, 302-n is a problem. The capacity of the buffer memory is usually designed according to the failure occurrence time. However, in the conventional apparatus as described above, a buffer memory is prepared for each transmission destination, so that it is necessary for normal operation. It was necessary to prepare the above capacity. Also, when the distribution device adopts a configuration in which the reception operation is stopped when the buffer memory is full,
Once the ATM cell is received, the distribution process needs to be performed by checking the cell identification information and the like. Therefore, in order to prevent the received cell from being discarded, any one of the buffer memories prepared for each is required. It is necessary to stop all the receiving operations when it becomes full. For this reason, there was a problem that the use efficiency of the memory was deteriorated.

Accordingly, the present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide an ATM cell capable of efficiently operating a buffer memory for storing cells having a plurality of types. It is to provide a distribution control device.

[0006]

To achieve the above object, an ATM cell distribution control device according to the present invention comprises a data memory for storing input cells, and an address of the data memory for storing the cells. The address management means for managing each cell type, the address management means,
An input address requesting unit for transmitting the type of the input cell and requesting an address of the data memory for storing the cell, and a cell for writing the cell to the address of the data memory provided from the address management unit A writing unit, an output address requesting unit that sends the type of the output cell to the address management unit, and requests an address of the data memory in which the cell is stored; and the data provided from the address management unit. A cell reading means for reading the cell from an address of the memory.

In this case, the address management means includes a free address memory for holding a free address of the data memory, and a plurality of address memories prepared for each type of cell to be inputted. ,
An address memory for holding an address of the buffer memory storing a cell of a specific type; and when an address request is received from the input address requesting means, an address of 1 is read from the free address memory and written into the cell. Means for outputting to the means, and storing the address in the address memory corresponding to the type of the input cell; and, when an address request is received from the output address requesting means, the address corresponding to the type of the cell. Output cell control means for reading one address from the address memory, outputting the read address to the cell reading means, and storing the address in the free address memory can be provided.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one illustrated embodiment. FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. As shown in FIG. 1, an ATM cell distribution control device 100 according to the present invention includes an input interface unit 102 and a single buffer memory 1.
04, an output interface unit 106, and an address management unit 108.

The input interface unit 102 is supplied with a control signal from a device adjacent on the upstream side, and is supplied with an ATM cell via a main transmission line. The input interface unit 102 separates the cell identification information from the input cell (identification information separation function) and requests an address from the address management unit 108 based on the cell identification information (input address request function).
The input cell is written to the address on the buffer memory 104 corresponding to the obtained address (cell write function). That is, the input interface unit 102 performs a receiving operation based on the control signal, performs interface processing on the ATM cell, and performs the cell identification information (VPI, VCI
), And the cell identification information is stored in the address management unit 10.
8 Then, the address information is received from the address management unit 108 for each cell, and the address information and the ATM cell are supplied to the buffer memory 104 to execute the write control.

On the other hand, the output interface unit 106 includes:
A control signal including cell identification information is supplied from a device adjacent to the downstream side as a transmission destination. The output interface unit 106 sends the cell identification information to the address management unit 108, requests the storage address of the cell to be read (output address request function), and outputs the cell from the address on the buffer memory 104 corresponding to the acquired address. Read (cell read function) and output this to the requesting side. That is, the output interface unit 106 performs a transmitting operation in response to the control signal, and stores the cell identification information designated according to the status of the device adjacent on the downstream side or the request, to the address management unit 108.
To supply. Then, address information is received from the address management unit 108 for each cell, and the address information is supplied to the buffer memory 104 to execute read control. The buffer memory 104 reads the ATM cell in the storage area corresponding to the address information from the output interface unit 106 and supplies the ATM cell to the output interface unit 106. The read ATM cells are sent out onto the main transmission path via the output interface unit 106.

The address management unit 108 manages an address of the buffer memory 104 for storing a cell. The address management unit 108, as described above,
In response to a request from O.02, the address of the buffer memory 104 in which the input cell is stored is output, and in accordance with a request from the output interface unit 106, the address of the buffer memory 104 in which the cell to be output is stored is output.

FIG. 2 is a block diagram showing a specific configuration of the address management unit 108. As shown in FIG. 2, the address management unit 108 includes two decoders 200 and 208,
Two selectors 204 and 210, a free address memory 202 having a FIFO configuration, and address memories 206-1, 206-2, also having a FIFO configuration.
, 206-n.

The free address memory 202 is a memory for holding a free address of the buffer memory 104 for storing the cells. When no cell is stored in the buffer memory 104 (initial state), the free address memory 202 is used. The memory 202 stores all the head addresses of the buffer memory 104 that can store cells (memory = “FULL”).

A plurality of address memories 206-1, 206
,..., 206-n are the types of cells to be input,
For example, it is prepared for each VPI or VCI, and each address memory holds an address of the buffer memory storing a cell of a specific type. For example, the address memory 20
, 206-n can be used for storing cells of VPI # 1, # 2,..., #N, respectively. When no cell is stored in the buffer memory 104, each address memory is empty (memory = “EMPTY”). Here, each address memory 206-1, 206-2,..., 20
The capacity of 6-n is preferably the same as the capacity of the free address memory 202.

When the decoder 200 receives the cell identification information input from the input interface unit 102, it reads out the address 1 from the free address memory 202, returns it to the input interface unit 102, and sets the selector 204 By controlling the address, the address memory 206-1, 2 corresponding to the type of the input cell.
06-2,..., 206-n.

When the decoder 208 receives the identification information of the cell to be output from the output interface unit 106, the address memory 206-1, 206-2,.
Out of the address memory corresponding to the type of the cell, and return it to the output interface unit 106, and store the address in the free address memory 202.

Next, the operation of the ATM cell distribution control device will be described. When a cell is input to the input interface unit 102, the input interface unit 102 separates the cell identification information from the input cell and sends it to the address management unit 108. As shown in FIG. 2, the decoder 200 of the address management unit 108 that has received the cell identification information of the input cell, stores the address stored at the head address of the free address memory 202 (this is the buffer memory 104).
Address. ) And the selector 20
4 to output the address to the address memory 206-1 corresponding to the received cell identification information (for example, “VP = # 1”). The address read from the free address memory 202 is returned to the input interface unit 102 as a cell write destination address, and is stored in the address memory 206-1 selected via the selector 204. Similarly, when a cell is input to the input interface unit 102, the address management unit 108 controls the buffer memory 10 for storing the cell input.
4 as well as the address memory 206-1, 206-2,..., 206-corresponding to the VP.
The storage address of the cell is stored in any one of n.

Here, when the empty address memory 202 becomes empty (memory = “EMPTY”), it indicates that the buffer memory 104 is filled with cells (buffer full state). 108 notifies the input interface unit 102 to stop the receiving operation.

The input interface unit 102 that has received the address from the address management unit 108 specifies the address and writes an input cell on the buffer memory 104. Through the above operations, the input cells are sequentially written to the designated addresses of the buffer memory 104. In this case, the identification information of the input cell is managed by the address management unit 108.
The input cells are basically arranged in the buffer memory 104 according to the input order regardless of the type.

Next, when a request to output a cell having predetermined identification information is made to the output interface unit 106, the output interface unit 106 sends the cell identification information to the address management unit 108. The decoder 208 of the address management unit 108 having received the cell identification information of the output cell,
As shown in FIG. 2, the received cell identification information (for example,
Address memory 206-2 corresponding to “VP = # 2”)
To read the address stored in the first address (this is the address of the buffer memory 104). The read address is used as the cell read destination address as the output interface unit 106.
And stored again in the free address memory 202. If the address does not exist in the address memory corresponding to the specified identification information, the decoder 208 can return the fact to the output interface unit 106. This can be realized by checking the flag corresponding to each address memory.

The output interface unit 106 that has received the address from the address management unit 108 reads the cell from the buffer memory 104 by designating the address,
This is output to the requester. Through the above operation, the output cells are sequentially read from the designated address of the buffer memory 104 and output to the requesting device.

The embodiment of the present invention has been described with reference to the drawings. However, it is apparent that the present invention is not limited to the matters described in the above embodiments, and that changes, improvements, and the like can be made based on the description in the claims. In the present embodiment, the present invention has been described along an example in which the input interface section has a cell identification function, an address request function, and a cell write function. However, these functions are realized in separate configuration blocks. The present invention may be configured as described above.

[0023]

As described above, according to the present invention, cells can be stored by a single memory irrespective of the type of the cells, and therefore the use efficiency of the memory for storing the cells is significantly improved. Be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an address management unit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional ATM cell distribution control device.

[Explanation of symbols]

100 ATM cell distribution control device 102 Input interface unit 104 Buffer memory 106 Output interface unit 108 Address management unit 200, 208 Decoder 204, 210 Selector 202 Free address memory 206-1, 206-2, ..., 206-n Address memory

Claims (2)

[Claims] 1. A data memory for storing a cell to be inputted, and an address of the data memory for storing the cell,
Address management means for managing each cell type; input address request means for sending the input cell type to the address management means and requesting an address of the data memory for storing the cell; A cell writing means for writing the cell to the address of the data memory given by the address management means; and a type of the output cell to the address management means, and an address of the data memory where the cell is stored. An ATM cell distribution control device, comprising: an output address requesting unit for requesting a cell address; and a cell reading unit for reading the cell from an address of the data memory provided from the address management unit. 2. The address management means includes: a free address memory for holding a free address of the data memory; and a plurality of address memories prepared for each type of input cell, wherein each address memory is a specific address memory. An address memory for holding an address of the buffer memory storing cells of the following types; and when an address request is received from the input address requesting means, an address of 1 is read from the free address memory, and is read out from the cell writing means. And output to
Input cell control means for storing the address in the address memory corresponding to the type of the input cell; and, when an address request is received from the output address request means, one address from the address memory corresponding to the type of the cell. And output cell control means for outputting the read address to the cell read means and storing the address in the free address memory.
3. The ATM cell distribution control device according to claim 1.