JP2002135120A - Δς modulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means for eliminating spurious noise, generated when a DC signal is input to a ΔΣmodulator and to attempt improvement of S/N in a signal zone by noise-shaping effect. SOLUTION: An initial setting circuit 25 is controlled by a circuit 24 detecting a start trigger 23, which instructs the initiation of DC of an input signal 21 or of modulation movement. Initial value is given to an accumulator at the initiation of ΔΣ modulation. It is so constructed of that the ΔΣ modulator 20 will not be influenced in normal operation. Quantization noise is randomized and tone of spectrum is removed, by giving the initial value to the accumulator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a .DELTA..SIGMA. Modulator widely used in the fields of audio and communications, and more particularly to a technique for improving the S / N in a signal band.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional first-order ΔΣ modulator has a subtractor 2 for subtracting an input signal X (Z) and a feedback signal, and an output of the subtracter 2 for one sampling. A cumulative adder (integrator) 3 that performs cumulative addition (integration) for each clock; and a binary value of + Δ if the output of the cumulative adder 3 is ≧ the threshold level, and −Δ if <the threshold level The comparator 5 includes a comparator 5 that generates a quantized output signal Y (Z), and a delay unit 8 that feeds back a signal obtained by delaying the output signal Y (Z) by one sampling clock to the subtractor 2 as the feedback signal.

In FIG. 1, each element of the primary ΔΣ modulator is described by a Z function obtained by performing Z conversion, and Z ⁻¹ represents a delay element for delaying an input by one sampling clock.

The first-order ΔΣ modulator is a feedback system composed of the above-described elements, and has two delay units 4 and 8.
Is a modulator that converts an input signal 1 having a dynamic range of -Δ to + Δ into a binary quantized output signal (+ Δ, −Δ) 7 in synchronization with a sampling clock 9 for the input signal.

FIG. 5 is a diagram for explaining the operation principle of the primary Δ 次 modulator shown in FIG. Output signal Y in first-order ΔΣ modulator
(Z) is expressed as follows: Y (Z) = X (Z) + (1−Z ⁻¹ ) Q (Z) Expression 1 where input signal X (Z) and noise component (1−Z ⁻¹ )
Q (Z). Also, the spectrum Y of the output signal
(F) is Y (f) = X (f) + (1−e− ^2πfTs ) Q (f) Equation 2. Similarly, the input signal spectrum X (f) and the noise component (1−e ^−jωTs ) The sum of Q (f).

[0006] The noise component 16 of the second term on the right side of Equation 2 is
The input signal 10 that changes within the range of Δ to + Δ is represented by + Δ, −
The spectrum is obtained by multiplying the spectrum Q (f) of the quantization noise Q (Z) 6 generated when modulating the binary quantization signal 13 of Δ by the high-pass characteristic (1−e− ^jωTs ).

The spectrum Q of the quantization noise Q (Z) 6
(F) indicates that if the amplitude of the input signal 10 is sufficiently large, D
Since it can be regarded as white noise uniformly distributed from C to the Nyquist frequency 17, the noise component 16 included in the output signal spectrum Y (f) 14 is dispersed in a high band with the Nyquist frequency 17 as a peak. This effect is called a noise shaping effect and is one of the major features of the ΔΣ modulator.

To demodulate the input signal 10, a low-pass filter 19 having a cutoff frequency at the upper limit of the signal band 18 may be used to separate it from the noise component 16 dispersed in a high frequency band. After demodulation, the noise component 16 remaining in the signal band 18 is
Since the noise is reduced by the noise shaping effect, a high S / N ratio can be secured in the signal band 18, and the input signal can be faithfully demodulated.

However, when the input signal 10 is DC, the spectrum Q (f) of the quantization noise Q (Z) 6, which can be regarded as white noise if the amplitude of the input signal 10 is sufficiently large, has a tone component. Become. This tone component is based on the high-pass characteristic (1-
e ^−jωTs ), the output signal Y
(F) Appears as spurs in 14 and becomes a factor of deteriorating the S / N in the signal band 18.

When DC is applied to the input signal X (Z) 1 using the primary ΔΣ modulator of FIG. 1, the output signal Y (Z) 7
The mechanism by which spurs are generated in FIG.

[0011] As shown in FIG.
When the C input x (n) = + Δ / 2 is added, the output of the accumulator 3 becomes a periodic ramp waveform as shown in FIG. 6B, and the comparator 5 uses the threshold level 0 as a determination point. As shown in FIG. 6C, a binary quantized output signal y (n) 7 of + Δ and −Δ is generated.

As shown in FIG. 6C, the time response y (n) of the output signal 7 is a periodic signal that repeats + Δ and −Δ with a duty ratio corresponding to the ratio between the quantization step and the DC input.

In this example, the quantization step is (+ Δ) −
Since (−Δ) = 2Δ and the DC input is (+ Δ / 2), (+ Δ / 2) / (2Δ) = 1/4, and the time response y (n) of the output signal 7 is (−Δ, +
A repetition period signal having a duty ratio of 1: 4 (Δ, + Δ, + Δ) is obtained. As shown in FIG. 6E, the spectrum Y (f) of the output signal 7 includes ｛(sampling frequency /
2) Spurious will occur at a frequency point that is an integral multiple of ／.

The cause of the spurious is that the output signal 7
This is in the quantization noise 6 generated when the value is quantized. The time response q (n) of the quantization noise 6 at the time of DC input is shown in FIG.
A periodic signal as shown in FIG.
(F) has a tone characteristic as shown in FIG. 6 (f). Since this tone component cannot be completely suppressed even by the high-pass characteristic of the Δ 、 modulator, spurious is generated in the output signal 7.

FIG. 7 shows a conventional 3rd-order delta-sigma modulator shown in FIG. 4 connected in a three-stage cascade and adding the output signals of the respective 1st-order delta-sigma modulators to obtain a final output signal. FIG. 10 is a block diagram illustrating an example of a next MASH scheme ΔΣ modulator.

In FIG. 7, a third-order MASH type ΔΣ modulator 27 connects the first-order ΔΣ modulators 30 to 32 in a three-stage cascade, and outputs signals Y1 (Z) of the respective first-order ΔΣ modulators 30 to 32. , Y2 (Z) and Y3 (Z) are added to obtain a final output signal Y (Z) 29. If this method is adopted, a high-order and stable ΔΣ modulator can be formed, but the output signal Y (Z) 29 is multi-valued. Tertiary MASH
The output signal Y (Z) 29 of the system ΔΣ modulator 27 is given by Y (Z) = X (Z) + (1−Z ⁻¹ ) ³ Q3 (Z)... Here, Q3 (Z) is quantization noise generated in the third-stage ΔΣ modulator 32.

The spectrum Y (f) of the output signal 29
Is given by Y (f) = X (f) + (1−e− ^2πfTs ) ³ Q3 (f) Equation 4

As is clear from equations 3 and 4, the third-order MA
In order to remove the spurious generated at the time of DC input in the SH system ΔΣ modulator 27, the quantization noise Q3 (Z) generated in the third-order primary ΔΣ modulator 32 is randomized, and the tone of the spectrum is reduced. The point is to eliminate sex.

FIG. 8 shows a simulation result when a sine wave of 100 Hz is applied to the input signal X (Z) 28 of the conventional third-order MASH type ΔΣ modulator 27. The simulation was performed under the conditions of a quantization step Δ = 1, a sampling frequency fs = 1 kHz, and a total number of samples of 90.

FIG. 8A shows a first-order ΔΣ modulator 32 of the third stage.
8, the time response q3 (n) of the quantization noise generated in FIG.
(B) is the time response y (n) of the output signal 29, FIG.
Is the spectrum Q3 (f) of the quantization noise generated by the first-order ΔΣ modulator 32 at the third stage, and FIG.
Is the spectrum Y (f).

In the case of a sine wave input, the quantization noise q3
(N) is fully randomized (FIG. 8 (a)),
The spectrum Q3 (f) can be regarded as almost white (FIG. 8 (c)). According to Equation 4, the spectrum Y (f) of the output signal 29 is ^{equal to} the spectrum X (f) of the input signal 28 and the spectrum of the quantization noise (1-e- ^2πfTs ) ^{3 that} is noise- ^shaped by the third-order high-pass characteristic of the modulator. Q
3 (f), if the quantization noise Q3 (f) is whitened, as in this case, the noise component included in the output signal 29 is noise-shaped to a high frequency band, and the noise component is generated near the signal. S / N ratio is improved (FIG. 8)
(D)).

FIG. 9 shows that the input signal X (Z) 28 of the conventional third-order MASH type ΔΣ modulator 27 has DC (x (n) = 0).
Shows the simulation results when. The simulation conditions are the same as in the case of a sine wave input.

FIG. 9A shows a third-order primary ΔΣ modulator 32.
9, the time response q3 (n) of the quantization noise generated in FIG.
(B) is the time response y (n) of the output signal 29, FIG.
Is the spectrum Q3 (f) of the quantization noise generated in the first-order ΔΣ modulator 32 in the third stage, and FIG.
Is the spectrum Y (f).

The time response y (n) of the output signal 29 is
The four sample periods of (3, -3, 1, -1), the average of which is 0, which is the same as the DC input, and the input signal X (Z) 28 can be reproduced by passing through a low-pass filter (FIG. 9 ( b)). The quantization noise q3 (n) is (0, 1,
The repetition of 1, 1) results in a 4-sample periodic signal (FIG. 9A).

Therefore, due to this periodicity, tone-like quantization noise Q3 (f) is generated at a frequency that is an integral multiple of the sampling frequency / 4 cycle = 1 kHz / 4 = 250 Hz (FIG. 9C). This tonal quantization noise cannot be suppressed even through the third-order high-pass characteristic of the modulator, and appears as spurious in the spectrum Y (f) of the output signal 29.
This is a factor of deteriorating the in-band S / N (FIG. 9D).

Therefore, in order to remove spurious noise at the time of DC input, it is necessary to randomize the quantization noise 6 by using some method and whiten its spectrum. Conventionally, the following three methods have been proposed to remove the spurious of the output signal at the time of DC input.

(Conventional method) A method of adding a pseudo-random waveform dither to the input signal 1 to randomize the quantization noise 6 even at the time of DC input and to remove spurious components of the output signal 7.

(Conventional method) A method of reducing the quantization step, reducing the quantization noise 6 and removing the spurious of the output signal 7 by making the comparator 5 multi-valued.

(Conventional method) A method of adding a DC offset to the input signal 1, randomizing the quantization noise 6, and removing spurious components of the output signal 7 (Japanese Patent Laid-Open No. 7-143).
006, JP-A-2000-174627, etc.).

[0030]

However, each of the above conventional methods has the following disadvantages.

Since adding a pseudo-random waveform to the input signal 1 as in the method described above is the same as adding noise, there is a disadvantage in that the S / N deteriorates.

In the case of the above method, a multi-value comparator having two or more threshold levels is required. It is very difficult to keep the threshold levels of the multi-level comparator at equal intervals from the viewpoint of device variation and the like, so that it is difficult to perform completely linear multi-level quantization. The non-linearity of the multi-value comparator has a disadvantage that the output signal 7 is distorted.

The method described above is a method which can relatively easily remove spurious components of the output signal 7, but has a drawback that the influence of the DC offset generated in the output signal 7 must be removed in advance by calibration or the like.
Further, when the input signal 1 is digital, at least one bit is required for DC offset input, and there is a disadvantage that the dynamic range is deteriorated.

It is an object of the present invention to provide a method for reducing ΔΣ without deteriorating characteristics such as S / N, distortion, and dynamic range.
It is an object of the present invention to provide a means for removing spurious generated when a DC signal is input to a modulator and improving S / N in a signal band by a noise shaping effect.

[0035]

SUMMARY OF THE INVENTION The present invention provides a method for randomizing quantization noise generated when an output signal is quantized by giving an initial value to a cumulative adder in a .DELTA..SIGMA. , The tone characteristic of the quantization noise is removed (whitened), and the spurious appearing in the output signal at the time of DC input is suppressed.

As a result, even when DC is input, a .DELTA..SIGMA. Modulator that can eliminate spurious output signals and improve S / N by noise shaping can be realized.

[0037]

FIG. 1 is a block diagram showing an embodiment of a ΔΣ modulator according to the present invention.

In the present invention, in addition to the conventional Δ 与 え る modulator 20, an initial value setting circuit 25 for giving an initial value to the accumulator in the ΔΣ modulator 20 is added. Initial value setting circuit 2
5 is controlled by a DC detection circuit 24 for the input signal 21 or a circuit 24 for detecting a start trigger 23 for instructing the start of a modulation operation, when a DC component is detected in the input signal, or when ΔΣ modulation is started. At the time, an initial value is given to the accumulator, and during the steady operation, the ΔΣ modulator 20 is not affected at all.

By giving the initial value to the accumulator using the ΔΣ modulator according to the present invention, the quantization noise can be randomized and the tone characteristics of the spectrum can be removed. The selection of the initial value must be examined by simulation or the like, but the following can be said from experience. As the initial value, an integer multiple of ４ of an integer multiple of 量子 of the quantization step, and an integer multiple of ８ of an integer multiple of ４ of the quantization step are selected. That is, the initial value of the accumulator = ｛quantization step (2Δ) /
An initial value is selected according to an index of 2 ⁿ ｝ × integer (n → large). When digitally setting an initial value, it is effective to set the initial value with LSB = 1. This technique is more effective for higher order ΔΣ modulators.

Next, an embodiment of the present invention will be described using a third-order MASH system ΔΣ modulator as an example.

FIG. 2 shows a third-order MASH method ΔΣ according to the present invention.
FIG. 4 is a block diagram of a modulator, showing a conventional third-order MASH method Δ
In addition to the Σ modulator, a circuit 41 for providing an initial value k to the accumulator in the first-order primary ΔΣ modulator 37 is added.

Circuit 41 for providing initial value k to accumulator
Is connected to the initial value holding circuit 43 only when the start trigger 42 instructing the start of the modulation operation is detected, and the initial value k is added to the accumulator in the first-order primary ΔΣ modulator 37 to perform the modulation operation. Is controlled to be connected to the steady-state holding circuit 44 that gives an output value of 0 after the start, and is controlled so as not to affect the first-order ΔΣ modulator 37 during steady-state operation.

FIG. 3 shows a third-order MASH method ΔΣ according to the present invention.
DC (x (n) is applied to the input signal X (Z) 35 of the modulator 34.
= 0) is shown. A simulation was performed by giving a quantization step / 2 ⁷ as the initial value k of the accumulator.

FIG. 3A shows the first-order ΔΣ modulator 39 of the third stage.
Time response q3 (n) of the quantization noise generated at
(B) is the time response y (n) of the output signal 36, FIG.
Is the spectrum Q3 (f) of the quantization noise generated by the first-order ΔΣ modulator 39 in the third stage, and FIG.
Respectively show the spectrum Y (f).

By giving the initial value k to the accumulator, the time response y (n) of the output signal 36 becomes (6, -3,
1, 1,...), Which is 128 sample periods, which is randomized as compared with the case where the conventional method is used, but whose average is 0 which is the same as that of the DC input (FIG. 3B). The quantization noise q3 (n) is also randomized to a period of 128 samples (FIG. 3 (a)), and its tone is removed from its spectrum Q3 (f) and can be regarded as white noise (FIG. 3 (c)). .

As a result, the noise component included in the spectrum Y (f) of the output signal 36 despite the DC input is
Due to the high-pass characteristic of the ΔΣ modulator, noise shaping is performed, and the S / N in the band is improved (FIG. 3D).

[0047]

According to the present invention, the spurious generated when a DC input is applied to the ΔΣ modulator can be removed.
Even when a DC input is applied, the S / N in the signal band can be improved by the noise shaping effect.

Further, according to the present invention, unlike the conventional method, it is not necessary to mix pseudo random noise into the input signal, so that S / N degradation in the signal band does not occur. Also,
Since it is not necessary to use a multi-value comparator, the deterioration of the distortion factor does not occur. Furthermore, since there is no need to add a DC offset to the input, there is no need to perform calibration, and the dynamic range does not deteriorate.

Also, a ΔΣ PLL that uses a ΔΣ modulator to switch the frequency counter of a fractional-N PLL to remove spurious signals generated when the counter is switched and performs noise shaping in a high frequency band has attracted attention. If used, there is no need to add a DC offset to the input, so that a wide frequency setting dynamic range can be secured without deteriorating the frequency setting dynamic range (dynamic range of the input signal) of the PLL.

The reason is that, by giving an initial value to the accumulator in the ΔΣ modulator, quantization noise that is periodic at the time of DC input is randomized, and the tone property of the spectrum is removed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a ΔΣ modulator according to the present invention.

FIG. 2 is a block diagram of a third-order MASH type ΔΣ modulator according to the present invention.

FIG. 3 is a simulation result when DC is input to the third-order MASH type ΔΣ modulator of the present invention.

FIG. 4 is a block diagram of a conventional first-order ΔΣ modulator.

FIG. 5 is a diagram illustrating the operation principle of a conventional first-order ΔΣ modulator.

FIG. 6 is a diagram illustrating the operation of each unit when DC is input to a conventional primary ΔΣ modulator.

FIG. 7 is a block diagram of a conventional third-order MASH type ΔΣ modulator.

FIG. 8 is a simulation result when a sine wave is input to a conventional third-order MASH type ΔΣ modulator.

FIG. 9 is a simulation result when DC is input to a conventional third-order MASH type ΔΣ modulator.

[Explanation of symbols]

1, 21, 28, 35 Input signal: X (Z) 2 Subtractor 3 Cumulative adder (integrator) 4, 8 Delay unit 5 Comparator 6 Quantization noise 7, 26, 29, 36 Output signal: Y (Z) 9, 22 Sampling clock 10 Time response of input signal: x (n) 11 Spectrum of input signal: X (f) 12, 18 Signal band 13 Time response of output signal: y (n) 14 Spectrum of output signal: Y ( n) 15 signal component 16 noise component 17 Nyquist frequency (sampling frequency fs /
2) 19 Low-pass filter 20 ΔΣ modulator 23, 42 Start trigger 24 DC detection circuit / Start trigger detection circuit 25 Cumulative adder (integrator) initial value setting circuit 27, 34 Third-order MASH method ΔΣ modulator 30, 31, 32 , 37, 38, 39 Primary ΔΣ modulator 33, 40 Output signal adder 41 Circuit for giving initial value k to cumulative adder 43 Initial value holding circuit 44 0 value holding circuit

Claims (4)

[Claims] 1. A subtracter for subtracting an input signal and a feedback signal, a cumulative adder for cumulatively adding the output of the subtracter for each sampling clock, and binary-quantizing the output of the cumulative adder to output A comparator for generating a signal;
A ΔΣ modulator including a delay unit that generates a signal obtained by delaying the output signal by one sampling clock and outputs the signal as the feedback signal to the subtractor, when a DC component is detected in an input signal or when ΔΣ modulation starts. A ΔΣ modulator characterized in that initial value setting means for giving an initial value to the accumulator is provided. 2. The method according to claim 1, wherein the initial value setting means includes a DC detection circuit /
A start trigger detecting circuit and a cumulative adder initial value setting circuit, wherein the DC detecting circuit / start trigger detecting circuit detects a DC component of the input signal or instructs start of ΔΣ modulation operation 2. The ΔΣ modulator according to claim 1, wherein an initial value is given to the cumulative adder from the cumulative adder initial value setting circuit only when is detected. 3. The method according to claim 1, wherein the initial value is "(quantization step / 2
3. The ΔΣ modulator according to claim 1, wherein ⁿ ) is an integer, where n is an integer. 4. A ΔΣ modulator, comprising: a subtracter for subtracting an input signal and a feedback signal;
A cumulative adder for performing cumulative addition for each sampling clock;
A comparator for generating an output signal by binary-quantizing the output of the accumulator and a delay unit for generating a signal obtained by delaying the output signal by one sampling clock and outputting the signal as the feedback signal to the subtractor. 1st order Δ
Ｎ N modulators connected in N stages (N is plural) cascade
A first MASH type ΔΣ modulator, wherein the initial value setting means is configured to give an initial value to a cumulative adder in the first stage primary ΔΣ modulator. Item 4. The ΔΣ modulator according to any one of Items 1 to 3.