JP2002125362A - Method for improving main circuit element life time in semiconductor power converting device - Google Patents
Method for improving main circuit element life time in semiconductor power converting deviceInfo
- Publication number
- JP2002125362A JP2002125362A JP2000316000A JP2000316000A JP2002125362A JP 2002125362 A JP2002125362 A JP 2002125362A JP 2000316000 A JP2000316000 A JP 2000316000A JP 2000316000 A JP2000316000 A JP 2000316000A JP 2002125362 A JP2002125362 A JP 2002125362A
- Authority
- JP
- Japan
- Prior art keywords
- main circuit
- load
- circuit element
- carrier frequency
- life
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Dc-Dc Converters (AREA)
- Power Conversion In General (AREA)
- Inverter Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体電力変換装
置における主回路素子寿命の改善方法に関する。The present invention relates to a method for improving the life of a main circuit element in a semiconductor power conversion device.
【0002】[0002]
【従来の技術】従来インバータ主回路素子の寿命改善例
を図9に示す。このインバータ主回路82はIGBTa
〜IGBTfをスイッチング素子としている。モータ制
御回路83から出力されるモータ駆動信号はPWM発生
回路84によりパルス幅変調されIGBTドライブ回路
85を介して主回路のIGBTa〜IGBTfのベース
を駆動し、主回路82で電源81からの直流を三相交流
に変換してモータ88に出力する。タイマセット回路8
6及びIGBT保温回路87はIGBTの寿命を延ばす
ための回路で、タイマ設定回路86は予め設定されたモ
ータ88の始動開始時刻に基づいて主回路82のIGB
Ta〜IGBTfの保温開始時刻を演算する。IGBT
保温回路87は演算した保温開始時刻になると、主回路
のIGBTを保温させるための信号をPWM発生回路8
4に出力して各IGBTをモータ88に出力しないタイ
ミングで交互にオン・オフさせてIGBTa〜fの保温
を行う。これによりモータ88の始動開始まで各IGB
Tを暖めることができ、その後モータ88を運転しても
IGBTの温度は急上昇しなくなる。したがってモータ
運転開始時前後でのIGBTの温度変化を所定範囲に抑
制できるので、IGBTの寿命が改善される。(特開平
8−186905号)。2. Description of the Related Art FIG. 9 shows an example of improving the life of a conventional inverter main circuit element. This inverter main circuit 82 is IGBTa
To IGBTf are the switching elements. The motor drive signal output from the motor control circuit 83 is pulse width-modulated by a PWM generation circuit 84 and drives the bases of the main circuits IGBTa to IGBTf via an IGBT drive circuit 85. It is converted to a three-phase AC and output to the motor 88. Timer set circuit 8
6 and an IGBT heat retention circuit 87 are circuits for extending the life of the IGBT, and a timer setting circuit 86 is provided for the IGBT of the main circuit 82 based on a preset start start time of the motor 88.
The heat retention start time of Ta to IGBTf is calculated. IGBT
When the calculated heat retention start time comes, the heat retention circuit 87 outputs a signal for keeping the IGBT of the main circuit warm, using the PWM generation circuit 8.
4 and the IGBTs are alternately turned on and off at a timing when the IGBTs are not output to the motor 88 to keep the IGBTs Ta-f. As a result, each IGB is
T can be warmed, and the temperature of the IGBT does not rise rapidly even after the motor 88 is operated. Therefore, the temperature change of the IGBT before and after the start of the motor operation can be suppressed to a predetermined range, so that the life of the IGBT is improved. (Japanese Patent Application Laid-Open No. Hei 8-186905).
【0003】図10にインバータ主回路素子の寿命改善
の他の従来例を示す。このインバータ装置は、電源91
の三相交流を順変換部92で直流に変換し、コンデンサ
93で平滑した直流をPWM制御信号で制御される逆変
換部94で三相交流に変換してモータ99を駆動する。
搬送波信号発生部95からの搬送波信号は搬送波周波数
可変設定部96に入力し、PWM作成回路97は電圧指
令信号を搬送波周波数可変設定部96から出力される搬
送波信号でパルス幅変調して逆変換部94のスイッチン
グ素子Sのベースを駆動するためのPWM信号としてい
る。FIG. 10 shows another conventional example of improving the life of an inverter main circuit element. This inverter device has a power supply 91
The three-phase alternating current is converted to direct current by the forward converter 92, and the direct current smoothed by the capacitor 93 is converted to three-phase alternating current by the inverse converter 94 controlled by the PWM control signal to drive the motor 99.
The carrier signal from the carrier signal generator 95 is input to the carrier frequency variable setting unit 96, and the PWM generation circuit 97 performs pulse width modulation on the voltage command signal with the carrier signal output from the carrier frequency variable setting unit 96 to perform inverse conversion. It is a PWM signal for driving the base of the switching element S 94.
【0004】逆変換部94にはスイッチング素子Sの温
度を検出するサーミスタ98が設けられており、搬送波
周波数可変設定部96はサーミスタ98で検出した温度
を所定温度と比較し所定温度以上になると、その検出温
度に対し所定比率で搬送周波数を低減してPWM作成回
路97に出力する。搬送周波数が低減すると逆変換部9
4のスイッチング素子Sのスイッチング回数が低減しス
イッチング素子Sの温度上昇が低減するので、スイッチ
ング素子Sの破壊、劣化が回避される。(特開平11−
69836号)。The inverting section 94 is provided with a thermistor 98 for detecting the temperature of the switching element S. The carrier frequency variable setting section 96 compares the temperature detected by the thermistor 98 with a predetermined temperature. The carrier frequency is reduced at a predetermined ratio with respect to the detected temperature and output to the PWM generation circuit 97. When the carrier frequency decreases, the inverse conversion unit 9
4, the number of times of switching of the switching element S is reduced, and the temperature rise of the switching element S is reduced, so that the destruction and deterioration of the switching element S are avoided. (Japanese Patent Laid-Open No. 11-
No. 69836).
【0005】[0005]
【発明が解決しようとする課題】主回路用半導体素子は
図5に示すように構成されている。可変速装置の順変換
部や逆変換部で使用される主回路素子で発生する損失に
は定常損失とスイッチング損失がある。定常損失は主回
路素子がオンした時の電圧Vceと流れている電流Ic
との積で求まる。スイッチング損失は素子に流れる電流
Icでスイッチング1回当りの損失ESWが決まっており
スイッチング回数(PWMにおける搬送周波数)の積で
求まる。図8に主回路素子のVce−Ic特性例を示
す。The main circuit semiconductor element is constructed as shown in FIG. The loss generated in the main circuit element used in the forward conversion unit and the inverse conversion unit of the variable speed device includes a steady loss and a switching loss. The steady loss is determined by the voltage Vce and the current Ic flowing when the main circuit element is turned on.
And the product of The switching loss is determined by the product of the number of switching times (the carrier frequency in PWM), and the loss E SW per switching is determined by the current Ic flowing through the element. FIG. 8 shows an example of Vce-Ic characteristics of the main circuit element.
【0006】これら損失(定常損失+スイッチング損
失)によって、主回路素子のケースとジャンクション間
で温度上昇(ΔTj−c)が発生する。Due to these losses (steady-state loss + switching loss), a temperature rise (ΔTj−c) occurs between the case of the main circuit element and the junction.
【0007】ΔTj−c=Rth(j−c)×損失 Rth(j−c):ジャンクション−ケース間の熱抵抗 時定数は適用素子により異なるか、およそ0.2〜0.
3秒、0.5〜1秒で飽和する。ΔTj−c = Rth (j−c) × loss Rth (j−c): Thermal resistance between junction and case The time constant varies depending on the applied element, or approximately 0.2 to 0.
Saturates in 3 seconds, 0.5-1 second.
【0008】主回路素子の寿命のパラメータとして「パ
ワーサイクル」と「熱疲労」がある。パワーサイクル
は、温度の平衡状態から上記損失によってジャンクショ
ン温度Tjが上昇下降を繰り返す。このときの温度変化
幅ΔTjによって素子破壊に至るまでの温度上昇下降を
繰り返す回数が求まる特性である(図6)。There are "power cycle" and "thermal fatigue" as parameters of the life of the main circuit element. In the power cycle, the junction temperature Tj repeatedly rises and falls due to the above-mentioned loss from the temperature equilibrium state. This is a characteristic in which the number of times the temperature rises and falls until the element is destroyed is determined from the temperature change width ΔTj at this time (FIG. 6).
【0009】温度変化幅ΔTjが大きければ許容される
温度上昇下降の繰り返し回数は小さくなり、ΔTjが小
さければ許容される温度上昇下降の繰り返し回数は大き
くなる。これは主に図5に示す半導体電力変換素子内の
シリコンチップ13とボンディングワイヤ15とのボン
ディング部分に、熱による膨張収縮が繰り返されること
で機械的ストレスが加わりボンディング部分に劣化が生
じることに起因する。When the temperature change width ΔTj is large, the allowable number of repetitions of temperature rise / fall decreases, and when ΔTj is small, the allowable number of repetitions of temperature rise / fall increases. This is mainly because mechanical expansion is applied to the bonding portion between the silicon chip 13 and the bonding wire 15 in the semiconductor power conversion device shown in FIG. I do.
【0010】熱疲労もやはりパワーサイクル同様温度上
昇下降の繰り返しによる機械的ストレスである。但し、
ストレスの加わる部分はモジュールの冷却部(一般的に
は銅ベース板11)と絶縁基板12間或いは絶縁基板1
2とシリコンチップ13間の半田付け部分が主である。
これはモジュールの冷却部と絶縁基板で熱膨張係数が異
なるために発生する。熱疲労もパワーサイクル同様ケー
ス温度の変化幅が小さければ繰り返し許容回数は大きく
なり、上昇下降幅が大きくなれば繰り返し許容回数は小
さくなる。[0010] Thermal fatigue is also mechanical stress due to repetition of temperature rise and fall like a power cycle. However,
The stressed part is between the cooling part of the module (generally, the copper base plate 11) and the insulating substrate 12 or the insulating substrate 1
The main part is a soldered portion between the silicon chip 2 and the silicon chip 13.
This occurs because the thermal expansion coefficient differs between the cooling section of the module and the insulating substrate. As for the thermal fatigue, as in the case of the power cycle, the allowable number of repetitions increases if the variation width of the case temperature is small, and the allowable number of repetitions decreases if the increase / decrease width increases.
【0011】上記要因による寿命を延ばすには温度変化
幅を小さくすれば良い。通常、そのためには電流が多く
流れて損失が増大する条件下では搬送周波数を下げて損
失を減少させるか、或いは、容量の大きい素子を採用し
て損失を減らし温度変化幅を小さくする方法がとられ
る。In order to extend the life due to the above factors, the temperature change width may be reduced. Usually, for this purpose, under the condition that a large amount of current flows and the loss increases, the carrier frequency is lowered to reduce the loss, or a method of adopting a large-capacity element to reduce the loss and reduce the temperature change width is adopted. Can be
【0012】搬送周波数の減少は、電流制御性能の劣
化、騒音の増大、電流波形の悪化またそれによるモータ
の温度上昇を招く。また、素子容量を大きくした場合コ
スト増加素子サイズの増大またそれによる装置の大型化
の要因となる。A decrease in the carrier frequency causes a deterioration in current control performance, an increase in noise, a deterioration in current waveform, and a rise in motor temperature. Further, when the element capacity is increased, the cost increases, the element size increases, and the device becomes larger.
【0013】本発明は、上記課題に鑑みてなされたもの
であり、その目的とするところは、素子容量を大きくし
たり制御性能を下げることなく素子寿命を延ばすことが
できる半導体電力変換装置における主回路素子寿命の改
善方法を提供することにある。The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor power conversion device capable of extending the life of an element without increasing the element capacity or reducing control performance. An object of the present invention is to provide a method for improving the life of a circuit element.
【0014】[0014]
【課題を解決するための手段】本発明の半導体電力変換
装置における主回路素子寿命の改善方法は、主回路にI
GBTなどのパワーサイクル寿命や熱疲労寿命を持つ半
導体素子を用いた電力変換装置において、低負荷時にパ
ルス幅変調用の搬送周波数を高くして前記半導体素子の
スイッチング損失を増加させ、半導体素子のジャンクシ
ョン温度を高くすることで高負荷時のジャンクション温
度との差を小さくすることを特徴とするものである。A method for improving the life of a main circuit element in a semiconductor power conversion device according to the present invention includes the steps of:
In a power converter using a semiconductor device having a power cycle life or a thermal fatigue life such as a GBT, a carrier frequency for pulse width modulation is increased at a low load to increase a switching loss of the semiconductor device, thereby increasing a junction of the semiconductor device. It is characterized in that the difference from the junction temperature under a high load is reduced by increasing the temperature.
【0015】または、低負荷時に半導体素子のゲート抵
抗を大きくして前記半導体素子のスイッチング損失を増
加させ、半導体素子のジャンクション温度を高くするこ
とで高負荷時のジャンクション温度との差を小さくする
ことを特徴とするものである。Alternatively, the gate resistance of the semiconductor element is increased at a low load to increase the switching loss of the semiconductor element and the junction temperature of the semiconductor element is increased to reduce the difference from the junction temperature at a high load. It is characterized by the following.
【0016】これら方法は併用することができる。These methods can be used in combination.
【0017】[0017]
【発明の実施の形態】実施の形態1 本発明の負荷状態に応じて搬送周波数を変える方法の例
を図1、図2を用いて説明する。図1は、モータ9を速
度制御する電力変換装置の構成を示す。PWM演算部1
はパルス幅変調に使用する搬送周波数を周波数指令によ
り調節しうるように構成されている。PWM演算部1に
は周波数指令、電圧指令が入力し、出力されるPWM信
号はゲートドライブ回路2を介して主回路3のスイッチ
ング素子Sのゲートを駆動し、インバータ主回路3から
周波数指令、電圧指令に応じた交流をモータ9に出力さ
せる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An example of a method of changing a carrier frequency according to a load state according to the present invention will be described with reference to FIGS. FIG. 1 shows a configuration of a power conversion device that controls the speed of the motor 9. PWM operation unit 1
Is configured such that a carrier frequency used for pulse width modulation can be adjusted by a frequency command. A frequency command and a voltage command are input to the PWM operation unit 1, and the output PWM signal drives the gate of the switching element S of the main circuit 3 via the gate drive circuit 2, and the frequency command and the voltage are output from the inverter main circuit 3. The motor 9 outputs an alternating current according to the command.
【0018】上記搬送周波数の調節は、図2に示すよう
にインバータの負荷状態を監視して、軽負荷のときは搬
送周波数を高くし、重負荷のときは搬送周波数を高くす
る。負荷状態の監視は例えばインバータ主回路3からモ
ータ9に出力される電力又は電流、或いはスイッチング
素子Sの温度等を検出し、所定の値と比較して軽負荷、
重負荷を判断する。The carrier frequency is adjusted by monitoring the load condition of the inverter as shown in FIG. 2, and increasing the carrier frequency when the load is light and increasing the carrier frequency when the load is heavy. For monitoring the load state, for example, the power or current output from the inverter main circuit 3 to the motor 9 or the temperature of the switching element S is detected and compared with a predetermined value to reduce the light load,
Determine heavy load.
【0019】軽負荷時搬送周波数を高くするとスイッチ
ング素子のスイッチング回数が増し、素子の損失が増加
してジャンクション温度Tjが上昇する。また、重負荷
時搬送周波数を低くするとスイッチング回数が減り、素
子の損失が減少してジャンクション温度Tjが低下す
る。しかして軽負荷時と重負荷時のジャンクション温度
Tjの差が小さくなり、スイッチング素子の寿命が長く
なる。When the carrier frequency at the time of light load is increased, the number of times of switching of the switching element increases, the loss of the element increases, and the junction temperature Tj increases. Further, when the carrier frequency under heavy load is reduced, the number of times of switching is reduced, the loss of the element is reduced, and the junction temperature Tj is lowered. As a result, the difference between the junction temperature Tj at the time of light load and the junction temperature Tj at the time of heavy load becomes small, and the life of the switching element becomes longer.
【0020】上記では軽負荷時、重負荷時共に搬送周波
数を変更しているが、軽負荷時のみ搬送周波数を高くす
ることでもスイッチング素子の寿命を延ばすことができ
る。実施の形態2本発明の負荷状態に応じてゲート抵抗
を切り替える方法の例を図3、図4を用いて説明する。
図3はインバータ主回路素子のゲート回路を示す。ゲー
トドライブ回路21の出力端子23と主回路素子Sのゲ
ート端子G間に、抵抗R1と、抵抗R2とゲート抵抗切
替スイッチSWの直列回路を並列に接続し、スイッチS
Wをオフとしたときゲート抵抗はR1のみとなりゲート
抵抗(値)が大きくなり、スイッチSWをオンとしたと
きゲート抵抗R1、R2が並列となりゲート抵抗が小さ
くなるようにしてある。In the above description, the carrier frequency is changed under both a light load and a heavy load. However, by increasing the carrier frequency only under a light load, the life of the switching element can be extended. Second Embodiment An example of a method of switching a gate resistance according to a load state according to the present invention will be described with reference to FIGS.
FIG. 3 shows a gate circuit of the inverter main circuit element. Between the output terminal 23 of the gate drive circuit 21 and the gate terminal G of the main circuit element S, a series circuit of a resistor R1, a resistor R2 and a gate resistance changeover switch SW is connected in parallel.
When W is turned off, the gate resistance becomes only R1 and the gate resistance (value) increases, and when the switch SW is turned on, the gate resistances R1 and R2 become parallel to reduce the gate resistance.
【0021】そして、図4に示すようにインバータの負
荷状態を監視し、軽負荷時はスイッチSWをオフさせて
ゲート抵抗を大きくし、重負荷時はスイッチSWをオン
させてゲート抵抗を小さくする。ゲート抵抗が大きくな
ると主回路素子の損失が増え、ゲート抵抗が小さくなる
と主回路素子Sの損失が減るので、軽負荷時と重負荷時
の主回路素子ジャンクション温度Tjの差は小さくな
る。Then, as shown in FIG. 4, the load state of the inverter is monitored. When the load is light, the switch SW is turned off to increase the gate resistance, and when the load is heavy, the switch SW is turned on to reduce the gate resistance. . When the gate resistance increases, the loss of the main circuit element increases, and when the gate resistance decreases, the loss of the main circuit element S decreases. Therefore, the difference between the main circuit element junction temperature Tj under light load and under heavy load decreases.
【0022】上記では軽負荷時、重負荷時にゲート抵抗
値を大、小に切り換えているが、軽負荷時のみゲート抵
抗を大きくすることでもスイッチング素子の寿命を延ば
すことができる。ゲート抵抗・スイッチング特性例を図
7に示す。In the above description, the gate resistance is switched between large and small at light load and heavy load. However, the life of the switching element can be extended by increasing the gate resistance only at light load. FIG. 7 shows an example of gate resistance and switching characteristics.
【0023】上記本発明の方法では、軽負荷時に素子の
損失を増加させているが、重負荷時より損失が大きくな
るわけではないので、冷却能力を強化することなく実施
できる。以下に、ゲート抵抗を切替える方法による素子
寿命の改善例を示す。In the above-described method of the present invention, the loss of the element is increased at light load, but the loss is not greater than at heavy load, so that the method can be carried out without enhancing the cooling capacity. Hereinafter, an example of the improvement of the element lifetime by the method of switching the gate resistance will be described.
【0024】[0024]
【表1】 [Table 1]
【0025】主回路素子の通常損失特性、スイッチング
損失特性、パワーサイクル寿命、熱抵抗等適用素子によ
って異なる。表1の条件で素子損失を求める。搬送周波
数は基準を6KHzとする。また、素子のジャンクショ
ン−ケース間の熱抵抗は0.1〔℃/W〕とする。The normal circuit characteristics, switching loss characteristics, power cycle life, thermal resistance, and the like of the main circuit element vary depending on the applied element. Element loss is determined under the conditions shown in Table 1. The carrier frequency is set at 6 KHz. The thermal resistance between the junction and the case of the element is set to 0.1 [° C./W].
【0026】高負荷時の損失は、 170+0.016×6000=266W 従って、ジャンクション−ケース間の温度上昇は、2
6.6℃となる。The loss under high load is 170 + 0.016 × 6000 = 266 W Therefore, the temperature rise between the junction and the case is 2
It will be 6.6 ° C.
【0027】上記対策を講じない場合の低負荷時の損失
は、 33+0.005×6000=63W よって、ジャンクション−ケース間の温度上昇差は、
6.3℃となる。If the above measures are not taken, the loss at low load is 33 + 0.005 × 6000 = 63 W. Therefore, the difference in temperature rise between the junction and the case is:
6.3 ° C.
【0028】これにより、低負荷時と高負荷時の温度上
昇差は。20.3℃となる。As a result, the difference in temperature rise between when the load is low and when the load is high is as follows. 20.3 ° C.
【0029】図6に示したパワーサイクル特性におい
て、温度変化幅ΔTj=20℃のパワーサイクル寿命は
約1850万回となる。ここでΔTjを1℃小さくする
とパワーサイクルは約1960万回となり、5〜6%寿
命を延ばすことが可能となる。ここで軽負荷時の温度上
昇を1℃高くするには、損失を10W増やせばよい。こ
れを実施の形態1の搬送周波数を変える方法で行うと、
軽負荷時搬送周波数を6KHzから8KHzに変えれば
良い。In the power cycle characteristics shown in FIG. 6, the power cycle life at a temperature change width ΔTj = 20 ° C. is about 18.5 million times. Here, if ΔTj is reduced by 1 ° C., the power cycle becomes about 19.6 million times, and the life can be extended by 5 to 6%. Here, to increase the temperature rise under light load by 1 ° C., the loss may be increased by 10 W. When this is performed by the method of changing the carrier frequency in the first embodiment,
The carrier frequency at light load may be changed from 6 KHz to 8 KHz.
【0030】また、上記の例ではゲート抵抗のみ切り換
えても0.43℃しか差を詰められないが、更に大きな
ゲート抵抗を選択してやることで実現可能である。In the above example, even if only the gate resistance is switched, the difference can be reduced only by 0.43 ° C., but can be realized by selecting a larger gate resistance.
【0031】実施の形態1と2の方法は併用可能であ
り、ゲート抵抗で補えい分は搬送周波数を増加すること
でまかなうことが可能である。The methods of Embodiments 1 and 2 can be used together, and the portion compensated by the gate resistance can be covered by increasing the carrier frequency.
【0032】[0032]
【発明の効果】本発明は、上述のとおり構成されている
ので、以下に記載する効果を奏する。 (1)軽負荷時と重負荷時の主回路素子のジャンクショ
ン温度差を小さくできるので、主回路素子の寿命が改善
される。 (2)軽負荷時に主回路素子の損失を増加させるが重負
荷時より損失が大きくなるわけではないので、冷却能力
を強化することなく主回路素子の寿命を改善できる。 (3)負荷状態を監視して、搬送周波数又はゲート抵抗
を変えるだけであるから、簡単に実施できる。 (4)搬送周波数を変える方法とゲート抵抗を変える方
法を併用することで主回路素子の軽負荷時と重負荷時の
ジャンクション温度差を更に小さくすることができる。Since the present invention is configured as described above, the following effects can be obtained. (1) Since the junction temperature difference between the main circuit element under light load and heavy load can be reduced, the life of the main circuit element is improved. (2) Although the loss of the main circuit element is increased at light load, the loss is not larger than at heavy load, so that the life of the main circuit element can be improved without strengthening the cooling capacity. (3) Since it is only necessary to monitor the load state and change the carrier frequency or the gate resistance, it can be easily implemented. (4) By using both the method of changing the carrier frequency and the method of changing the gate resistance, the junction temperature difference between the light load and the heavy load of the main circuit element can be further reduced.
【図1】実施の形態1にかかるインバータのブロック
図。FIG. 1 is a block diagram of an inverter according to a first embodiment.
【図2】実施の形態1の方法説明図。FIG. 2 is a diagram illustrating a method according to the first embodiment.
【図3】実施の形態2にかかるインバータのブロック
図。FIG. 3 is a block diagram of an inverter according to a second embodiment;
【図4】実施の形態2の方法説明図。FIG. 4 is a diagram illustrating a method according to the second embodiment.
【図5】主回路用半導体素子の内部構成例を示す概略側
面図。FIG. 5 is a schematic side view showing an example of the internal configuration of a semiconductor element for a main circuit.
【図6】スイッチング素子のパワーサイクル特性例を示
すグラフ。FIG. 6 is a graph showing an example of power cycle characteristics of a switching element.
【図7】IGBTのゲート抵抗−スイッチング損失特性
例を示すグラフ。FIG. 7 is a graph showing an example of a gate resistance-switching loss characteristic of an IGBT.
【図8】スイッチング素子のコレクタ・エミッタ間飽和
特性例を示すグラフ。FIG. 8 is a graph showing an example of a collector-emitter saturation characteristic of a switching element.
【図9】従来例を示すブロック図。FIG. 9 is a block diagram showing a conventional example.
【図10】従来他の例を示すブロック図。FIG. 10 is a block diagram showing another conventional example.
1…PWM演算部 3…主回路 21…ゲートドライブ回路 S…主回路素子 R1,R2…ゲート抵抗 SW…ゲート抵抗切替スイッチ DESCRIPTION OF SYMBOLS 1 ... PWM calculation part 3 ... Main circuit 21 ... Gate drive circuit S ... Main circuit element R1, R2 ... Gate resistance SW ... Gate resistance changeover switch
───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5H007 AA03 AA06 BB06 CA01 CB05 CC07 DB01 DC02 DC03 DC08 EA14 5H730 AA12 AS13 BB57 CC01 DD02 FG06 FG07 FG22 XX38 ZZ13 5H740 AA08 BA11 BB05 BB09 BB10 BC06 KK01 MM08 NN17 NN18 PP01 PP02 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)
Claims (3)
寿命や熱疲労寿命を持つ半導体素子を用いた電力変換装
置において、 低負荷時にパルス幅変調用の搬送周波数を高くして前記
半導体素子のスイッチング損失を増加させ、半導体素子
のジャンクション温度を高くすることで高負荷時のジャ
ンクション温度との差を小さくすることを特徴とする半
導体電力変換装置における主回路素子寿命の改善方法。In a power converter using a semiconductor element having a power cycle life or a thermal fatigue life such as an IGBT for a main circuit, a switching frequency of the semiconductor element is increased by increasing a carrier frequency for pulse width modulation at a low load. And increasing the junction temperature of the semiconductor element to reduce the difference from the junction temperature under a high load.
寿命や熱疲労寿命を持つ半導体素子を用いた電力変換装
置において、 低負荷時に半導体素子のゲート抵抗を大きくして前記半
導体素子のスイッチング損失を増加させ、半導体素子の
ジャンクション温度を高くすることで高負荷時のジャン
クション温度との差を小さくすることを特徴とする半導
体電力変換装置における主回路素子寿命の改善方法。2. In a power converter using a semiconductor element having a power cycle life or thermal fatigue life such as an IGBT in a main circuit, a gate resistance of the semiconductor element is increased at a low load to increase a switching loss of the semiconductor element. A method for improving the life of a main circuit element in a semiconductor power conversion device, wherein the difference from the junction temperature under high load is reduced by increasing the junction temperature of the semiconductor element.
することを特徴とする半導体電力変換装置における主回
路素子の寿命改善方法。3. A method for improving the life of a main circuit element in a semiconductor power conversion device, wherein the method according to claim 1 and the method according to claim 2 are used together.
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