JP2002124999A - Method and device for confirming psk synchronization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow easy confirmation of synchronization of a PSK signal by tuning a radio device. SOLUTION: There are provided a PLL phase synchronizing part 101 of a Costas loop of complex number, an AFC part 102, and a beat sound generating part 103. The phase error in a BPSK signal by complex calculation is acquired from an arc tangent circuit 7, and at a second adder/subtracter 12, a frequency error is calculated based on the phase error. The frequency error is integrated by an integrator 13, and a sine wave is generated by a sine wave signal generator 14 according to an output frequency of the integrator 13, which is amplified by an amplifier 15 so that a speaker 16 is rumbled with a beat sound. Establishment of synchronization is judged by confirming a zero beat.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a PSK (Phase Shi
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for confirming a tuning state of a received signal when receiving a ft Keying) signal, and more particularly to a method and apparatus for facilitating tuning confirmation.

[0002]

2. Description of the Related Art There are various types of communication in amateur radio communication as in business radio communication. In recent years, a PSK (Phase Shift Keying) signal has been used, for example, in a radio carrier using single sideband modulation. Generally transmitted by PS
A communication form called K31 has attracted attention because it has advantages such as reliable communication even when the energy per noise to noise power density is low and narrow band characteristics.

[0003]

By the way, this PSK
In the case of receiving a signal from a transmitting station in search of a communication partner in the communication using 31 and trying to start communication by tuning to the received signal, it is necessary to synchronize with a modem. For example, if the radio wave of the partner station is a single sideband modulated wave (hereinafter referred to as "SSB"), the tuning is performed to the extent that the tuning by the modem is possible by listening to the SSB sound from the wireless receiver. There is a need. However,
Actually, it is not easy to judge whether or not tuning has been achieved by listening to a subtle change in the SSB sound, which requires skill, and a tuning confirmation device that is convenient for tuning operation is desired. The present invention has been made in view of the above situation, and
An object of the present invention is to provide a PSK tuning confirmation method and a device for easily confirming tuning by tuning a wireless receiver in communication using an SK signal. It is another object of the present invention to provide a PSK tuning confirmation method and a PSK tuning confirmation method that can surely and easily confirm that tuning has been achieved even when the S / N ratio of a received signal has decreased. Is to do.

[0004]

In order to achieve the above object, a PSK tuning confirmation method according to the present invention comprises a PSK tuning confirmation method for confirming a PSK signal modulated by a radio carrier in a radio receiver. A method for calculating a phase error of the PSK signal by a complex operation based on a low-frequency output signal of the wireless receiver, obtaining a frequency error from the phase error, integrating the frequency error, and integrating the frequency error by a predetermined multiple. A frequency signal is generated, and the audible frequency signal is applied to an electric signal / sound wave converting means for converting an electric signal into a sound wave signal to sound the electric signal / sound wave converting means, and the sound of the electric signal / sound wave converting means disappears. With this, it is determined that the tuning of the PSK signal has been achieved in the wireless receiver.

In such a configuration, particularly, a so-called beat sound is generated by using an integrated value of the frequency error. Therefore, even when the S / N ratio is low, the beat sound when tuning is achieved disappears. It is easy to obtain a so-called zero beat, and it is possible to easily and surely confirm that synchronization has been achieved.

In order to achieve the above object, a PSK tuning confirmation apparatus according to the present invention comprises a complex phase error detecting means for calculating a phase error of an input PSK signal by a complex operation, and a complex phase error detecting means. Frequency integration means for obtaining a frequency error based on the output signal and integrating the frequency error with a predetermined integration time constant, and beat sound generation means for generating an audible frequency sound corresponding to the frequency of the output signal of the frequency integration means Is provided.

This configuration is particularly suitable for realizing and executing the above-described PSK tuning confirmation method, and each means is implemented by so-called hardware or, for example, a DSP (Digital Signal Processor). It can be realized by executing software by an IC having such a high arithmetic processing function.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. The members, arrangements, and the like described below do not limit the present invention, and can be variously modified within the scope of the present invention. First, a configuration of a PSK tuning confirmation device (hereinafter, referred to as “this device”) according to an embodiment of the present invention will be described with reference to FIG. At first, the device is generally called a PLL (Phaseed Locked Loop) for phase synchronization in which a complex Costas loop is formed.
p) The phase synchronization unit 101 and an AFC (Aut
A with a loop formed
An FC unit 102 is provided, and a beat sound generating unit 103 that converts a frequency error into an audible frequency sound and outputs the sound is provided. Next, a specific configuration will be described. First, in the input stage of the present device,
An analog-to-digital converter for converting a BPSK signal obtained from a so-called audio output (low-frequency output signal) terminal of a wireless receiver (not shown) from an analog signal to a digital signal (in FIG. 1, denoted as “ADC”) 1 is provided. An output terminal of the analog / digital converter 1 is connected to a band-pass filter (denoted as “BPS” in FIG. 1) 2 and an S / N detector (denoted as “S / NDET” in FIG. 1) 3 Is connected to the input terminal of. Further, the output terminal of the band-pass filter 2 is connected to another input terminal of the S / N detector 3.

The band-pass filter 2 is a narrow-band band-pass filter that allows only a BPSK signal converted into a digital signal to pass therethrough. The output signal S 1 is applied to the S / N detector 3 as described above. And a signal complexing circuit (denoted as "COM CON" in FIG. 1)
4 is applied. The S / N detector 3 is
It calculates the S / N of the input signal, and calculates the S / N ratio from the ratio of the power of the signal before passing through the band-pass filter 2 to the power of the signal after passing through the band-pass filter 2. ing. The signal complex circuit 4 is for converting a signal output from the band-pass filter 2 into a complex number. The signal S1 from the band-pass filter 2 input to the signal complex circuit 4 is generally S1 = A sin (ωt + n
Φ). Here, A is the amplitude of the signal S1,
n is 0 or 1, and Φ is π radian. Then, such a signal S1 is adapted to be outputted as ^{Ae i (ω t + n Φ} ) and complex number has been signal S2 by the signal complex circuit 4, the output of the signal complex circuit 4 The signal S2 is supplied to the heterodyne mixer 5
To be applied. In FIG. 1,
Portions indicating signal flows represented by outline arrows (between the signal complexing circuit 4 and the heterodyne mixer 5, between the heterodyne mixer 5 and the complex local oscillator 10, between the heterodyne mixer 5 and the multiplier 6, And between the multiplier 6 and the arc tangent circuit 7) indicate that the part is treated as a complex number, and specifically, a signal corresponding to a real part,
This means that there are two types of signals corresponding to the imaginary part.

The heterodyne mixer 5 receives an output signal from a complex local oscillator (indicated as “complex LoOSC (VCO)” in FIG. 1) 10 in addition to the signal from the signal complexing circuit 4. The two input signals are subjected to heterodyne mixing to output an output signal S3. The details of the output signal S3 will be described later together with the output signal of the complex local oscillator 10. A multiplier 6 having two input terminals is provided at a stage subsequent to the heterodyne mixer 5, and the output signal S3 of the heterodyne mixer 5 is applied to either of the two input terminals. It has become. Then, an output signal as a result of multiplication in the multiplier 6 (details will be described later)
Is an arc tangent circuit ("tan" in FIG. 1).
^{- 1} "hereinafter) 7 is inputted to, a loop filter (referred to as" LPF "in Fig. 1) 8, the multiplier 6
The imaginary component of the calculation result is input.

The arc tangent circuit 7 calculates the angle based on the output signal of the multiplier 6 (details will be described later), and the output signal of the arc tangent circuit 7 will be referred to as a delay circuit (described in FIG. 1 as "DELAY"). Notation) 11 and the second adder / subtractor 12. The loop filter 8 is a known / known loop filter in a so-called PLL loop, and its output signal is applied to one input terminal of the first adder / subtractor 9.
A signal from an integrator 13 described later is applied to the other input terminal of the first adder / subtractor 9 with a negative polarity. That is, the first adder / subtractor 9 outputs a signal corresponding to a result obtained by subtracting the output signal of the integrator 13 from the output signal of the loop filter 8.

The output signal of the first adder / subtractor 9 is
The signal is applied to the complex local oscillator 10. The complex local oscillator 10 is a voltage-controlled oscillator having a known / known configuration, and in the embodiment of the present invention, generates two sine-wave signals having a phase difference of 90 degrees. It is configured. That is, the output frequency of the complex local oscillator 10 changes according to the magnitude of the output signal of the first adder / subtractor 9 (details will be described later). In the components described above, in particular, the part including the heterodyne mixer 5, the multiplier 6, the loop filter 8, the first adder / subtractor 9, and the complex local oscillator 10 is a so-called PLL-based phase locked loop.
It constitutes the L phase synchronization unit 101.

On the other hand, the delay circuit 11 applies a predetermined delay to the input signal and outputs the delayed signal. The output is input to the second adder / subtractor 12 with a negative polarity. The second adder / subtractor 12 has two inputs. The output signal of the arc tangent circuit 7 delayed by the delay circuit 11 as described above is input to the second adder / subtracter 12, and the arc tangent circuit not affected by the delay is input. 7, and a difference between the two, that is, a frequency difference corresponding to the phase difference is obtained (details will be described later). The output signal of the second adder / subtractor 12 is
The voltage is applied to the integrator 13. The integrator 13 integrates the frequency error input from the second adder / subtracter 12 by changing its integration time constant according to the S / N ratio of the BPSK signal which is the input signal of the present apparatus. Therefore, the signal of the S / N detector 3 is input as a signal for controlling the time constant. The output signal of the integrator 13 is applied to the first adder / subtractor 9 with a negative polarity, and the beat sound generator 103
(In FIG. 1, denoted as “SIN”) 14.

Thus, in the above-described components, the heterodyne mixer 5, multiplier 6, arc tangent circuit 7, delay circuit 11, second adder / subtractor 12, integrator 1
3. A portion including the first adder / subtractor 9 and the complex local oscillator 10 constitutes the AFC section 102.
The beat sound generator 103 is for generating a beat sound according to the magnitude of the error based on the frequency error signal obtained by the integrator 13, and includes a sine wave signal generator 14 and a sine wave Amplifier 15 for amplifying the output signal of signal generator 14
And a speaker 16.

Next, the operation of the present apparatus having the above configuration will be described. First, a BPSK signal input to the present apparatus, converted from an analog signal to a digital signal by the analog-to-digital converter 1, and from which unnecessary frequency components are removed by the band-pass filter 2, is given by S 1 = As
The signal is input to the signal complex circuit 4 in a state represented by in (ωt + nΦ). Then, the complex signal by the signal complex circuit 4 is obtained as S2 = Ae ^{i (ω t + n Φ),} and is input to the heterodyne mixer 5. On the other hand, if the phase of the output signal of the complex local oscillator 10 is advanced by Δωt from the phase of the BPSK input to the apparatus, the complex local oscillator 10 outputs e ^{i (Δω −ω)} A signal having a phase represented by ^t is output and input to the heterodyne mixer 5.

Then, in the heterodyne mixer 5,
As a result of heterodyne mixing of the two signals Ae ^{i (ω t + n Φ)} and e ^{i ( Δω−ω) t} , the output signal S3 is BP
SK signal and a signal corresponding to a phase difference between the complex local oscillator 10, i.e., specifically, so that the signal represented as ^{S3 = Ae i (Δω + n} Φ) is obtained. In the multiplier 6, as a result of squaring the signal S3, the output signal S4
^{The, S4 = Ae i (2 Δω} + 2 n Φ) = signal represented as ^{Ae 2 i} Δω ^t is obtained, whereas the signal S4 is input to the arctangent circuit 7, is to the loop filter 8, the An imaginary component will be applied. That is, in this case, since it is ^{Ae 2 i Δω t = A (} cos2Δωt + isin2Δωt), as the imaginary component, so that the sin2Δωt is applied to the loop filter 8.

The signal S4 is supplied to the loop filter 8
Is applied to the first adder / subtractor 9 after the unnecessary signal component is removed. If the input from the integrator 13 to the first adder / subtractor 9 is zero, The output of the adder / subtracter 9 of 1 becomes the output signal of the loop filter 8 itself, which is applied to the complex local oscillator 10. Here, assuming that the output signal of the first adder / subtractor 9 is x, this x corresponds to the output frequency of the complex local oscillator 10,
It is an element that gives a frequency difference according to the phase difference with the input signal. That is, when there is a phase difference Δωt between the input signal and the output frequency of the complex local oscillator 10, the output signal of the complex local oscillator 10 is expressed as e ^{i (Δω−ω) t} , Here, Δω is determined as Δω = βx. Here, β is a constant. Then, the PLL phase synchronization unit 1 sets the phase difference to zero (Δωt = 0).
When 01 operates and synchronization is established, the output frequency of the complex local oscillator 10 matches the frequency of the input signal.

On the other hand, in the arc tangent circuit 7,
Is the output signal Ae of the multiplier 6^{i ( Two Δ ω + Two n Φ)}About
Arctangent is calculated. That is, the output signal A
e^{i ( Two Δω + Two n Φ)}Is calculated.
The result is that the BPSK signal, which is the input signal,
It corresponds to the phase difference between the output signals of the local oscillator 10.
Therefore, in the embodiment of the present invention, a double phase difference Δ
ωt is output and applied to the delay circuit 11.
ing. Then, in the second adder / subtractor 12, the
Output signal of arctangent circuit 7 and arctangent
The signal of the circuit 7 is subtracted from the delayed signal.
As a result, the cycle between the input signal and the output signal of the complex local oscillator 10 is
The signal αΔω (where α is a constant) corresponding to the wave number error is calculated.
Will be issued. Where the heterodyne mixer
5. Multiplier 6 and arc tangent circuit 7
Is the part that performs complex operations, so to speak.
The phase error determined by the transient circuit 7 is
Therefore, the second adder / subtractor 12
Corresponding to the frequency error obtained from the difference between the phase errors
Signal αΔω is converted to a real phase error
Unlike the frequency error calculation based on
Indicates whether it is shifted to the higher side or to the lower side.
It has become something.

The signal α from the second adder / subtracter 12
Δω is integrated in the integrator 13 so that the frequency error is averaged. The integration time constant of the integrator 13 is changed in accordance with the S / N ratio calculated by the S / N detector 3. When the S / N is good, the integration time constant is short, and the S / N is small. If it is bad, it is set longer. The output signal of the integrator 13 is applied to the first adder / subtractor 9 and subtracted from the output signal of the loop filter 8 described above, and the output signal x as the operation result is sent to the complex local oscillator 10. Will be applied. Therefore, the frequency deviation between the output signal of the complex local oscillator 10 and the input signal frequency is more accurately and reliably corrected by adding the integrated signal of the frequency error by the integrator 13 to the output signal of the loop filter 8. The Rukoto.

As described above, since the frequency shift is corrected by the AFC unit 102 in addition to the phase lock-in by the PLL phase lock unit 101, the band of the loop filter 8 can be set narrow. That is,
By narrowing the band of the loop filter 8, even if the so-called lock range is narrowed, the frequency lock function of the AFC unit 102 compensates for the narrow lock range of the PLL phase synchronizing unit 101, which is more reliable than in the past. Synchronization is performed. In particular, the control of the integration time constant of the integrator 13 is such that when the S / N is poor, the integration time constant is lengthened and the time required for locking (establishing synchronization) is reduced, while when the S / N is good, the integration time constant is controlled. Is locked so as to be locked earlier, and is locked in an appropriate lock time according to the S / N.

On the other hand, the output signal of the integrator 13 is input to the sine wave signal generator 14 so that the sine wave signal generator 1
From No. 4, a sine wave whose frequency is a predetermined multiple of the frequency error, that is, a sine wave represented by sin (mΔωt) is output. Here, m is a preset constant, and is set to m = 4 in the embodiment of the present invention. Of course, the value of m may be other than 4. The output signal of the sine wave signal generator 14 is amplified to an appropriate level by the amplifier 15 and applied to the speaker 16, so that a beat sound corresponding to the frequency error can be heard. In the state where the input signal is locked (synchronous state) as described above, Δω = 0, so that the beat sound from the speaker 16 disappears. Therefore, the user sets the dial for adjusting the receiving frequency of the wireless receiver or the like to the speaker 1.
By operating so that the beat sound from 6 disappears, the tuning of BPSK by the wireless receiver can be performed very easily and
It can be performed reliably.

In the above-described embodiment, the input signal is described as a BPSK signal.
It need not be limited to this, but other forms of PSK signals,
For example, a similar operation can be obtained with a QPSK signal. In this case, the output of the multiplier 6 is the fourth power of the original QPSK signal. Also, the configuration shown in FIG. 1 can be realized by so-called hardware, and a part excluding the analog / digital converter 1, the amplifier 15, and the speaker 16 can be replaced by a DSP (Digital Signal Processor).
It may be realized by software processing according to r) or any of them.

[0023]

As described above, according to the present invention,
The phase error is obtained by a complex operation, the frequency error is calculated based on the phase error, and the frequency error is integrated to expand the frequency error so as to generate a so-called beat sound of an audible frequency. Irrespective of this, it is possible to easily determine whether or not tuning has been performed based on the presence or absence of a stable beat sound, and it is possible to easily and reliably confirm tuning by tuning the wireless receiver. In particular, by changing the integration time constant in accordance with the S / N ratio, the beat sound can be reliably obtained even when the S / N ratio is low, and the effect of easy tuning can be obtained. To play.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a PSK tuning confirmation device according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 4 ... Signal complexing circuit 5 ... Heterodyne mixer 6 ... Multiplier 7 ... Arc tangent circuit 10 ... Complex local oscillator 11 ... Delay circuit 13 ... Integrator 14 ... Sine wave signal generator 16 ... Speaker

Claims (5)

[Claims] 1. A PSK tuning confirmation method for confirming the tuning of a PSK signal modulated by a radio carrier in a radio receiver, the method comprising: detecting a phase of the PSK signal based on a low-frequency output signal of the radio receiver. An error is obtained by a complex operation, a frequency error is obtained from the phase error, and the frequency error is integrated to generate an audio frequency signal multiplied by a predetermined multiple. A frequency signal is applied to make the electric signal / sound wave converter sound, and it is determined that the PSK signal has been tuned in the wireless receiver when the sound of the electric signal / sound wave converter has disappeared. PSK tuning confirmation method. 2. A complex phase error detecting means for calculating a phase error of an input PSK signal by a complex operation, a frequency error is obtained based on an output signal of the complex phase error detecting means, and the frequency error is determined by a predetermined value. A PSK tuning confirmation device comprising: frequency integration means for integrating with an integration time constant; and beat sound generation means for generating an audible frequency sound according to the frequency of an output signal of the frequency integration means. 3. The complex phase error detecting means receives the input P
A signal complexing circuit for converting the SK signal into a complex number; a complex local oscillator for generating a signal having a frequency corresponding to a phase error of the PSK signal in a complex number form according to a control signal applied from the outside; A heterodyne mixer that performs heterodyne mixing of an output signal of a complex circuit and an output signal of the complex local oscillator; a multiplier that multiplies output signals of the heterodyne mixer; and an imaginary number of an output signal of the multiplier A loop filter to which only the component is applied; and two input terminals. One of the input terminals receives the output signal of the loop filter, and adds and subtracts the two signals applied to the two input terminals. And a first adder / subtracter for outputting the operation result as a control signal of the complex local oscillator, and an arithmetic unit for calculating an arc tangent of the output signal of the multiplier. And a delay circuit for delaying the output signal of the arc tangent circuit; and adding and subtracting the output signal of the arc tangent circuit and the output signal of the delay circuit. A second adder / subtractor; and an integrator for integrating an output signal of the second adder / subtractor with an integration time constant according to an external control signal,
The output signal of the integrator is configured to be applied to the other input terminal of the first adder / subtractor, and the beat sound generating means generates a sine wave signal that generates a sine wave signal having a predetermined multiple of the output frequency of the integrator. The PSK tuning confirmation according to claim 1, comprising: a wave signal generator; an amplifier for amplifying an output signal of the sine wave signal generator; and a speaker connected to an output terminal of the amplifier. apparatus. 4. An S / N for calculating an S / N ratio of an input PSK signal and outputting the calculated S / N ratio to the integrator as a control signal for determining an integration time constant in the integrator.
4. The PSK tuning confirmation device according to claim 3, further comprising a ratio calculating means. 5. An S / N ratio calculating means for converting an analog input PSK signal into a digital signal, and passing only the PSK signal included in the output signal of the analog / digital converter. And the ratio of the power of the output signal of the band-pass filter to the power of the output signal of the analog-to-digital converter is represented by S
The PSK according to claim 4, further comprising: an S / N detector that calculates the ratio as a / N ratio.
Synchronization confirmation device.