JP2002124852A - Storage circuit, semiconductor integrated circuit and design method dealing with delay failure test - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase success rate of path delay test by enhancing the controllability of path delay test thereby making active a path to be tested stably and surely. SOLUTION: A flip-flop having a function for shifting normal input data to output and a function for setting a value to be outputted fixedly and outputting the set values cyclically according to a clock is employed in at least a part of a path of logic circuit formed between an external input and an external output and a desired fixed value is outputted to a gate connected with the path thus activating the path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a storage circuit, a semiconductor integrated circuit, and a delay fault effective for a path delay test relating to a delay fault of a storage circuit (flip-flop) constituting the semiconductor integrated circuit. Related to test-ready design method.

[0002]

2. Description of the Related Art Conventionally, a phenomenon may occur that a manufactured LSI operates correctly in an operation cycle lower than the actual speed, but does not operate at the actual speed. Such a state is referred to as "a delay failure has occurred" in the LSI.
Check that no delay failure has occurred, that is, the manufactured L
In order to guarantee the actual operating speed of SI, a speed test is performed.
You need to check the results. For this purpose, there is a method called a path delay test in which a signal propagation path (path) in a circuit of a semiconductor integrated circuit to be tested is selected and a test is performed on the assumption that a delay fault has occurred.

[0003] The path delay test is performed by setting the test target to LS
This is a test method in which the test is divided into signal propagation paths (paths) in I and a test is performed on each of them assuming a delay fault. To perform an actual operation speed test of a normal LSI, use L
It is necessary to move the entire SI at the actual operating speed, but the path delay test method divides the test target and performs independent tests for each, making it easy to generate tests. There is an advantage that the calculation of the range is easy.

A specific method of performing a path delay test will be described with reference to the drawings. For example, in FIG. 11, the output of the flip-flop 12 changes from the value 0 to the value 1, and the change is determined by the signal line 112, the NAND cell 16, the signal line 113, and the OR.
Flip-flop 1 via cell 17 and signal line 114
Suppose that it is desired to test whether or not the signal propagation path (path) leading to 5 reaches a delay fault in the path, that is, whether or not the time required for propagation is as designed.

In order to carry out this test, first, a value 0 is set to the flip-flop 12, a value 1 is set to the flip-flop 13, and a value 0 is set to the flip-flop 14 using a scan chain function. .

The explanation of the scan chain will be described below. Also, the combinational circuit 11 is operated, and the signal 19 is set to the value 1, 110 to the value 1, and 111 to the value 0. At this time, the signal 112 has a value of 0, the signal 113 has a value of 1, and the signal 114 has a value of 1.
become. Once a pulse is applied to the signal 18, the flip-flops 12, 13, 14, 15 take their respective data inputs and change state, the flip-flop 12 changes from a value 0 to a value 1, the flip-flop 13 changes to a value 1 again, The flip-flop 14 changes to the value 0 again, and the flip-flop 15 takes in the state of the signal 114, the value 1. When the state of the flip-flop 12 changes from the value 0 to the value 1, the signal 112 changes from the value 0 to the value 1, which changes the signal 113 from the value 1 to the value 0, and further changes the signal 114 from the value 1 to the value 1. The change to the value 0 propagates the change in the signal state.

Thereafter, when a pulse is applied to the signal 18 again, the value of the signal line 114 is taken into the flip-flop 15. Signal line 114 captured by flip-flop 15
Of the flip-flop 12 when the clock is turned on.
If the state change has propagated to reach 114, the value is 0; if the change has not yet propagated, the value is again 1; that is, the first pulse application interval and the second pulse application interval for the signal 18; And the propagation delay of the propagation path from the signal 112 to the signal 114 is larger than the flip-flop 15.
Will determine the value captured by

By observing the value taken in by flip-flop 15 after a series of operations, signals 112, 1
It is possible to confirm the propagation delay of the change transmitted through the propagation paths 13 and 114 and the magnitude of the first pulse application and the second pulse application interval for the signal 18. Assuming that the propagation delay in the design specification is t, a test is performed with the first and second pulse intervals for the signal 18 being set to t, and if the value taken in by the flip-flop 15 is 0, the actual propagation delay is If it is 1 or less than t, it can be determined that the actual propagation delay is greater than t. Use the scan chain function to observe the value captured by the flip-flop.

Here, the scan design and the function of the scan chain will be described. Scan design is a design method for controlling and observing the signal state of registers such as flip-flops in a circuit.Registers used in a circuit are used in addition to functions used in a normal system. Design to have a serial shift function that is used only during testing.

The serial shift function of each register is connected to each other to function as a shift register, and the state of the register can be controlled and observed by using the serial shift function of the register during a test. . This special register is called a scan register, and a register that normally functions as a flip-flop is called a scan flip-flop.

FIG. 12 shows a design example of a scan flip-flop generally called a two-phase clock scan flip-flop. This flip-flop has input 84
In the state where (A) and the input 85 (B) are fixed to the value 0, the edge-operating flip-flop which takes in the value of the input 81 (D) at the rising edge of the clock 83 (CP) and propagates it to the output 86 (Q) Works as

When the input 83 (CP) is fixed at a value of 1, the value of the input 82 (SI) is fetched when the input 84 (A) is at the value 1, and the input 85 (B) is set at the value of 1 at the input 85 (B). Sometimes, the value of the output 87 (SO) is updated. When the input 85 (B) has the value 0, the gate 814
Is cut off, and a loop composed of the gates 820, 821, and 815 is formed. As a result, the value of the output 87 (SO) is maintained.

That is, this flip-flop has an input 81
(D) is a data input, an input 83 (CP) is a clock input, an output 86 (Q) is a data output, and operates as a normal edge operation type flip-flop.
(SI) is data input, output 87 (SO) is data output, input 84 (A) is master clock, input 85
(B) is used as a slave clock to operate as a two-phase clock flip-flop.
This flip-flop functions as a scan flip-flop by using the function of an edge operation type flip-flop as a system and by using the function of a two-phase clock type flip-flop as a serial shift register.

[0014]

A problem with the above-described conventional path delay test method is that it is difficult to keep a path to be tested active. For example, in order to accurately test the propagation paths of the signals 112, 113, and 114 in FIG. 11, it is necessary to ensure that a signal change propagates along this path, that is, fix the signal 115 to the value 1 and fix the signal 116 to the value 0. Must. Fixing the signal 115 to the value 1 and the signal 116 to the value 0 means that the data held in the flip-flop 13 is the value 1 and the flip-flop 14
Has to be fixed to the value 0. However, during the test, when a pulse is applied to the signal 18, the data held in the flip-flops 13 and 14 changes by taking in the values of the signals 110 and 111. To set the values of the signals 110 and 111, the combinational circuit 11 must be controlled.
That control is not always possible.

For example, if the circuit 11 in the preceding stage is designed so that the value held by the flip-flop 13 always toggles each time a pulse is input to the clock 18, the value held before and after the pulse is applied to the clock 18. Cannot be fixed to 1. The difficulty in fixing the value held by the flip-flop before and after the application of the pulse to the clock leads to the difficulty in keeping the path to be tested active in the path delay test.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to improve the controllability of a path delay test so that a path to be tested is made active stably and surely. An object of the present invention is to provide a storage circuit, a semiconductor integrated circuit, and a design method for a delay fault test capable of increasing the success rate of a test.

[0017]

In order to achieve the above object, a feature of the present invention is that a set value is inputted to a storage circuit which shifts input data together with application of a clock and outputs it from an output terminal. Input means, holding means for holding a set value input from the input means and outputting it from an output terminal, and output data for inputting data of the output terminal together with application of a clock pulse and causing the holding means to cyclically hold the data. Fixing means.

A feature of the invention of claim 2 is that it has a function of selecting whether data to be taken in when a clock pulse is applied is data held cyclically by the holding means or data input from outside, Which is to be selected can be set by a scan path shift in advance.

According to a third aspect of the present invention, the input means comprises an input terminal and a first gate connected thereto, and the holding means comprises a second gate connected to the first gate, a first inverter, and a second inverter. A first loop circuit including an inverter and a third gate, a second loop circuit including a third inverter, a fourth inverter, and a fifth gate connected to the first loop circuit via a fourth gate; An output terminal connected to a two-loop circuit, wherein the output data fixing means introduces the held value of the second loop circuit into the first loop circuit via a fifth inverter, a multiplexer, and a sixth gate. The input means comprises a seventh gate connected to a first gate of the input means, a sixth inverter, a seventh inverter, and an eighth gate connected to the seventh gate. That it is characterized in that it consists of the third loop circuit and the multiplexer.

A feature of the invention of claim 4 is that of claim 1 or 2
The described storage circuit is used for at least a part of a logic circuit formed between an external input and an external output.

According to a fifth aspect of the present invention, a step of selecting a test target path of a test target circuit including at least one or more storage circuits, and a state to be taken by the circuit to activate the test target path. Analyzing and inserting a test point circuit as needed; calculating a state retention of the test target circuit; selecting a replacement target storage circuit based on the state retention; Replacing the storage circuit with the storage circuit according to the first aspect.

Here, the input terminal is the terminal SI of FIG.
The first gate is connected to the transmission gate 215,
The second gate is connected to the transmission gate 212 and the first gate.
The inverter is the inverter 219, the second inverter is the inverter 220, the third gate is the transmission gate 216, the fourth gate is the transmission gate 213, the third inverter is the inverter 221,
The inverter is the inverter 225, the fifth gate is the transmission gate 214, the fifth inverter is the inverter 223, and the multiplexer is the multiplexer 210.
The sixth gate is connected to the transmission gate 211,
The seventh gate is connected to the transmission gate 217 and the sixth gate.
The inverter corresponds to the inverter 224, the seventh inverter corresponds to the inverter 225, and the eighth gate corresponds to the transmission gate 218.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration according to an embodiment of a storage circuit of the present invention.

In the scan flip-flop of the present invention, 21 (D), 22 (SI), and 23 (C
P), 24 (A), 25 (B), 26 (SU), 27
(ST). As output signals, 28 (Q), 2
9 (SO).

The operation of the flip-flop of this embodiment will be described. First, inputs 24 (A), 25 (B), 26 (S
When U) and 27 (ST) have a fixed value of 0, this flip-flop inputs data from input 21 (D) and inputs data from input 23 (C).
P) operates as a rising edge operation flip-flop having a clock input and an output 28 (Q) as a data output.

Under this input condition, the gate 210 sets the input 2
1, the input from (D) is passed, the gate 216 is fixed in the passing state, and the internal signal 236 (CUN) is input 23.
(CP) is inverted and the internal signal 237 (CU) is input 23
It has the same value as (CP). Under these operating conditions, input 23 (C
When P) has the value 0, the gate 213 blocks the signal propagation from the input 21 (D), and the output 28 becomes the gates 221 and 22.
It is the output of the loop consisting of 2,214.

When the input 23 (CP) changes from 0 to 1, the gate 211 is shut off and the gates 219, 220,
The loop consisting of 216 and 212 is released, and keeps the value transmitted from the input 21 until immediately before. The value is propagated to output 28 (Q) through open gates 213 and 221. When the input 23 (CP) changes from 1 to 0, the gate 213 is shut off, and the value passing through the gate 221 at that time is changed to the gate 221, 222, 2
14 are held.

Subsequently, inputs 24 (A), 25 (B), 26
The operation when (SU) is fixed to the value 0 and 27 (ST) is fixed to the value 1 will be described. Under this input condition, the output of the gate 210 is selected as the output 29 (SO) to selectively pass the input value from the input 21 (D) or the output value of the gate 233.
The gate 216 is in the passing state, the internal signal 236 (CUN) is the inversion of the input 23 (CP), and the internal signal 237 (CU) is in the same state as the input 23 (CP). Output 29 (SO)
Indicates that the input 25 (B) is 0,
4, the data held in the loop of the gate 225 and the gate 218.

Under these operating conditions, the input 23 (CP) has the value 0
In this case, the gate 213 cuts off the data from the input 21 and the output 28 is the output of the loop composed of the gates 221, 222 and 214.

When the input 23 (CP) changes from the value 0 to the value 1, the gate 211 is cut off and the gates 219 and 22 are turned off.
The loop consisting of 0, 216, and 212 keeps holding the signal from the gate 210 immediately before. The signal is output through the opened gate 213 and the gate 221 to output 28 (Q).
Propagated to

When the input 23 (CP) changes from 1 to 0, the gate 213 is shut off, and the data passing through the gate 221 at that time is held in a loop composed of the gates 221, 222 and 214.

Next, the operation when the value of the input 26 (SU) is fixed to 1 will be described. Under this input condition, the gate 213 interrupts the signal value propagation from the gate 219 and the gate 214
Is open, the output 28 (Q) is applied to the gates 221 and 2
The data held by the loop composed of the loops 22 and 214 is continuously output.

Finally, the operation when the input 23 is fixed to the value 1 will be explained. Under this input condition, the flip-flop of the present invention has an input 22 (SI) as a data input, an input 24 (4) as a master clock, an input (B) as a slave clock, and an output 29.
(SO) operates as a two-phase clock flip-flop that outputs data. Since the input 23 (CP) is fixed at 1, the gate 212 is passed and the gate 211 is shut off.

When the input 24 (A) changes from the value 0 to the value 1 under this operating condition, the gate 215 is opened and the gate 21 is opened.
Data from input 22 (SI) is propagated to 2, 217. Subsequently, when the input 24 (A) becomes 0, the gate 215 is shut off, the gate 216 is opened instead, and the gate 21 is turned off.
A loop is formed at 9, 220, 216, and 212 to keep the immediately preceding data.

When the input 25 (B) changes from the value 0 to the value 1, the gate 217 is opened, and the gates 219, 220,
The data held in the loop consisting of 216 and 212 is transferred to gate 2
24, 225 to the output 29 (SO). Subsequently, when the input 25 (B) becomes 0, the gate 217 is shut off,
Instead, the gate 218 is opened and immediately before the gate 22
4 and 225 are transmitted to gates 224 and 22.
5, 218, and output 29 (S
O).

FIG. 2 is a diagram illustrating a design example using the flip-flop of the present invention shown in FIG. 1 and explaining a path delay test method using a special function of the flip-flop. The three (32, 33, 34) flip-flops of the present invention are positioned in a circuit by replacing flip-flops used in normal operation.

In order to maintain the function as a normal operation, the D input, CP input, and Q output of each flip-flop are connected to system logic signals (315, 316, 317, 318, 319, 319).
36). Also, a scan shift path connection (311, 31) connecting the SI input and SC output of each flip-flop so that the scan chain function works.
2, 313, 314) and scan control clock connection (3
7, 38).

Further, flip-flop output control signals (39, 310) which are a feature of the present invention are connected. 36 (CP-EXT), 3
7 (A-EXT), 38 (B-EXT), 39 (SU-
EXT), 310 (ST-EXT), 311 (SI-E)
XT) and 312 (SO-EXT). Of these, only 312 (SO-EXT) is an output terminal and the others are input terminals.

Here, in the circuit of FIG. 2, the output of the flip-flop 32 changes from 0 to 1 according to the change of the clock 36, and the change is indicated by the signal 317, the AND cell 35, the signal 3
A delay time until the signal reaches the flip-flop 34 via the line 19 is set as a test target. FIGS. 3 to 6 show test input signals and signal waveforms of output observation performed at each terminal in order to execute a series of tests.

As a test procedure, first, a signal waveform shown in FIG. 3 is input. In the test cycles 41 to 43,
The flip-flop is operated as a shift register by alternately applying pulses to the scan master / slave clocks 37 and 38 of the flip-flop with the clock 36 (CP-EXT) of the flip-flop fixed at a value of 1. The input value of the shift data input 310 (SI-EXT) is changed so that the flip-flop 32 has the value 0, the flip-flop 33 has the value 1 and the flip-flop 34 has the value 1 as a result of the shift.

The reason why the value 0 is set in the flip-flop 32 is that this flip-flop is the starting point of the path to be tested, and the change to be tested is to test the change from the value 0 to the value 1. . The value 1 is set in the flip-flop 33 because the output of the flip-flop 33 is one of the inputs of the AND gate 35 in the path to be tested. It is necessary to make it.

The reason for setting the value 1 to the flip-flop 34 is to change the state of the flip-flop 32 from the value 0 to the value 1 by applying a pulse to the clock 36. Since the input signal 315 of the flip-flop 32 is supplied from the flip-flop 34, by setting the value of the flip-flop 34 to 1, a desired change can be made by applying a pulse to the clock.

In the test cycle 44, the signal 39 (SU-EXT) connected to the input 26 (SU) of each flip-flop 32, 33, 34 is changed from the value 0 to the value 1. This operation has a role of holding and fixing the value set in each flip-flop by the shift input from 41 to 43 in a loop including the gates 221, 222 and 214 in the flip-flop.

FIG. 4 shows a test cycle following FIG.
The test cycles 51 to 53 are also scan shift cycles. However, since the shift is performed while the input signal 39 (SU-EXT), that is, the flip-flop 26 (SU) is held at 1, the shift is performed in this test cycle. Data is not propagated to the output 28 (Q) of each flip-flop 32, 33, 34. As a result of the shift, a value of 0 is stored in the flip-flop 32, a value of 1 is stored in the flip-flop 33, and a value of 0 is stored in the flip-flop 34 in a loop composed of the gates 224, 225, and 218 in each flip-flop.

The shifted data has a role of selecting data to be taken into the flip-flop when a pulse is applied to the system clock 36. When a pulse is applied to the clock input 23 of the flip-flop (that is, 36 inputs of the circuit), the flip-flop having shifted the value 0 takes in the data of the external input 21. The same data (output of the gate 223) is fetched again.

The value 1 is shifted to the flip-flop 33,
Since it is held, even if a pulse is applied to the clock 23, its own output is taken again and the output does not change. This signal has a role of fixing one input of the AND gate 35 under test to a value of 1 and the signal 3 of the test target path.
It is set for the purpose of ensuring signal propagation from 17 to the output 319.

In the test cycle 54, after the input signal 36 (CP-EXT) in the circuit connected to the clock input 23 (CP) of the flip-flops 32 and 33 is changed to a value of 0, the input 26 of the flip-flops 32 and 33 ( The input signal 39 (SU-EXT) in the circuit connected to SU) is changed to 0.

When the clock input of the flip-flops 32 and 33 is changed from the value 1 to the value 0, the loop composed of the gates 219, 220, 216 and 212 in the flip-flop is cut off, but the gates 221 and 221 in the flip-flop are cut off.
The loop consisting of 222, 214 continues to hold data. Thereafter, the flip-flop input 26 (SU) is set to the value 1
From 0 to value 0, 23 instead of 26 (SU)
Since the value of (CP) forces the gate 213 to shut off and the gate 214 to open, the gates 221, 222, 21
4 does not change.

FIG. 5 shows a test cycle subsequent to FIG. 4, in which a path delay test is actually performed. At timing 61, a pulse is applied once to the clock input 36 to the flip-flops 32 and 33. Then, the flip-flop 32, which holds the value 0, takes in the data of the signal 315 and changes to the value 1. This gives signal 3
17 changes from the value 0 to the value 1, and the signal 3
19. Propagation to the input of the flip-flop 34.
The clock input 36 is changed from a value 0 to a value 1 at a timing 62 after a certain time from 61.

The flip-flop 34 first takes in the value 0 at the rising edge of the clock at the timing 61. Then, at the time of the rising edge of the clock at the timing 62, the state of the input signal of the flip-flop 34 at that time is captured. By the time when the change of the flip-flop 32 generated at the timing 61 is 62, the flip-flop 3
If it has been transmitted to the input of 4, the value 1 is taken in.
If the propagation of the change has not yet arrived, the value 0 is fetched again.

That is, the interval between 61 and 62 is allowed from the flip-flop 32 permitted by the design specification from the flip-flop 34 via the signal 317, the gate 35, and the signal 319.
If the path is set to the maximum propagation delay time, the value 1 is stored in the flip-flop 34 if the path is in accordance with the design specification, and the value 0 is stored if the path has a delay fault. The result can be used to find a delay fault.

FIG. 6 is a test cycle subsequent to FIG. 5, and has the meaning of observing test results. First, in a cycle 71, at timing 62, the gates 219, 2
The values captured in the loop of 20, 216, 212 are propagated to the loop of gates 224, 225, 218. Thereafter, by applying pulses alternately to the scan shift clocks 37 and 38, the data held in each flip-flop is shifted out and observed. The state observed at the output 314 (SO-EXT) at the timing 75 is the flip-flop 3
The value is 4. Based on whether this is 0 or 1, the quality of the test result can be determined.

According to this embodiment, in addition to the function of shifting normal input data to the output, it is possible to set a value to be fixedly output and to output the set value cyclically according to a clock. A flip-flop as shown in FIG. 2 is created, and this flip-flop is used, for example, in FIG.
By configuring a circuit as described above, a desired fixed value for activating the test path is output to a gate in the middle of the test path to make the test path active easily and stably, which has conventionally been quite difficult. Thus, it is possible to easily automate the generation of the in-circuit pulse delay test, increase the test accuracy, and increase the success rate of the path delay test.

Next, a conventional test 2 shown in FIG.
In the scan design using the phase scan flip-flop, a method for obtaining the maximum effect with a minimum increase in circuit scale by selectively using the flip-flop of the present invention shown in FIG. 1 will be described.

FIG. 7 is a flowchart showing a processing procedure according to an embodiment of the design method for delay fault test of the present invention, and showing an example of a flip-flop replacement process. Hereinafter, the operation of the present example will be described based on the flowchart of FIG. It is assumed that the circuit is already scan-combined and incorporates a scan path. The purpose of this system is to measure the efficiency of path delay test generation in a circuit by making minimal modifications to the current circuit.

First, in step 91, a path to be subjected to a delay test is selected from the paths in the circuit. Subsequently, in step 92, the internal signal state necessary for activating the path to be tested is analyzed, and the input terminal state and the flip-flop state required for making the state are analyzed. If the path can be activated only by controlling the state of the input terminal and the flip-flop, the process proceeds to step 94.
Move to However, if there is a signal in the circuit that cannot be controlled only by the input terminal or the flip-flop, and thus the activation of the path cannot be guaranteed, a test point circuit is inserted (step 93) and the analysis is performed again.

In step 94, it is analyzed whether or not the state of the flip-flop necessary to activate the path can be maintained even if a pulse is input to the clock of the flip-flop. The flip-flop having poor controllability of the state retention is determined to be a target of the state retention improvement (step 95), and is replaced with a flip-flop of the present invention having a high state retention as shown in FIG.

Next, an example will be described in which a circuit delay is actually improved using the flow of FIG. FIG. 8 shows a circuit example edited in this example. In this circuit, the flip-flops 102 to 107
In the conventional two-phase clock type scan flip-flop shown in FIG. 1, their CP, SI, A, and B inputs are actually connected to external terminals, respectively, though not shown in the figure, and each of the SI, It is assumed that the input and the SO output are connected in series to complete the connection as a scan chain.

First, in step 91, in the circuit as shown in FIG.
13, it is assumed that a pulse that reaches the flip-flop 107 via the AND gate 1010, the signal 1014, the OR gate 1011, the signal 1015, the AND gate 1012, and the signal 1016 is selected as a target of the delay test.

Subsequently, in step 92, the state which the circuit should take to activate the path to be tested is analyzed. First, to activate the path under test,
It is possible to determine from the logic of the path that it is necessary to fix the signal 1017 to 1, 1021 to 0, and 1022 to 1.
These signals are as follows: 1017 is from black box 101, 1021 and 1022 are flip-flops 105, 1
06. That is, the path to be tested cannot be reliably activated only by the flip-flop and the input terminal.

Then, the process proceeds to a step 93, wherein the improvement of the situation is measured by inserting a test point circuit as shown in FIG. Of the signals that must be controllable to activate the path, only signal 1017 is the flip-flop 10
Since control cannot be performed directly from the input terminals 2 to 106 and the input terminal, the controllability therefor is improved by inserting a test point circuit.

More specifically, an OR gate 1A1 having a signal 1017 as one input is inserted into the circuit, and the OR gate 1A1
7 is replaced with the output 1A3 of the OR gate. The other input of the OR gate 1A1 is connected to an input terminal 1A2 which is fixed to 1 during the test to ensure controllability.

Returning to step 92, the controllability for activating the path is confirmed. It is confirmed that the path can be activated only by controlling the flip-flop and the input terminal.

In step 94, the state retention of the flip-flop is calculated. In order to hold the signal 1021 at 0, the flip-flop 105 must be held at 0. Even if a clock is once applied to the flip-flop, it is checked whether the same state can be held. The data input of flip-flop 105 is flip-flop 1
This is the NAND calculation result of the outputs 02 and 103. Since the flip-flops 102 and 103 do not directly affect the controllability for activating the test target path, the values can be freely set. Therefore, the flip-flops 102 and 1
By setting both states of 03 to 1, the flip-flop 105 is in the state of 0 even if clocked once.
It can be seen that can be maintained.

Subsequently, in order to hold the signal 1022 at 1, the flip-flop 106 must be held at 1. When it is confirmed that the same state can be maintained even when a clock is input to the flip-flop 106, the data input of the flip-flop 106 is configured to invert the output of the flip-flop 106 itself. In order for the state of the flip-flop 106 to become 1 after the clock is input, the flip-flop 106
It must set itself to a state of zero. However, since the flip-flop 106 itself must be set to 1 before the clock is turned on, the condition cannot be satisfied. For this reason, it is determined that the flip-flop 106 has poor 1-state retention.

In step 95, the flip-flop 106 having poor retention of 1 is selected as a target for improving retention. In step 96, the flip-flop 106 is replaced with the retention-improving flip-flop of the present invention as shown in FIG. Figure 1 shows the result of replacement.
0 is shown. Through a series of these operations, the controllability of the path delay test of the test target path is improved, and a reliable path delay test can be performed.

According to the present embodiment, only the minimum necessary flip-flops of the conventional flip-flops in the current circuit are replaced with the flip-flops of the present invention shown in FIG. The controllability of the delay test can be efficiently improved.

It should be noted that the present invention is not limited to the above-described embodiment, and can be embodied in other various forms in a specific configuration, function, operation, and effect without departing from the gist thereof. .

[0069]

As described above in detail, according to the first to fourth aspects of the present invention, a path delay test can be performed by using a flip-flop capable of outputting a desired set value stably and fixedly. , The path to be tested can be reliably activated, and the success rate of the path delay test can be increased.

According to the fifth aspect of the present invention, the controllability of the path delay test of the semiconductor integrated circuit can be efficiently improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit example according to an embodiment of a storage circuit (flip-flop) of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example according to a first embodiment of the semiconductor integrated circuit of the present invention configured using the flip-flop illustrated in FIG. 1;

FIG. 3 is a diagram showing an example of input signal and output signal waveforms for executing a test in the circuit of FIG. 2;

FIG. 4 is a diagram showing an example of input signal and output signal waveforms for executing a test in the circuit of FIG. 2;

FIG. 5 is a diagram showing an example of input signal and output signal waveforms for executing a test in the circuit of FIG. 2;

FIG. 6 is a diagram showing an example of input signal and output signal waveforms for executing a test in the circuit of FIG. 2;

FIG. 7 is a flowchart showing a processing procedure according to an embodiment of the design method for delay fault test of the present invention.

8 is a circuit diagram showing an example of a circuit to be subjected to the processing procedure shown in FIG. 7;

FIG. 9 is a circuit diagram showing a circuit example in which a test point circuit is inserted according to the processing procedure shown in FIG. 7;

FIG. 10 is a circuit diagram showing an example of a circuit in which flip-flops are replaced by the processing procedure shown in FIG. 7;

FIG. 11 is a circuit diagram for explaining a specific method of performing a conventional path delay test.

FIG. 12 is a circuit diagram showing a configuration example of a conventional two-phase clock scan flip-flop.

[Explanation of symbols]

21 to 27, 36 to 311, 81 to 85 Input signal line 28, 29, 86 to 87, 314 Output signal line 31 Combination circuit unit 32 to 34 Flip flop 35, 232, 1010, 1012 AND gate 101 Black box 102 to 107 Two-phase clock scan flip-flop 108 NAND gate 210 Multiplexer 211-218 Transmission gate 219-230, 816-824 Inverting gate 231, 1011, 1A1 OR gate 233-235, 312-313, 315-319, 8
25 to 827, 1013 to 1022, 1A2 to 1A3,
1B2 to 1B3 signal line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/822 H01L 27/04 TF term (Reference) 2G032 AA07 AC10 AD06 AE07 AG01 AG07 AH04 AK11 AK16 5B048 AA19 AA20 CC18 EE02 5F038 DT04 DT06 DT15 EZ20 5J043 AA09 AA25 HH01 HH04 JJ04 JJ07 JJ08 KK01 5L106 DD00 DD08 GG03 GG07

Claims (5)

[Claims] 1. A storage circuit for shifting input data together with application of a clock and outputting the shifted data from an output terminal, an input means for inputting a set value, and holding the set value input from the input means and outputting the set value from an output terminal. A storage circuit comprising: a holding unit; and an output data fixing unit that inputs data of the output terminal together with application of a clock pulse and causes the holding unit to cyclically hold the data. 2. A function to select whether data to be taken in at the time of applying a clock pulse is data held cyclically by the holding means or data input from the outside is provided. 2. The storage circuit according to claim 1, wherein the setting can be made by the following scan path shift. 3. The input means includes an input terminal and a first gate connected thereto, and the holding means includes a second gate, a first inverter, a second inverter, and a third inverter connected to the first gate. A first loop circuit composed of a gate, a second loop circuit composed of a third inverter, a fourth inverter and a fifth gate connected to the first loop circuit via a fourth gate;
An output terminal connected to a loop circuit, wherein the output data fixing means introduces the held value of the second loop circuit into the first loop circuit via a fifth inverter, a multiplexer, and a sixth gate. And a third loop circuit including a seventh gate connected to the first gate of the input means, a sixth inverter, a seventh inverter, and an eighth gate connected to the seventh gate; 3. The storage circuit according to claim 1, comprising the multiplexer. 4. A semiconductor integrated circuit, wherein the storage circuit according to claim 1 is used for at least a part of a logic circuit formed between an external input and an external output. 5. A step of selecting a test target path of a test target circuit including at least one or more storage circuits; analyzing a state to be taken by the circuit to activate the test target path; 2. The step of inserting a test point circuit, the step of calculating the state retention of the test target circuit, the step of selecting a replacement target storage circuit based on the state retention, and the step of selecting the replacement target storage circuit. Replacing the storage circuit with a storage circuit according to the above.