JP2002124675A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid electric field concentration on a P-type region beneath an N-type source region of a DTMOS FET and more stably hold the drain-source backward withstand voltage to reduce the on-resistance. SOLUTION: An NPN-pillar layer composed on a P-pillar layer 3 and an N-pillar layer 4 in the vertical direction is formed on unit MOS FET regions surrounded by trench type element isolation region 5, the P-pillar layer 3 located at the center of the NPN-pillar layer has a gentle gradient of an impurity concentration distribution from the top surface in the depth wise direction, and the gradient of this distribution reduces to nearly zero at a depth of 4.0 μm from the surface, resulting in an approximately constant concentration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a MOS FET structure in which an N-type region and a P-type region formed in a unit element region in a vertical direction are horizontally adjacent to each other. The present invention relates to a structure of a semiconductor device and a method of manufacturing the same, and is used for a power switching element requiring low on-resistance and high withstand voltage.

[0002]

2. Description of the Related Art A power switching element using a MOS FET is required to have a low on-resistance and a high withstand voltage. However, in a conventional power MOS FET having a planar structure, if the on-resistance is reduced, the withstand voltage is also reduced, and the withstand voltage is increased. Then, there is a contradictory relationship that the on-resistance increases.

That is, a power MOS FET having a planar structure as shown in FIG. 5 is formed on an N-epi layer 62 having a relatively low impurity concentration formed on an N + substrate 61 having a relatively high impurity concentration.
A MOS structure is formed, and a current path from the back surface of the substrate to the MOS FET via the N-epi layer 62 is taken.

For this reason, the resistance (ON resistance) of the MOS FET during the ON operation depends on the thickness of the N-epi layer 62. Since the depletion layer extends in the N-epi layer 62, the breakdown voltage is maintained in the N-epi layer.
Determined by 62 thickness. As described above, since the current path and the region for maintaining the breakdown voltage are the same, the N-epi layer is formed in order to increase the breakdown voltage.
Increasing the thickness of 62 increases the on-resistance and conversely, N-
Reducing the on-resistance by reducing the thickness of the epi layer 62 has a contradictory relationship that the withstand voltage also decreases, and it has been difficult to satisfy both.

The above-mentioned conventional power MOS having a planar structure
To eliminate the conflicting relationship between low on-resistance and high withstand voltage in FET, and to achieve low on-resistance and high withstand voltage, for example,
Coolmos-a new milestone in high voltage Power MOS
"By L. Lorenz, G. Deboy (1), Super Jun
MOS FET with a ction (super junction) structure (Cool MOS; Sie
mens registered trademark) has been proposed.

[0006] The power MOS FET of this super junction structure is shown in FIG.
As shown in the figure, the N pillar region is a current path
71 and P to maintain reverse breakdown voltage between drain and source
The pillar layers 72 are formed in the vertical direction, respectively.

With this structure, the on-resistance is reduced by the N pillar layer 71.
The breakdown voltage depends on the concentration and width of the N pillar layer 71 and the P pillar layer 72 because the depletion layer extends in the lateral direction.
As a result, the power MO of the conventional planar structure shown in FIG.
SFET has the same reverse breakdown voltage between drain and source (for example, 600 V) and on-resistance of about 1/3 to about
It can be reduced to 1/4.

[0008]

However, the manufacturing process of the MOS FET disclosed in Document 1 is complicated because it is necessary to repeat the epitaxial growth, patterning and ion implantation of silicon a plurality of times. Such a very long process requires cost and time, greatly increases the manufacturing cost, and has little merit in the cost of the semiconductor chip.

In order to improve this point, the applicant of the present application has proposed a highly productive deep trench MO capable of manufacturing a power MOS FET satisfying both low on-resistance and high breakdown voltage at low cost.
The structure of S (Deep Trench MOS; DTMOS) and its manufacturing method were proposed.

The DTMOS structure has a low on-resistance characteristic comparable to that of a super junction structure by a relatively short manufacturing process (deep trench formation, simultaneous ion implantation and thermal diffusion of B and As, formation of an insulator isolation region, flattening). , A MOS FET with a medium to high withstand voltage of 200 V or more can be realized, drastically reducing the number of processes and halving the manufacturing cost.

Here, the basic structure of the DTMOS FET according to the above proposal and a method of manufacturing the same will be briefly described.

FIG. 7 is a sectional view showing a part of the basic structure of a DTMOS FET currently proposed.

Each unit element (cell) of the DTMOS FET is
Boron (B) Arsenic (A) is formed on both sides (both sides) of a P + pillar layer 83 having a width of 10 μm and formed in the vertical direction by diffusion and having a rectangular cross section.
s) An NPN pillar layer having a strip-shaped N + pillar layer 84 having a width of about 2.5 μm and formed in the vertical direction by diffusion is present.
Then, a trench surrounds the NPN pillar layer.
Are provided, and an insulator 85 is embedded therein.

(As-B) in the two N + pillar layers 84
The total amount and the (B−As) total amount in the P + pillar layer 83 are:
They are set equally with a difference within ± 5%. This highly accurate control of the amount of impurities can be achieved by implanting As and B ions into the trench side walls.

A P + base (b) is formed on the P + pillar layer 83.
ase) region 87 is formed, and an N + source (S
channel region (the surface region of the P region sandwiched between the N + source region 86 and the N + pillar layer 84)
A gate electrode 89 is formed thereon via a gate oxide film 88, and through an opening of an interlayer insulating film formed thereover.
Source metal wiring to contact N + source region 86
90 are formed. Thus, a power MOSFET structure in which the N + substrate 80 is used as a drain and the N + pillar layer 84 is used as a current path is realized.

FIG. 8 is a perspective view showing a plane pattern and a part of a cross-sectional structure of a stripe pattern type DTMOSFET as an example of the DTMOS FET shown in FIG.

In this structure, the NPN pillar layer and the trench of each unit element are arranged in a plane stripe pattern.

FIG. 9 is a perspective view showing a part of a plane pattern and a sectional structure of an offset mesh type DTMOS FET as another example of the DTMOS FET shown in FIG.

In this structure, in order to increase the channel density of the DTMOS, NPN pillar layers of each unit element are arranged in a plane offset mesh.

FIG. 10 shows the DTMOS FE shown in FIGS.
It is sectional drawing which shows an example of the structure of the DTMOSFET which concerns on the example of improvement of the structure of the N + pillar layer of T.

In the structure shown in FIGS. 7 to 9, the depletion layer spreads on the surface of the N + pillar layer 84 when a voltage is applied, so that the structure is easily affected by surface charges. And electric field concentration occurs at that portion, which may lead to breakdown.

On the other hand, in the structure shown in FIG. 10, the N + pillar layer 84 has N +
The formation of the region 84a prevents the depletion layer from reaching the surface of the N + pillar layer 84 when a voltage is applied. In this case, the N + region 84a can be formed at the same time when the N source region is formed, so that the number of steps is not increased.

FIG. 11 is a sectional view showing an example of the structure of a DTMOS FET according to an improved example of the structure of the insulator 85 inside the trench shown in FIGS. 7 to 9.

In the structure shown in FIGS. 7 to 9, the inside of the trench is filled with an insulator 85. However, in order to completely fill the inside of the trench with an insulator 85 such as an oxide film (SiO ₂ film), Need a long time. In the thermal process after the embedding, the silicon of the N + pillar layer 84 and the P +
_A large thermal stress is applied to silicon at the bottom of the trench due to a difference in thermal expansion coefficient between the insulators 85 such as the _two films, and crystal defects are intensively generated at that portion, which may increase the leak current.

On the other hand, in the structure shown in FIG. 11, an insulating film 85a is formed on the side surface of the trench, and then the inside of the trench is filled with polysilicon (Poly Si) 85b. Since the polysilicon 85b inside the trench is not a current path and does not need to be completely buried, it can be formed (buried) at a high growth rate (short time).

Since the silicon of the N + pillar layer 84 and the P + pillar layer 83 and the polysilicon 85b inside the trench have the same thermal expansion coefficient, even if a thermal process is performed after the polysilicon 85b is buried, a large thermal stress is applied to the silicon at the bottom of the trench. Will not join. Therefore, it is possible to prevent a crystal defect from occurring in that portion and an increase in leak current.

FIG. 12 shows a part of a cross-sectional structure of the DTMOS FET for schematically explaining a part of a manufacturing process of the DTMOS FET shown in FIG.

First, the N-epi layer 81 formed on the N + substrate 80
A trench 82 reaching the N + substrate 80 from the surface of the substrate is formed by reactive ion etching (RIE). At this time, the portion other than the trench on the surface of the N-epi layer 81 is covered with the oxide film 91.

Next, As and B ions are implanted into the trench side walls at an implantation angle of about 7 ° by, for example, a rotary ion implantation method. Next, by heat diffusion at 1150 ° C for 24 hours or more,
Simultaneous diffusion of As and B is performed.

At this time, since the diffusion coefficient of B 2 is sufficiently larger than the diffusion coefficient of As, As diffuses about 2.5 μm from the side wall of the trench to become the N + pillar layer 84, and B diffuses about 7.5 μm. Together with the diffusion from both sides
+ The pillar layer 83 is formed. That is, the structure after the heat treatment
The NPN pillar layer in which the N + pillar layer 84 exists on the side wall of the trench with the + pillar layer 83 interposed therebetween is completed.

Next, an oxide film is formed on the side surfaces of the trench by thermal oxidation.
(SiO ₂ film), and furthermore, a chemical vapor deposition (Chemical Vapo
An SiO ₂ film or a SiN film is formed by an r Deposition (CVD) method. At this time, in order to realize the structure of the insulator as shown in FIG. 11, an insulating film, for example, an oxide film (SiO ₂ film) 85a is formed on the side surface of the trench, and then the inside of the trench is back-filled with polysilicon 85b. You may do so. At this time, since the polysilicon 85b inside the trench is grown from both sides of the trench, it can be buried in a short time.

Next, the substrate surface is flattened by chemical mechanical polishing (CMP). Subsequent processes are MO with planar structure
Performed in the same manner as the SFET manufacturing process, and as shown in FIG.
A P + base region is formed on the P + pillar layer 83, and a gate oxide is formed on the N + source region and a channel region (the surface of the P region sandwiched between the N + source region and the N + pillar layer) on the P + base region. By forming a gate electrode through the film,
A power MOS FET structure using the N + substrate 80 as a drain and the N + pillar layer 84 as a current path is realized.

In the above manufacturing method, the process from forming the P + pillar layer 83 and the N + pillar layer 84 to flattening the surface is performed by N-
1 epitaxial growth, 1 trench filling,
Low implantation of B and As ions.

By the way, in the structure shown in FIG.
In order to secure the threshold voltage Vth of T, when forming the P + base region 87 on the upper surface of the P + pillar layer 83, B ions are implanted so as to have a higher concentration than the P + pillar layer 83, and thermal diffusion is not performed. Not be.

Therefore, the boundary between the P + base region 87 having a high impurity concentration and the P + pillar layer 83 has a problem that the concentration gradient becomes steep, electric field concentration easily occurs under the P + base region 87, and the breakdown voltage is disadvantageous. is there.

As described above, the power MOS FET having the super junction structure proposed at present has a problem that the electric field is concentrated in the base region below the source region, which is disadvantageous for the reverse breakdown voltage between the drain and the source. .

The present invention has been made in order to solve the above-mentioned problems, and prevents electric field concentration in a base region below a source region, stably secures a higher reverse breakdown voltage between a drain and a source, and reduces on-resistance. It is an object of the present invention to provide a semiconductor device capable of realizing a low MOS FET and a method for manufacturing the same.

[0038]

According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor substrate having a low-resistance epilayer, a depth extending from a surface of the low-resistance epilayer to the semiconductor substrate, and A trench having a wide opening, a rounded tapered surface formed at the periphery of the opening, and a first conductivity type impurity and a second conductivity type impurity ion-implanted from the side wall of the trench into the low resistance epi layer. Second conductivity type pillar layers formed by thermal diffusion and formed in the vertical direction along opposing sidewall surfaces of adjacent trenches, and first conductivity type pillars formed in the vertical direction adjacent to and sandwiched therebetween. A second conductive type source region selectively formed on a surface of the first conductive type pillar layer; a second conductive type source region selectively formed on a surface of the first conductive type pillar layer; Second
A gate electrode formed on a channel region between the conductive type pillar layer and a gate insulating film, wherein the first conductive type pillar layer is used as a base, and the second conductive type pillar layer is used as a current path. A MOS FE having the semiconductor substrate as a drain.
T is formed, and the gradient of the concentration distribution becomes nearly zero at a depth of 4.0 μm or more from the surface of the first conductivity type pillar layer, and the concentration is almost constant.

In the second semiconductor device of the present invention, a vertical pillar layer is formed adjacent to a unit MOS FET region surrounded by a trench type element isolation region,
The first conductivity type pillar layer located at the center of the pillar layer has a gentle gradient of the impurity concentration distribution from the upper surface in the depth direction, and the gradient of the concentration distribution at a depth of 4.0 μm or more from the surface. Is near zero and has a substantially constant concentration.

In a first method of manufacturing a semiconductor device according to the present invention, a semiconductor substrate having a low-resistance epi layer has a depth from the surface of the low-resistance epi layer to the semiconductor substrate, and the opening portion is smaller than the bottom surface. Forming a trench having a wide, tapered surface with a rounded edge at the periphery of the opening, and performing thermal diffusion by ion-implanting a first conductivity type impurity and a second conductivity type impurity into sidewalls of the trench. , The first conductivity type impurity and the second
The second conductivity type pillar layer vertically extending along the trench side wall surface and the impurity concentration distribution in the depth direction from the surface are predetermined from the surface by utilizing the difference in the diffusion coefficient of the conductivity type impurity from the surface. Forming a first-conductivity-type pillar layer that gradually changes to a depth position, flattening a surface after burying an insulator in the trench, and an upper surface of the first-conductivity-type pillar layer Forming a second conductivity type source region selectively, and forming a gate electrode via a gate insulating film on a channel region between the second conductivity type source region and the second conductivity type region. And forming a MOS FET having the semiconductor substrate as a drain and the second conductivity type pillar layer as a current path between the drain and the second conductivity type source region.

[0041]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a part of a sectional structure of a DTMOS FET according to a first embodiment of the present invention.

This DTMOS FET is formed on a Si wafer and separated into chips. In the N-epi layer formed on N ++ substrate 1, boron (B) diffused width 10μ
arsenic (A) on both sides (both sides) of P + pillar layer 3
s) diffused N + pillar layer 4 with a width of about 2.5 μm
The NPN pillar layer (having a width of about 15 μm) in which exists is repeatedly present in the left-right direction. In this case, the depth surrounding the NPN pillar layer and reaching the inside of the N ++ substrate 1 from the surface of the N-epi layer (50 μm)
m or more) with a width of about 8 μm.
By embedding the insulator layer 5 therein, a large number of unit elements (cells) separated from each other are formed. In this case, the trench has a depth extending from the surface of the N-epi layer to the N ++ substrate 1, has a wider opening than the bottom surface,
A rounded tapered surface is formed at the periphery of the opening.

In the above-mentioned NPN pillar layer, the difference between the total amount of (As-B) in the two N + pillar layers 4 and the total amount of (B-As) in the P + pillar layer 3 is within ± 5%. They are set equal. In other words, the P + pillar layer 3 and the N + pillar layer 4 have almost the same concentration, and such high-precision control of the impurity amount is as follows.
This can be achieved by ion implantation of B and As into the trench side wall. The distribution of the impurity concentration in the depth direction from the surface of the P + pillar layer 3 is set and controlled as described later.

Then, the surface of the P + pillar layer 3 is selectively
An N + source region 6 is formed.
Gate insulating film on the channel region between
7, a gate electrode 8 is formed, and a source metal wiring 10 is formed so as to contact the N + source region 6 through an opening of an interlayer insulating film formed thereon. As a result, an NMOS transistor using the N + pillar layer 4 as a current path between the N + source region 6 and the N ++ substrate (drain region) 1
ET is configured.

Note that a portion having a high impurity concentration near the upper surface of the P + pillar layer 3 can be used as a base region. However, in order to secure a desired threshold voltage Vth, a portion near the upper surface of the P + pillar layer 3 is required. Even when the P + base region 8 is formed as shown by the middle dotted line, as in the above, the impurity concentration distribution has a gentle gradient in the depth direction even near the boundary between the P + base region 8 and the P + pillar layer 3. Can be made.

In addition, as shown in FIG. 11, a dielectric film (for example, Si ₃ After N ₄ or SiO ₂ ) is formed, an insulator (polysilicon or SiO ₂ ) may be embedded. Gate insulating film 7
In order to maintain the strength of the substrate, a thermal oxide film (SiO ₂ ) is used. The gate electrode 8 is made of polysilicon or metal silicide.

Also, as shown in FIG.
By forming an N + region in a part of the surface of the N-type pillar 14 that is continuous with the trench side wall, the depletion layer may not reach the surface of the N + pillar layer 14 when a voltage is applied.

Further, the DT having the cross-sectional structure as described above
The planar pattern of the MOS FET may be a stripe pattern as shown in FIG. 8 or an offset mesh type pattern as shown in FIG.

FIG. 2 shows an example of the impurity concentration distribution in a vertical section (BB 'line) in the P + pillar layer 3 of the DTMOS FET shown in FIG.

In this example, the distribution of the impurity concentration from the upper surface to the depth direction of the P + pillar layer 3 located at the center of the NPN pillar layer of each unit element starts from the portion where the surface concentration is high (base region). The concentration decreases while having a gentle gradient in the depth direction, and at a depth of about 4.0 μm or more from the surface (a position deeper than the base region), the gradient of the concentration distribution becomes almost zero and becomes almost constant. Has become.

FIG. 3 shows the depth position (P base depth) where the gradient of the concentration distribution on the upper surface of the P + pillar layer 3 of the DTMOS FET shown in FIG. 7 is a graph showing an example of a result of verifying a reverse breakdown voltage between a drain and a source by simulation.

From these results, it can be seen that if the present invention is applied to a 400 V DTMOS FET capable of obtaining a withstand voltage of 400 V when the P base depth is 3.5 μm and the P base depth is set to about 4.0 μm or more, Is increased to 408 V or more (2% or more), and if the P base depth is increased to about 4.5 μm or more, the withstand voltage becomes 413 V or more (3% or more).
% Or more). 600 V DTMOS FE
It can be easily inferred that the same effect can be obtained by applying the present invention to T.

That is, according to the structure of the DTMOS FET of the above embodiment, the on-resistance can be greatly reduced as compared with the conventional planar type MOS FET as in the case of the proposal described above with reference to FIG. . Further, the vicinity of the upper surface of the P + pillar layer 3 is used as a base region with a high impurity concentration, so that a desired threshold voltage Vth can be secured, and the impurity concentration is high from the upper surface to a predetermined depth. Since the distribution has a gentle gradient, the electric field concentration under the source region can be reduced. As a result, a higher reverse breakdown voltage between the drain and the source can be realized.

In the above description, the N-type DTMOS FET has been described. However, the present invention can be similarly applied to a P-type DTMOS FET.

FIGS. 4A to 4D show the DT shown in FIG.
As an example of the manufacturing process of a MOS FET, a half of a unit element (cell) is taken out and a cross-sectional structure is shown.

That is, first, as shown in FIG. 4A, a low resistance epi layer (N-epi layer) is formed on a semiconductor substrate (N ++ substrate) 1.
2 is formed, an etching mask 11 is formed on the surface of the N-epi layer 2, and the trench 12 is deeper from the surface of the N-epi layer 2 to the N ++ substrate 1 and has a larger opening than the bottom surface. To form

At this time, a rounded tapered surface is formed at the periphery of the trench opening in order to obtain the effects described later.
As an example of a process of forming such a trench opening peripheral portion, after the trench opening, the vicinity of the trench opening peripheral portion of the etching mask (for example, SiO ₂ film) 11 on the substrate used for the trench opening is reduced. A process (for example, isotropic etching using ammonium fluoride) and etching using CDE may be performed so that the periphery of the trench opening is rounded.

As another example of the step of forming the peripheral edge of the trench opening as described above, when an etching machine that opens so as to taper the trench side face is used, the supply time of the RIE gas and the The periphery of the trench opening may be rounded by repeating the gas supply time while changing the gas supply time according to a predetermined pattern.

Next, as shown in FIG. 4B, a P-type impurity (B in this example) and an N-type impurity (B in this example) are implanted into the trench side wall by an implantation angle of about 7 °, for example, by a rotary ion implantation method.
As) is implanted. At this time, As ion implantation is performed, for example, under the conditions of an acceleration voltage of 60 KeV and a dose of 4.1 × 10 ¹³ cm ⁻² , and B ion implantation is performed, for example, at an acceleration voltage of 60 KeV.
V and the dose are 4 × 10 ¹³ cm ⁻² .

Next, simultaneous diffusion of As and B is performed by thermal diffusion at 1150 ° C. for 2,000 minutes or more. At this time, since the diffusion coefficient of B is sufficiently larger than the diffusion coefficient of As,
As shown in FIG. 4 (c), the N pillar layer 4 has a rectangular cross section along the longitudinal direction on the side wall surface of the trench and the P pillar 4 has a rectangular cross section adjacent to the N pillar layer 4 in the lateral direction and overlapped with diffusion from both sides.
The pillar layers 3 are formed at substantially the same concentration. That is, in the structure after the heat treatment, an NPN pillar layer in which the N pillar layer 4 exists on both sides (trench side walls) with the internal P pillar layer 3 interposed therebetween is completed.

Further, (As) in the two N pillar layers 4
−B) The sum of the total amount and the total amount of (B−As) in the P pillar layer 3 are equal to each other within ± 5%. This high-precision control of the amount of impurities is achieved by forming As, B
This can be achieved by simultaneous implantation of ions.

Focusing on the fact that the dose of ion implantation is determined by the direction (angle) of the surface incident by ion implantation, the tapered surface at the periphery of the trench opening is previously rounded. Direction (angle) of the incident surface
Is changed by the roundness of the tapered surface, so that the gradient of the impurity concentration distribution from the upper surface to the depth direction in the P pillar layer 3 can be controlled to be gentle.

Next, as shown in FIG. 4D, after the insulator 5 is embedded in the trench, the surface is flattened by, for example, a CMP method or etching. In this example, an oxide film (SiO ₂ film) is formed on the trench surface by thermal oxidation, and further, a SiO ₂ film or a SiN film is formed by a chemical vapor deposition (CVD) method.

At this time, Si ₃ After forming the N ₄ film or the SiO ₂ film, polysilicon (Poly Si) may be preferentially grown and filled in the trench. Since the polysilicon inside the trench is not a current path, it is not necessary to completely bury the polysilicon, and it is possible to bury the polysilicon at a high growth rate by growing the polysilicon from both sides of the trench.

Next, a gate electrode 8 is formed on the channel region on the upper surface of the P pillar layer 3 via a gate insulating film 7, and an N + source region 6 is selectively formed on the surface of the P pillar layer 3. . Thus, a DTMOS FET having the N ++ substrate 1 as a drain and the N + pillar layer 4 as a current path between the N + source region 6 and the drain is obtained.

That is, according to the method of manufacturing the DTMOS FET of the above-described embodiment, the tapered surface has a depth reaching the substrate from the surface of the epilayer, has a wider opening than the bottom surface, and has a rounded edge at the periphery of the opening. By forming a trench with a trench, and ion-implanting a P-type impurity and an N-type impurity into the trench side wall and performing thermal diffusion, the N pillar layer 4 along the vertical direction on the trench side wall surface and adjacent to the N pillar layer 4 along the vertical direction are formed. The P pillar layer 3 is formed.

According to such a process, it becomes possible to form the P pillar layer 3 in which the distribution of the impurity concentration in the depth direction from the surface gradually changes from the surface to a predetermined depth position. At this time, a portion having a high impurity concentration (P base layer) can be formed on the upper surface of the P pillar layer 3 at the same time, and the step of forming the P base layer later can be reduced. However, it goes without saying that the P base layer forming step may be performed later.

In the above description, the method of manufacturing an N-type DTMOS FET has been described, but the present invention can be similarly applied to a method of manufacturing a P-type DTMOSFET.

<Second Embodiment> In the first embodiment, the DTMOS FET has a rounded tapered surface at the periphery of the trench opening, but the DTMOS FET has a rounded periphery at the periphery of the trench opening. Even when the tapered surface is not provided, the same effect as described above can be obtained by adopting the structure having the impurity concentration distribution as shown in FIG. 2 (the second embodiment).

<Third Embodiment> Second Embodiment In the first embodiment, a DTMOS FET has been described. However, even in a planar-structure MOS FET, the P base region is formed as shown in FIG. It can be easily inferred that the same effect as described above can be obtained by adopting a structure having a high impurity concentration distribution (third embodiment).

[0072]

As described above, according to the present invention, it is possible to prevent a concentration of an electric field in a base region below a source region, stably secure a higher reverse breakdown voltage between a drain and a source, and realize a MOS FET having a low on-resistance. A possible semiconductor device and a method for manufacturing the same can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of the structure of a DTMOS FET according to a first embodiment of the present invention.

FIG. 2 is a view showing an example of an impurity concentration distribution in a vertical section (BB ′ line) in a P + pillar layer of the DTMOS FET shown in FIG. 1;

FIG. 3 is a graph showing an example of a result of verifying a reverse breakdown voltage between a drain and a source by simulation using the P base depth of the DTMOS FET shown in FIG. 1 as a parameter.

FIG. 4 is a sectional view showing a half of a unit element (cell) as an example of a manufacturing process of the DTMOS FET shown in FIG. 1;

FIG. 5 is a cross-sectional view showing a part of a conventional power MOS FET having a planar structure.

FIG. 6 is a sectional view showing a part of a conventional power MOS FET having a super junction structure.

FIG. 7 is a cross-sectional view showing a part of the basic structure of a DTMOS FET currently proposed.

8 is a perspective view showing a part of a plane pattern and a cross-sectional structure of a stripe pattern type DTMOS FET as an example of the DTMOS FET shown in FIG. 7;

9 is a perspective view showing a part of a plane pattern and a cross-sectional structure of an offset mesh type DTMOS FET as another example of the DTMOS FET shown in FIG. 7;

FIG. 10 shows a DT according to an improved example of the structure shown in FIGS. 7 to 9;
FIG. 2 is a cross-sectional view illustrating an example of the structure of a MOS FET.

FIG. 11 is an insulator inside the trench shown in FIGS. 7 to 9;
85 is a cross-sectional view showing an example of the structure of the DTMOS FET according to the example of the 85 improved structure.

FIG. 12 is a sectional view showing a part of the structure of the DTMOS FET for schematically explaining a part of the manufacturing process of the DTMOS FET shown in FIG. 7;

[Explanation of symbols]

 1… N ++ substrate, 2… N-epi layer, 3… P + pillar layer, 4… N + pillar layer, 5… insulator layer, 6… N + source region, 7… gate insulating film, 8… gate electrode.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Shigeo Kozuki 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside Toshiba Microelectronics Center

Claims (16)

[Claims] A semiconductor substrate having a low-resistance epilayer; a depth extending from a surface of the low-resistance epilayer to the semiconductor substrate; an opening wider than a bottom surface; and a rounded edge of the opening. A trench having a tapered surface; a first conductivity type impurity and a second conductivity type impurity ion-implanted from the side wall of the trench into the low resistance epi layer by thermal diffusion; and opposing side wall surfaces of adjacent trenches A second conductivity type pillar layer vertically formed along each of the first and second conductivity type pillar layers, a first conductivity type pillar layer formed vertically adjacent to the second conductivity type pillar layer, and an insulator embedded in the trench. A second conductivity type source region selectively formed on the surface of the first conductivity type pillar layer; and a channel region between the second conductivity type source region and the second conductivity type pillar layer. Through the gate insulating film A MOS FET having the first conductivity type pillar layer as a base, the second conductivity type pillar layer as a current path, and the semiconductor substrate as a drain. A semiconductor device characterized in that the gradient of the concentration distribution becomes nearly zero at a depth of 4.0 μm or more from the surface of the one-conductivity-type pillar layer and has a substantially constant concentration. 2. A dose amount of the ion implantation of the first conductivity type impurity is controlled by a rounded tapered surface of an opening peripheral portion, and an impurity concentration in a depth direction from a surface of the first conductivity type pillar layer is controlled. 2. The semiconductor device according to claim 1, wherein the distribution gradually changes from the surface of the first conductivity type pillar layer to a predetermined depth position. 3. The semiconductor device according to claim 1, wherein an upper surface portion of said first conductivity type pillar layer is a base region having a high first conductivity type impurity concentration. 4. The second conductive type pillar layer according to claim 2, wherein
The total amount of (conductivity type impurity amount-first conductivity type impurity amount) and (first conductivity type impurity amount-second impurity amount) in the first conductivity type pillar layer.
4. The semiconductor device according to claim 1, wherein a difference between the total amount of the conductive type impurities) is set to be within ± 5%. 5. 5. The semiconductor device according to claim 5, wherein a second conductive type source region having a concentration substantially equal to that of said second conductive type source region is selectively formed on an upper surface of said second conductive type pillar layer.
2. A conductive type region is formed.
The semiconductor device according to any one of claims 4 to 4. 6. The semiconductor substrate having the low resistance epi layer is an N + substrate having an N- epi layer, wherein the first conductivity type impurity is Boron, and the second conductivity type impurity is As. The semiconductor device according to claim 1. 7. An insulator buried inside the trench is formed on the inner wall of the trench by a SiO ₂ film or a Si ₃ film. The semiconductor device according to claim 1, wherein polysilicon is buried through an N ₄ film. 8. The semiconductor device according to claim 1, wherein said gate insulating film is made of SiO ₂ , and said gate electrode is made of polysilicon or metal silicide. 9. A tapered surface of a semiconductor substrate having a low-resistance epi-layer, which has a depth reaching the semiconductor substrate from the surface of the low-resistance epi-layer, an opening wider than a bottom surface, and a rounded periphery of the opening. Forming a trench having: a first conductivity type impurity and a second conductivity type impurity by ion-implanting a first conductivity type impurity and a second conductivity type impurity into sidewalls of the trench; The second conductivity type pillar layer extending along the trench side wall surface in the vertical direction by utilizing the difference in the diffusion coefficient and the impurity concentration distribution in the depth direction from the surface adjacent to the second conductivity type pillar layer at the predetermined depth position from the surface. Forming a first-conductivity-type pillar layer that gradually changes until the first-conductivity-type pillar layer; burying an insulator in the trench and planarizing the surface; and selectively forming an upper surface of the first-conductivity-type pillar layer. Second Forming a conductive type source region, and forming a gate electrode on a channel region between the second conductive type source region and the second conductive type region via a gate insulating film; Forming a MOS FET using the second conductive type pillar layer as a drain and a current path between the drain and the second conductive type source region. 10. The method according to claim 1, wherein, during the ion implantation, a dose amount of the ion implantation of the first conductivity type impurity is controlled by a rounded tapered surface of an opening periphery to realize the impurity concentration distribution. A method for manufacturing a semiconductor device according to claim 9. 11. The method according to claim 1, wherein the ion implantation is performed by increasing a dose of ion implantation of the first conductivity type impurity into an upper surface portion of the first conductivity type pillar layer and diffusing the ion into the upper surface portion of the first conductivity type pillar layer by the diffusion. The method according to claim 10, wherein a second conductivity type base region is formed. 12. The method according to claim 9, wherein the step of flattening uses CMP or etching.
13. The method for manufacturing a semiconductor device according to claim 1. 13. The semiconductor substrate having the low resistance epi layer is an N + substrate having an N- epi layer, wherein the first conductivity type impurity is Boron and the second conductivity type impurity is As. The method of manufacturing a semiconductor device according to claim 9. 14. When burying an insulator in the trench, an SiO ₂ film or Si ₃ 14. The method of manufacturing a semiconductor device according to claim 9, wherein polysilicon is grown inside the trench after forming the N ₄ film. 15. The method of manufacturing a semiconductor device according to claim 9, wherein said gate insulating film is made of SiO ₂ , and said gate electrode is made of polysilicon or metal silicide. 16. A vertical pillar layer is formed so as to be adjacent to a unit MOS FET region surrounded by a trench type element isolation region, and a first pillar layer located at the center of the pillar layer is formed.
The conductivity type pillar layer has a gentle gradient of impurity concentration distribution from the upper surface to the depth direction, and the gradient of the concentration distribution becomes nearly constant at a depth of 4.0 μm or more from the surface, and becomes almost constant. A semiconductor device, comprising: