JP2002124662A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a static induction thyristor of a normally-off type which can control a large current. SOLUTION: In an electrostatic induction thyristor 100, a gate for controlling a current flowing through anode and cathode electrodes 92 and 94 is provide within N substrates 10 and 20 provided between the anode and cathode. A plurality of recesses 52 are made in the N substrate 10, a P+ gate region 65 is provided in a region exposed at sides of the recesses 52 of the substrate 10, and a P+ region 62 is provided between the gate regions of the same conductivity type as that of the gate regions 65 within the substrate 10 between the gate regions 65, so that a depletion layer continuously expands between the gate regions 65 under a condition that no bias is applied to the gate regions 64.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a normally-off type electrostatic induction (SI) thyristor.

[0002]

2. Description of the Related Art FIG.
FIG. 10 to FIG. 10 are perspective sectional views for explaining a conventional electrostatic induction thyristor 300 and a method for manufacturing the same.

Conventionally, this type of electrostatic induction thyristor 300
Was manufactured as follows.

[0004] That is, first, as shown in FIG. 8, N ^-
By selectively diffusing a P-type impurity into one main surface of the substrate 310, a P ⁺ gate region 314 is selectively formed.

Next, as shown in FIG. 9, an N ^- epitaxial layer 320 is formed on an N ^- substrate 310 by a chemical vapor deposition method.
To form At this time, a P ⁺ gate region 314 is also formed in the N ⁻ epitaxial layer 320 by auto doping.

[0006] Next, as shown in FIG. 10, N ^- substrate 31
The P layer 312 is formed by an impurity diffusion to the lower surface of the 0, N ^-
N ^{+ is formed on} the upper surface of the epitaxial layer 320 by impurity diffusion.
A layer 322 is formed.

Next, the anode electrode 3 is formed on the lower surface of the P layer 312.
40, and the cathode electrode 35 is formed on the upper surface of the N ⁺ layer 322.
0 is formed.

In the thus formed electrostatic induction thyristor 300, the P layer 312 is composed of the anode and the N ⁺ layer 32.
2 functions as a cathode, N ^- substrate 310 and N ^- epitaxial layer 320 both function as N base 360, and P ⁺ gate region 314 controls the anode current flowing between anode electrode 340 and cathode electrode 350. Functions as a gate.

In this conventional static induction thyristor 300, a P ⁺ gate region 314 having a high impurity concentration is buried in order to increase the maximum breaking current. To embed thus the P ⁺ gate regions 314 in N base 360 within, first, as shown in FIG. 8, N ^- substrate 310
P ⁺ gate region 314 is selectively formed on one main surface of
Thereafter, by chemical vapor deposition, N ^- it is necessary to form an epitaxial layer 320 ^- N on the substrate 310.

This N^-The epitaxial layer 320 is made of P⁺of
N where gate region 314 is selectively formed^-Substrate 310
Formed on⁺Grown on the gate region 314
N ^-Stacking holes are formed on the epitaxial layer 320.
High-quality N^-Epitaki
As a result, a high quality N-base
There is a problem that the disk 360 cannot be obtained.

As described above, the P ⁺ gate region 31
Since the impurity of No. 4 adversely affects the crystallinity of the N ⁻ epitaxial layer 320, there is a limit in increasing the impurity concentration of the P ⁺ gate region 314. As a result, it is necessary to increase the maximum cutoff current beyond a certain limit. I couldn't do it either.

Such a conventional electrostatic induction thyristor 30
In order to manufacture the normally-off type static induction thyristor 400 using the method 0 and this manufacturing method, it is conceivable to provide a P ⁺ region 315 also between the P ⁺ gate regions 314.

FIGS. 11 to 13 are perspective cross-sectional views for explaining a method of manufacturing a normally-off type electrostatic induction thyristor 400 using such a conventional method of manufacturing a static induction thyristor 300. is there.

[0014] First, as shown in FIG. 11, N ^- substrate 31
By selectively diffusing a P-type impurity into one main surface of P 0, a P ⁺ gate region 314 is selectively formed. Further, by selectively diffusing a P-type impurity over the entire main surface of N ⁻ substrate 310, P ⁺ is formed between P ⁺ gate regions 314.
A region 315 is formed.

Next, as shown in FIG. 12, an N ^- axial layer 320 is formed on an N ^- substrate 310 by chemical vapor deposition.
To form At this time, a P ⁺ gate region 314 and a P ⁺ region 315 are also formed in the N ⁻ epitaxial layer 320 by auto doping.

[0016] Next, as shown in FIG. 13, N ^- substrate 31
P layer 312 is formed on the lower surface of
^- forming the N ⁺ 322 by an impurity diffusion to the top surface of the epitaxial layer 320.

Next, the anode electrode 3 is formed on the lower surface of the P layer 312.
40, and the cathode electrode 35 is formed on the upper surface of the N ⁺ layer 322.
0 is formed.

In the thus formed electrostatic induction thyristor 400, the P layer 312 is composed of the anode and the N ⁺ layer 32.
2 functions as a cathode, N ^- substrate 310 and N ^- epitaxial layer 320 both function as N base 360, and P ⁺ gate region 314 controls the anode current flowing between anode electrode 340 and cathode electrode 350. Functions as a gate. Further, in this case, P ⁺
Since the P ⁺ region 315 is formed between the P ⁺ gate regions 314, the depletion layer is continuously formed between the P ⁺ gate regions 314 even when no bias is applied to the gate. Therefore, the thus formed electrostatic induction thyristor 400 functions as a normally-off type electrostatic induction thyristor.

However, when the normally-off type electrostatic induction thyristor 400 is manufactured in this manner, the following problem is further caused in addition to the above-described problem of manufacturing the conventional electrostatic induction thyristor 300. Come up.

That is, in the normally-off type static induction thyristor 400, not only the P ⁺ gate region 314 having a high impurity concentration but also the P ⁺ region 315 are embedded in the N base 360. To embed Thus P ⁺ of the gate region 314 and P ⁺ region 315 in N base 360 within, first, as shown in FIG. 11, N ^- gate region 314 of P ⁺ on one main surface of the substrate 310 and A P ⁺ region 315 is formed, and then N ⁻ is formed by chemical vapor deposition.
An N ⁻ epitaxial layer 320 needs to be formed on the substrate 310.

[0021] The N ^- epitaxial layer 320, gate region 314 and P ⁺ region 315 of P ⁺ is formed N ^-
Since it is formed on the substrate 310, the P ⁺ gate region 31
4 N was grown on the upper and the P ⁺ region 315 ^- crystal defects such as stacking hold easily occur in the epitaxial layer 320, high quality N ^- epitaxial layer 320 is not only on the P ⁺ gate region 314, P ⁺ Is not obtained even between the gate regions 314 of the high-quality N base 36.
There was a problem that it was more difficult to obtain 0.

The above-mentioned electrostatic induction thyristor 400
Since the P ⁺ gate region 314 is formed by diffusing impurities on one main surface of the N ⁻ substrate 310,
⁺ The side of gate region 314 is rounded. Therefore,
The depletion layer extending between the P ⁺ gate regions 314 is an anode-
It does not extend in parallel to the direction in which the anode current flows between the cathodes, and as a result, there is a problem that large current cannot be controlled.

Accordingly, an object of the present invention is to provide a normally-off type electrostatic induction thyristor capable of controlling a large current.

[0024]

According to the present invention, a gate for controlling a current flowing between the anode and the cathode is provided in a semiconductor substrate provided between the anode and the cathode. In the semiconductor device provided with, a cavity is provided in the semiconductor substrate, a gate region made of a semiconductor is provided in a region exposed on a side portion of the cavity of the semiconductor substrate, and further, in a state where no bias is applied to the gate, A semiconductor device is provided, wherein a semiconductor region of the same conductivity type as the gate region is provided in the semiconductor substrate between the gate regions so that a depletion layer continuously extends between the gate regions.

Preferably, the semiconductor region is provided continuously with the gate region.

It is preferable that a side portion of the cavity is provided substantially parallel to a direction of the current flowing between the anode electrode and the cathode electrode.

Further, preferably, a gate region is also provided in a region of the semiconductor substrate exposed at the bottom of the cavity.

Preferably, a gate electrode made of a good conductor electrically connected to the gate region is further provided in the cavity of the semiconductor substrate.

Further, the semiconductor substrate is a first conductivity type first semiconductor.
Semiconductor layer, a second semiconductor layer of another conductivity type provided on the first semiconductor layer, and a higher impurity concentration than the second semiconductor layer, provided on the second semiconductor layer. A third semiconductor layer of the other conductivity type, and one of the anode electrode and the cathode electrode is provided so as to be electrically connected to the first semiconductor layer. The other is provided so as to be electrically connected to the third semiconductor layer, the gate region and the semiconductor region are the one conductivity type semiconductor, and the cavity, the gate region, and the semiconductor region are the second semiconductor layer. It is preferably provided in the semiconductor layer.

[0030]

According to the present invention, there is provided a semiconductor device provided with a gate for controlling a current flowing between an anode electrode and a cathode electrode in a semiconductor substrate provided between the anode electrode and the cathode electrode. A cavity is provided in the substrate, and a gate region made of a semiconductor is provided in a region exposed on the side of the cavity of the semiconductor substrate. Since the anode current flows along the side of the cavity of the semiconductor substrate, by providing the gate region along the side of the cavity in this manner, the length of the depletion layer extending from the gate region at the time of off in the anode current direction is reduced. The channel width can be increased. Therefore, the withstand voltage in the off state can be increased,
Further, a leakage current can be reduced, and a semiconductor device which has an excellent breaking ability and can control a large current can be obtained.

Further, since the channel width can be increased in this manner, a predetermined off characteristic can be obtained without reducing the interval between the gate regions. Therefore, it is necessary to reduce the interval between the cavities of the semiconductor substrate. Disappears. As a result, it is possible to improve the yield when the cavity is finely processed in the semiconductor substrate.

In addition, since it is not necessary to reduce the space between the cavities, the cross-sectional area of the semiconductor substrate between the cavities is suppressed from being reduced, and the resistance of the semiconductor substrate between the cavities is reduced. The voltage can be reduced to increase the current.

Further, by providing a semiconductor region of the same conductivity type as the gate region between the gate regions so that the depletion layer continuously spreads between the gate regions when no bias is applied to the gate, a normally-off type Is obtained.

By providing the semiconductor region continuously with the gate region, the depletion layer can be more surely continuously extended between the gate regions in a state where no bias is applied to the gate.

Further, by providing the side portions of the cavity substantially parallel to the direction of the current flowing between the anode electrode and the cathode electrode, the depletion layer can be uniformly extended over the entire length of the channel between the gate regions when off. it can.
Therefore, the withstand voltage at the time of off-state can be further increased, the leakage current can be further reduced, and a semiconductor device having more excellent breaking ability can be obtained.

Further, by providing the side of the cavity almost parallel to the direction of the current flowing between the anode electrode and the cathode electrode, more excellent off characteristics can be obtained. The spacing between the cavities can be made wider. As a result, the yield at the time of finely processing the cavity in the semiconductor substrate can be further improved.

Further, since the space between the cavities can be made wider, the cross-sectional area of the semiconductor substrate between the cavities can be made larger, and the resistance of the semiconductor substrate between the cavities can be made smaller. The voltage is further reduced, and the current can be further increased.

By providing the gate region also in the region exposed at the bottom of the cavity of the semiconductor substrate, the resistance in the lateral direction of the gate is reduced, the maximum cutoff current can be increased, and the frequency can be increased.

Further, by further providing a gate electrode made of a good conductor electrically connected to the gate region in the cavity of the semiconductor substrate, the resistance in the lateral direction of the gate is reduced and the maximum breaking current can be increased. Carrier extraction current can be increased, and higher-speed switching becomes possible.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the accompanying drawings.

(First Embodiment) FIG. 1 is a cross-sectional view for explaining a static induction thyristor according to a first embodiment of the present invention and a method of manufacturing the same.

That is, first, at least
N is mirror-polished ^-Substrates 10 and 2
Prepare 0.

Next, as shown in FIG. 1A, N ^- substrate 10
A P ⁺ layer 12 is formed on the lower surface of the substrate by an impurity diffusion method. Next, a P ⁺ gate region 42 is selectively formed on the upper surface 14 of the N ⁻ substrate 10 by selectively diffusing boron as a P-type impurity.

Next, as shown in FIG. 1B, boron, which is a P-type impurity, is diffused to form a P ⁺ region 44 over the entire upper surface 14 of the N ⁻ substrate 10, thereby forming a region between the P ⁺ gate regions 42. A P ⁺ region 46 between gate regions is formed on the upper surface 14 of the N ⁻ substrate 10. The P ⁺ region 46 between the gate regions is
It is provided continuously with the P ⁺ gate region 42.

On the other hand, as shown in FIG. 1C, N ^- substrate 20
N ⁺ layer 22 is formed on the upper surface of the substrate by an impurity diffusion method.

Next, sulfuric acid + hydrogen peroxide aqueous solution
The N ^- substrates 10 and 20 are subjected to ultrasonic cleaning to remove organic substances and metals.

Next, the N ^- substrates 10 and 20 are washed with pure water and spin-dried at room temperature.

Next, as shown in FIG. 1D, the N ^- substrate 10
The N ⁻ substrate 10 and the N ⁻ substrate 20 are joined by heating at about 800 ° C. in a hydrogen atmosphere while the upper surface 14 of the N ⁻ substrate 20 and the lower surface 24 of the N ⁻ substrate 20 are in contact with each other.

Next, the P ⁺ formed on the lower surface of the N ^- substrate 10
N ⁺ formed on the lower surface of the layer 12 and the upper surface of the N ⁻ substrate 20
An anode electrode 92 and a cathode electrode 94 are formed on the upper surface of the layer 22, respectively.

In the thus formed electrostatic induction thyristor 100, the P ⁺ layer 12 is an anode, the N ⁺ layer 2
2 is a cathode, the N ^- substrate 10 and the N ^- substrate 20 both function as an N base 30, and the P ⁺ gate region 42 is
It functions as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94.

In this embodiment, the gate region 4 of P ⁺
Since the N base 30 in which the P ⁺ region 46 between the gate region 2 and the gate region are buried is formed by joining the N ⁻ substrate 10 and the N ⁻ substrate 20, the N base 30 having uniform and high-quality crystallinity can be obtained. . In this embodiment, N
^Since the entire surface of the upper surface 14, which is the bonding portion of the substrate 10, is P ⁺ , the entire surface including the P ⁺ gate region 42 can be uniformly bonded. Further, since the P ⁺ gate region 42 and the P ⁺ region 46 between the gate regions are both P-type, the manufacturing process is simplified. Further, it is possible to increase the concentration of the P ⁺ gate region 42, and it is possible to increase the maximum cutoff current.

In this embodiment, the gate region 4 of P ⁺
Between the two, a P ⁺ region 46 between the gate regions which is continuous with the P ⁺ gate region 42 is provided. Therefore, even when no bias is applied to the gate, the gate region 42 of P ⁺
The depletion layer continuously spreads therebetween, and a normally-off type electrostatic induction thyristor 100 is formed.

In this embodiment, the bonding is performed at about 800 ° C., but the bonding can be performed at about 400 ° C. or higher. However, impurities becomes about 1100 ° C. or more P ⁺ gate region 42 and gate region between P ⁺ region 46 the N ^- undesirable because diffused into the substrate 10 and 20, adversely affect the properties of the thyristor. The joining is more preferably performed at a normal pressure in a range of about 700 to 1100 ° C. This is because thermal diffusion of impurities is small and distortion of the junction crystal lattice can be reduced.

[0054] In the present embodiment, the pressure N ^- were subjected to bonding without adding particular from both sides of the substrate 10 and 20, N ^- be carried out joining while applying a pressure from both sides of the substrate 10 and 20 preferable. This is because the bonding temperature is reduced, the heat diffusion is suppressed, and the number of non-contact portions is reduced. The pressure is preferably added in the range of ^{0.1kg / cm 2 ~100kg / cm 2} . If the pressure is 0.1 kg / cm ² or less, the contact becomes insufficient, and if the pressure is 100 kg / cm ² or more, a displacement occurs due to deformation. At this time, the bonding temperature is preferably about 400 to 1100 ° C.
More preferably, it is about 500-1000 ° C. This is because the bonding temperature is lowered by the pressurization.

(Second Embodiment) FIG. 2 is a sectional view for explaining an electrostatic induction thyristor and a method of manufacturing the same according to a second embodiment of the present invention.

First, at least N ^- substrates 10, 20 whose surfaces to be joined to each other are mirror-polished are prepared.

Next, as shown in FIG. 2A, N ^- substrate 10
About 50 μm in width by photolithography on the upper surface 14 of
m, concave portions 52 having a depth of about 20 μm are provided at a pitch of about 70 μm. A convex portion 54 is formed between the concave portions 52. The side portion 51 of the concave portion 52 is provided substantially perpendicular to the upper surface 14 of the N ⁻ substrate 10.

Next, as shown in FIG. 2B, N ^- substrate 10
A P ⁺ layer 12 is formed on the lower surface of the substrate by an impurity diffusion method.

[0059] Further, boron, which is a P-type impurity by using N ^- diffusion on the entire surface from the upper surface 14 of the substrate 10, P
^{A +} region 60 is formed on the entire upper surface 14 of the N ⁻ substrate 10.
By forming P ⁺ region 60 over the entire surface, side gate region 64 of P ⁺ , bottom gate region 66, and P ⁺ region 62 between the gate regions are simultaneously formed. P ⁺
N is the side gate regions 64 and bottom gate regions 66 exposed respectively to the sides 51 and bottom 53 of the recess 52 ^-
A P ⁺ region 60 between gate regions is formed in a region of the N ⁻ substrate 10 formed in the region of the substrate 10 and exposed on the upper surface 56 of the projection 54. The P ⁺ bottom gate region 66, the side gate region 64, and the P ⁺ region 62 between the gate regions are formed continuously. The P ⁺ side gate region 64 and the bottom gate region 66 constitute a P ⁺ gate region 65. The diffusion of boron is about 1 in a BBr ₃ + O ₂ atmosphere.
The test was performed at a temperature of from 500 to 1200 ° C. At the time of the boron diffusion, an oxide film is formed on the side portion 51 and the bottom portion 53 of the concave portion 52 and on the upper surface 56 of the convex portion 54, but this is not shown.

[0060] On the other hand, as shown in FIG. 2C, N ^- substrate 20
N ⁺ layer 22 is formed on the upper surface of the substrate by an impurity diffusion method.

Next, sulfuric acid + hydrogen peroxide aqueous solution
The N ^- substrates 10 and 20 are subjected to ultrasonic cleaning to remove organic substances and metals.

Next, the N ^- substrates 10 and 20 are washed with pure water and spin-dried at room temperature.

Next, as shown in FIG. 2D, with the upper surface 56 of the convex portion 54 of the N ⁻ substrate 10 between the concave portion 52 and the lower surface 24 of the N ⁻ substrate 20 being in contact with each other, the 800 ° C
The N ⁻ substrate 10 and the N ⁻ substrate 20
To join.

Next, the P ⁺ formed on the lower surface of the N ^- substrate 10
N ⁺ formed on the lower surface of the layer 12 and the upper surface of the N ⁻ substrate 20
An anode electrode 92 and a cathode electrode 94 are formed on the upper surface of the layer 22, respectively.

In the thus formed electrostatic induction thyristor 100, the P ⁺ layer 12 is an anode, the N ⁺ layer 2
2 is a cathode, the N ⁻ substrate 10 and the N ⁻ substrate 20 both function as an N base 30, and the P ⁺ gate region 65 is
It functions as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94.

Also in this embodiment, the P ⁺ gate region 6
5 and the N base 30 in which the P ⁺ region 62 between the gate regions is buried is formed by joining the N ⁻ substrate 10 and the N ⁻ substrate 20, so that the N base 30 having uniform and high quality crystallinity can be obtained. . Further, it is possible to increase the concentration of the P ⁺ gate region 65, so that the maximum cutoff current can be increased.

In this embodiment, the gate region 6 of P ⁺
Between the gate regions 65 and P
⁺ Region 62 is provided. Therefore, even when no bias is applied to the gate, the depletion layer continuously extends between the gate regions 65, particularly between the side gate regions 64, and the normally-off type static induction thyristor 100 is formed.

In this embodiment, a concave portion 52 is provided on the upper surface 14 of the N ⁻ substrate 10, and a cavity is formed in the N base 30 by the concave portion 52 and the lower surface 24 of the N ⁻ substrate 20. In the present embodiment, a side gate region 64 is provided in a region exposed on the side portion 51 of the concave portion 52 of the N ⁻ substrate 10. Since the anode current flows along the side portion 51 of the concave portion 52, by providing the side gate region 64 along the side portion 51 of the concave portion 52 in this manner, the channel width can be increased, and the gate can be turned off when off. The length of the depletion layer extending from the region 65 in the anode current direction can be increased. Therefore, the withstand voltage in the off state can be increased, the leakage current can be reduced, the breaking ability is excellent, and the electrostatic induction thyristor 100 capable of controlling a large current can be realized.
Is obtained.

Since the channel width can be increased in this manner, a predetermined off characteristic can be obtained without reducing the distance between the gate regions 65. Therefore, the distance between the concave portions 52 of the N ^- substrate 10 can be improved. Need not be reduced.
As a result, the yield when finely processing the concave portion 52 on the upper surface of the N ^- substrate 10 can be improved.

In addition, since it is not necessary to reduce the distance between the concave portions 52, the N ^- substrate 10 between the concave portions 52 is not required.
Is also suppressed, and the N
^- resistance of the substrate 10 is reduced, as a result, the ON voltage attained is to large current decrease. Further, as in the present embodiment, the side portion 51 of the concave portion 52 is provided substantially parallel to the direction of the anode current flowing between the anode electrode 92 and the cathode electrode 94, so that the side gate region 64 also has the anode current. Thus, the depletion layer can be uniformly extended over the entire length of the channel between the gate regions 65 when the device is turned off. Therefore, the withstand voltage at the time of OFF can be further increased, the leakage current can be further reduced, and the electrostatic induction thyristor 100 which is excellent in the breaking ability and can control a larger current can be obtained.

(Third Embodiment) FIG. 3 is a sectional view for explaining an electrostatic induction thyristor and a method of manufacturing the same according to a third embodiment of the present invention.

First, as shown in FIGS. 3A and 3B,
In the same manner as in the first embodiment, N ^- the P ⁺ gate region 42 and gate region between P ⁺ region 46 to the upper surface 14 of the substrate 10 ^- to form a P ⁺ layer 12 on the lower surface of the substrate 10, N Form. The P ⁺ region 46 between the gate regions is provided continuously with the P ⁺ gate region 42.

[0073] On the other hand, as shown in FIG. 3C, N ^- substrate 20
An N ⁺ layer 22 is formed on the upper surface of the substrate by an impurity diffusion method, and a P ⁺ region 26 is formed on the entire lower surface 24 of the N ⁻ substrate 20 by an impurity diffusion method.

Next, sulfuric acid + hydrogen peroxide aqueous solution
The N ^- substrates 10 and 20 are subjected to ultrasonic cleaning to remove organic substances and metals.

Next, the N ^- substrates 10 and 20 are washed with pure water and spin-dried at room temperature.

[0076] Next, as shown in FIG. 3D, N ^- substrate 10
The N ⁻ substrate 10 and the N ⁻ substrate 20 are joined by heating at about 800 ° C. in a hydrogen atmosphere while the upper surface 14 of the N ⁻ substrate 20 and the lower surface 24 of the N ⁻ substrate 20 are in contact with each other.

Next, the P ⁺ formed on the lower surface of the N ^- substrate 10
N ⁺ formed on the lower surface of the layer 12 and the upper surface of the N ⁻ substrate 20
An anode electrode 92 and a cathode electrode 94 are formed on the upper surface of the layer 22, respectively.

In the thus formed electrostatic induction thyristor 100, the P ⁺ layer 12 is the anode, the N ⁺ layer 2
2 is a cathode, the N ^- substrate 10 and the N ^- substrate 20 both function as an N base 30, and the P ⁺ gate region 42 is
It functions as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94.

Also in this embodiment, the P ⁺ gate region 4
Since the N base 30 in which the P ⁺ region 46 between the gate region 2 and the gate region are buried is formed by joining the N ⁻ substrate 10 and the N ⁻ substrate 20, the N base 30 having uniform and high-quality crystallinity can be obtained. . Also in this embodiment, N
^Since the entire surface of the upper surface 14, which is the bonding portion of the substrate 10, is P ⁺ , the entire surface including the P ⁺ gate region 42 can be uniformly bonded. Further, since the P ⁺ region 26 is also formed on the lower surface 24 of the N ^- substrate 20, the electrical connection is further improved. Further, it is possible to increase the concentration of the P ⁺ gate region 42, and it is possible to increase the maximum cutoff current.

In this embodiment, the gate region 4 of P ⁺
Between the two, a P ⁺ region 46 between the gate regions that is continuous with the P ⁺ gate region 42 is provided, and a P ⁺ region 26 is further provided on the P ⁺ region 46 between the gate regions. Therefore, even when no bias is applied to the gate, the depletion layer continuously spreads between the P ⁺ gate regions 42, and the normally-off type static induction thyristor 100 is formed.

(Fourth Embodiment) FIG. 4 is a sectional view for explaining a static induction thyristor according to a fourth embodiment of the present invention and a method of manufacturing the same.

First, as shown in FIGS. 4A and 4B,
In the same manner as in the second embodiment, N ^- a recess 52 and protrusions 54 on the upper surface 14 of substrate 10, N ^- substrate 10
P ⁺ layer 12 is formed on the lower surface of P ⁺ by impurity diffusion method, and P ⁺ side gate region 64 and bottom gate region 66 are formed in recess 5.
A P ⁺ region 62 between gate regions is formed in a region of the N ⁻ substrate 10 exposed on the side portion 51 and the bottom portion 53 of the second substrate 2, and a region of the N ⁻ substrate 10 exposed on the upper surface 56 of the projection 54. P ⁺ bottom gate region 66, side gate region 64
The P ⁺ region 62 between the gate regions is formed continuously. P ⁺ side gate region 64 and bottom gate region 6
6 form a P ⁺ gate region 65.

[0083] On the other hand, as shown in FIG. 4C, N ^- substrate 20
An N ⁺ layer 22 is formed on the upper surface of the substrate by an impurity diffusion method, and a P ⁺ region 26 is formed on the entire lower surface 24 of the N ⁻ substrate 20 by an impurity diffusion method.

Next, sulfuric acid + hydrogen peroxide aqueous solution
The N ^- substrates 10 and 20 are subjected to ultrasonic cleaning to remove organic substances and metals.

Next, the N ^- substrates 10 and 20 are washed with pure water and spin-dried at room temperature.

Next, as shown in FIG. 4D, the upper surface 56 of the convex portion 54 of the N ⁻ substrate 10 between the concave portion 52 and the lower surface 24 of the N ⁻ substrate 20 are brought into contact with each other for about 800 ° C
By heating with N 2, N ⁻ substrate 10 and N ⁻ substrate 2
Join 0.

Next, the P ⁺ formed on the lower surface of the N ^- substrate 10
N ⁺ formed on the lower surface of the layer 12 and the upper surface of the N ⁻ substrate 20
An anode electrode 92 and a cathode electrode 94 are formed on the upper surface of the layer 22, respectively.

In the thus-formed electrostatic induction thyristor 100, the P ⁺ layer 12 is the anode, the N ⁺ layer 2
2 is a cathode, the N ⁻ substrate 10 and the N ⁻ substrate 20 both function as an N base 30, and the P ⁺ gate region 65 is
It functions as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94.

Also in this embodiment, the P ⁺ gate region 6
5 and the N base 30 in which the P ⁺ region 62 between the gate regions is buried is formed by joining the N ⁻ substrate 10 and the N ⁻ substrate 20, so that the N base 30 having uniform and high quality crystallinity can be obtained. . Further, since the P ⁺ region 26 is also formed on the lower surface 24 of the N ^- substrate 20, the electrical connection is further improved. Also, the gate region 6 of P ⁺
5 can be made high concentration, and the maximum breaking current can be increased.

In this embodiment, the gate region 6 of P ⁺
Between the gate regions 65 and P
⁺ Region 62 is provided, and P ⁺ region 26 is further provided on P ⁺ region 62 between gate regions. Accordingly, even when no bias is applied to the gate,
In particular, a depletion layer continuously extends between the side gate regions 64,
A normally-off type electrostatic induction thyristor 100 is formed.

(Fifth Embodiment) FIGS. 5 and 6 are sectional views for explaining a static induction thyristor and a method of manufacturing the same according to a fifth embodiment of the present invention.

First, as shown in FIGS. 5A and 5B,
In the same manner as in the second embodiment, N ^- a recess 52 and protrusions 54 on the upper surface 14 of substrate 10, N ^- substrate 10
P ⁺ layer 12 is formed on the lower surface of P ⁺ by impurity diffusion method, and P ⁺ side gate region 64 and bottom gate region 66 are formed in recess 5.
A P ⁺ region 62 between gate regions is formed in a region of the N ⁻ substrate 10 exposed on the side portion 51 and the bottom portion 53 of the second substrate 2, and in a region of the N ⁻ substrate 10 exposed on the upper surface 56 of the projection 54. P ⁺ bottom gate region 66, side gate region 64
The P ⁺ region 62 between the gate regions is formed continuously. P ⁺ side gate region 64 and bottom gate region 6
6 form a P ⁺ gate region 65.

Next, as shown in FIG.
The gate electrode film 72 made of tungsten having a thickness of
Formed over the entire upper surface 14 of the N ^- substrate 10 by the D method.

Next, as shown in FIG. 5D, the gate electrode film 72 is patterned by photolithography to form a gate electrode 74 having a width of about 25 μm to form a bottom gate region 66.
Above and in the recess 52.

[0095] On the other hand, as shown in FIG. 6A, N ^- substrate 20
N ⁺ layer 22 is formed on the upper surface of the substrate by an impurity diffusion method.

Next, sulfuric acid + hydrogen peroxide aqueous solution
The N ^- substrates 10 and 20 are subjected to ultrasonic cleaning to remove organic substances and metals.

Next, the N ^- substrates 10 and 20 are washed with pure water and spin-dried at room temperature.

Next, as shown in FIG. 6B, the upper surface 56 of the convex portion 54 of the N ^- substrate 10 between the concave portion 52 and the lower surface 24 of the N ^- substrate 20 are brought into contact with each other for about 800 ° C
The N ⁻ substrate 10 and the N ⁻ substrate 20
To join. When aluminum is used for the gate electrode 74, the bonding is performed at about 400 ° C.

Next, the P ⁺ formed on the lower surface of the N ^- substrate 10
N ⁺ formed on the lower surface of the layer 12 and the upper surface of the N ⁻ substrate 20
An anode electrode 92 and a cathode electrode 94 are formed on the upper surface of the layer 22, respectively.

In the electrostatic induction thyristor 100 formed as described above, the P ⁺ layer 12 is the anode, the N ⁺ layer 2
2 is a cathode, the N ⁻ substrate 10 and the N ⁻ substrate 20 both function as an N base 30, and the P ⁺ gate region 65 is
It functions as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94.

Also in this embodiment, the P ⁺ gate region 6
5 and the N base 30 in which the P ⁺ region 62 between the gate regions is buried is formed by joining the N ⁻ substrate 10 and the N ⁻ substrate 20, so that the N base 30 having uniform and high quality crystallinity can be obtained. . Further, it is possible to increase the concentration of the P ⁺ gate region 65, so that the maximum cutoff current can be increased.

Also in this embodiment, the P ⁺ gate region 6
Between the gate regions 65 and P
⁺ Region 62 is provided. Therefore, even when no bias is applied to the gate, the depletion layer continuously extends between the gate regions 65, particularly between the side gate regions 64, and the normally-off type static induction thyristor 100 is formed.

In this embodiment, since the gate electrode 74 made of tungsten is provided on the bottom gate region 66, the lateral resistance of the gate is reduced, so that the maximum cutoff current can be increased and the carrier can be extracted. The current can be increased and faster switching is possible.

The gate electrode 74 is made of N^-Substrate 10
And N^-Before bonding the substrate 20, N^-In the recess 52 of the substrate 10
The gate electrode 7
Even if 4 is provided, N⁺Layer 22 and
N^-A groove having a large aspect ratio is provided in the substrate 20, and the groove is formed.
It is no longer necessary to form the gate electrode 74 in
⁺Layer 22 and N^-Substrate 20 is finely divided by its groove
The resistance does not become high.

The recess 52 provided on the upper surface of the N ⁻ substrate 10 only needs to be able to accommodate the gate electrode 74.
The formation does not take too long.

Further, the gate electrode 74 is made of the N ⁻ substrate 10
Because it is housed in the concave portion 52 provided on the upper surface of the
N ^- N is bonded to the convex portion 54 of the upper surface of the substrate 10 ^- substrate 20
There is no need to provide a recess in the lower surface 24 of the
May be planar. Therefore, when the projection 54 on the upper surface of the N ^- substrate 10 and the lower surface 24 of the N ^- substrate 20 are joined, it is not necessary to perform special alignment, thereby facilitating manufacture.

(Sixth Embodiment) FIG. 7 is a sectional view for explaining an electrostatic induction thyristor and a method of manufacturing the same according to a sixth embodiment of the present invention.

First, as in the case of the fifth embodiment shown in FIGS. 5A to 5D, the concave portion 52 is formed on the upper surface 14 of the N ^- substrate 10.
P ⁺ layer 12 is formed on the lower surface of N ⁻ substrate 10 by an impurity diffusion method, and side gate region 64 and bottom gate region 66 of P ⁺ are formed on side portion 51 and bottom portion 53 of concave portion 52. each N is exposed ^- forming a gate region between the P ⁺ region 62 is a region of the substrate 10 ^- is formed in the region of the substrate 10, N exposed on the upper surface 56 of the protrusion 54. The P ⁺ bottom gate region 66, the side gate region 64, and the P ⁺ region 62 between the gate regions are formed continuously. P ⁺ side gate region 64 and bottom gate region 66 provide P ⁺
Of the gate region 65. Further, a gate electrode 74 made of tungsten is selectively formed on the bottom gate region 66 and in the recess 52.

[0109] On the other hand, as shown in FIG. 7A, N ^- substrate 20
An N ⁺ layer 22 is formed on the upper surface of the substrate by an impurity diffusion method, and a P ⁺ region 26 is formed on the entire lower surface 24 of the N ⁻ substrate 20 by an impurity diffusion method.

Next, sulfuric acid + hydrogen peroxide aqueous solution
The N ^- substrates 10 and 20 are subjected to ultrasonic cleaning to remove organic substances and metals.

Next, the N ^- substrates 10 and 20 are washed with pure water and spin-dried at room temperature.

Next, as shown in FIG. 7B, the upper surface 56 of the convex portion 54 of the N ^- substrate 10 between the concave portion 52 and the lower surface 24 of the N ^- substrate 20 are brought into contact with each other for about 800 hours in a hydrogen atmosphere. ° C
The N ⁻ substrate 10 and the N ⁻ substrate 20
To join.

Next, the P ⁺ formed on the lower surface of the N ^- substrate 10
N ⁺ formed on the lower surface of the layer 12 and the upper surface of the N ⁻ substrate 20
An anode electrode 92 and a cathode electrode 94 are formed on the upper surface of the layer 22, respectively.

In the thus formed electrostatic induction thyristor 100, the P ⁺ layer 12 is the anode, the N ⁺ layer 2
2 is a cathode, the N ⁻ substrate 10 and the N ⁻ substrate 20 both function as an N base 30, and the P ⁺ gate region 65 is
It functions as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94.

Also in this embodiment, the P ⁺ gate region 6
5 and the N base 30 in which the P ⁺ region 62 between the gate regions is buried is formed by joining the N ⁻ substrate 10 and the N ⁻ substrate 20, so that the N base 30 having uniform and high quality crystallinity can be obtained. . Further, since the P ⁺ region 26 is also formed on the lower surface 24 of the N ^- substrate 20, the electrical connection is further improved.

Also in this embodiment, the gate region 6 of P ⁺
Between the gate regions 65 and P
⁺ Region 62 is provided, and P ⁺ region 26 is further provided on P ⁺ region 62 between gate regions. Accordingly, even when no bias is applied to the gate,
In particular, a depletion layer continuously extends between the side gate regions 64,
A normally-off type electrostatic induction thyristor 100 is formed.

Also in this embodiment, since the gate electrode 74 made of tungsten is provided on the bottom gate region 66, the resistance in the lateral direction of the gate is reduced, the maximum cutoff current can be increased, and the carrier is extracted. The current can be increased and faster switching is possible.

In the fifth and sixth embodiments, the gate electrode 74 is formed of tungsten. However, other high melting point metal such as molybdenum or polycrystalline silicon doped with impurities such as boron is used. And aluminum or the like may be used.

[0119]

According to the semiconductor device of the present invention, a gate for controlling a current flowing between an anode electrode and a cathode electrode is provided in a semiconductor substrate provided between an anode electrode and a cathode electrode. In a semiconductor device, a cavity is provided in a semiconductor substrate, and a gate region made of a semiconductor is provided in a region exposed on a side portion of the cavity of the semiconductor substrate, so that a withstand voltage in an off state can be increased and a leakage current can be reduced. It can be made smaller, has excellent breaking ability, and can control a large current. Further, a predetermined off characteristic can be obtained without reducing the interval between the gate regions, and it is not necessary to reduce the interval between the cavities of the semiconductor substrate. As a result, it is possible to improve the yield when the cavity is finely processed in the semiconductor substrate. Further, since it is not necessary to reduce the interval between the cavities, the cross-sectional area of the semiconductor substrate between the cavities is suppressed from being reduced, and the resistance of the semiconductor substrate between the cavities is reduced. Current can be achieved.

Further, by providing a semiconductor region of the same conductivity type as the gate region between the gate regions so that the depletion layer continuously spreads between the gate regions when no bias is applied to the gate, a normally-off type is provided. Is obtained.

By providing this semiconductor region continuously with the gate region, the depletion layer can be more surely continuously extended between the gate regions in a state where no bias is applied to the gate.

Further, by providing the side of the cavity almost parallel to the direction of the current flowing between the anode electrode and the cathode electrode, the withstand voltage at the time of off can be further increased, and the leakage current can be reduced. And a semiconductor device which is more excellent in the breaking ability can be obtained. Further, the space between the cavities of the semiconductor substrate can be made wider, and as a result, the yield when microfabricating the cavities in the semiconductor substrate can be further improved. Further, the cross-sectional area of the semiconductor substrate between the cavities can be made wider, and the resistance of the semiconductor substrate between the cavities can be made smaller. As a result, the on-voltage can be further reduced and the current can be further increased.

Further, by providing the gate region also in the region exposed at the bottom of the cavity of the semiconductor substrate, the resistance in the lateral direction of the gate is reduced, so that the maximum breaking current can be increased and the frequency can be increased.

Further, by further providing a gate electrode made of a good conductor electrically connected to the gate region in the cavity of the semiconductor substrate, the resistance in the lateral direction of the gate is reduced and the maximum breaking current can be increased. Carrier extraction current can be increased, and higher-speed switching becomes possible.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a static induction thyristor and a method of manufacturing the same according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a static induction thyristor and a method of manufacturing the same according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a static induction thyristor and a method of manufacturing the same according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a static induction thyristor and a method of manufacturing the same according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a static induction thyristor according to fifth and sixth embodiments of the present invention and a method of manufacturing the same.

FIG. 6 is a sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a fifth embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a static induction thyristor and a method of manufacturing the same according to a sixth embodiment of the present invention.

FIG. 8 is a perspective sectional view for explaining a conventional electrostatic induction thyristor and a method for manufacturing the same.

FIG. 9 is a perspective sectional view illustrating a conventional electrostatic induction thyristor and a method for manufacturing the same.

FIG. 10 is a perspective sectional view for explaining a conventional electrostatic induction thyristor and a method for manufacturing the same.

FIG. 11 is a perspective sectional view for explaining a conventional normally-off type electrostatic induction thyristor and a method of manufacturing the same.

FIG. 12 is a perspective sectional view for explaining a conventional normally-off type electrostatic induction thyristor and a method for manufacturing the same.

FIG. 13 is a perspective sectional view for explaining a conventional normally-off type electrostatic induction thyristor and a method for manufacturing the same.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... N ^- substrate 12 ... P ⁺ layer 14 ... Top surface 20 ... N ^- substrate 22 ... N ⁺ layer 24 ... Bottom surface 26 ... P ⁺ region 30 ... N base 42 ... P ⁺ gate region 44 ... P ⁺ region 46 ... Gate Inter-region P ⁺ region 51 ... side portion 52 ... concave portion 53 ... bottom portion 54 ... convex portion 56 ... top surface 60 ... P ⁺ region 62 ... gate region P ⁺ region 64 ... side gate region 65 ... gate region 66 ... bottom gate region 72 gate electrode film 74 gate electrode 92 anode electrode 94 cathode electrode 100 electrostatic induction thyristor

Claims (6)

[Claims] A semiconductor device provided between an anode electrode and a cathode electrode, wherein a gate for controlling a current flowing between the anode electrode and the cathode electrode is provided in the semiconductor device; A cavity is provided therein, a gate region made of a semiconductor is provided in a region exposed on a side portion of the cavity of the semiconductor substrate, and a depletion layer is continuously formed between the gate regions in a state where no bias is applied to the gate. A semiconductor device, wherein a semiconductor region of the same conductivity type as the gate region is provided in the semiconductor substrate between the gate regions so as to spread. 2. The semiconductor device according to claim 1, wherein said semiconductor region is provided continuously with said gate region. 3. The semiconductor device according to claim 1, wherein a side portion of the cavity is provided substantially parallel to a direction of the current flowing between the anode electrode and the cathode electrode. 4. The semiconductor device according to claim 1, wherein a gate region is provided also in a region of said semiconductor substrate exposed at a bottom of said cavity. 5. The semiconductor device according to claim 1, wherein a gate electrode made of a good conductor electrically connected to the gate region is further provided in the cavity of the semiconductor substrate. Semiconductor device. 6. A semiconductor substrate comprising: a first semiconductor layer of one conductivity type; a second semiconductor layer of another conductivity type provided on the first semiconductor layer; and the second semiconductor layer. And a third semiconductor layer of another conductivity type having a higher impurity concentration than the second semiconductor layer, wherein one of the anode electrode and the cathode electrode is electrically connected to the first semiconductor layer. The other of the anode electrode and the cathode electrode is provided so as to be electrically connected to the third semiconductor layer, and the gate region and the semiconductor region are the one conductivity type semiconductor. 6. The semiconductor device according to claim 1, wherein the cavity, the gate region, and the semiconductor region are provided in the second semiconductor layer.