JP2002124631A - Semiconductor integrated circuit and surge-protecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To incorporate an inductance component in a bonding wire used at package mounting time in a semiconductor integrated circuit. SOLUTION: A capacitance 27, for executing a series resonance with an inductance component of a bonding wire 25 for connecting a GND pad 26 of a semiconductor integrated circuit chip side to an external grounding element, is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit operating at a high frequency and a surge protection circuit applied to the semiconductor integrated circuit.

[0002]

2. Description of the Related Art A general semiconductor integrated circuit is designed so that the potential of a substrate surface immediately adjacent or immediately below an element constituting a transistor circuit or the like is maintained at a reference potential of the circuit. Wire is used. FIGS. 7A and 7B are a mounting diagram and a circuit diagram showing a conventional example in which the ground of a semiconductor integrated circuit is contacted with the bonding wire, for example. Here, 23 is a semiconductor integrated circuit, 25 is a bonding wire, 26 is a GND pad, 28 is a ground point, 29
Is an inductor by a bonding wire, 30 is N
A PN transistor, 31 represents a signal source, and 46 represents a ground plane. Conventionally, the inductance component is reduced by using two or more bonding wires as shown in FIG. 8A, or the bonding wire to the ground is shortened as much as possible by using a ground post as shown in FIG. 8B. Was taking the way.

Further, in a normal semiconductor integrated circuit, in order to prevent destruction of an internal circuit due to a surge caused by external static electricity or the like, a protection diode is formed to release positive and negative surges to a power supply and a ground portion, respectively. A surge protection circuit is formed. FIG. 9 is a circuit diagram showing a conventional example of a surge protection circuit in a semiconductor integrated circuit. Here, 42 is a part of the semiconductor integrated circuit, 43 is a surge protection diode, and 44 is a power supply.

[0004]

However, when the semiconductor integrated circuit is used at a high frequency, bonding
There has been a problem that the inductance component of the wire becomes high impedance in a high frequency range, which leads to high frequency characteristics at a desired frequency.

That is, there is a problem (first problem) that when a semiconductor integrated circuit is used at a high frequency, an inductance component of a bonding wire causes high frequency characteristics.

In the surge protection circuit of the semiconductor integrated circuit, the stray capacitance of the surge protection diode and the resonance of the inductance component due to the bonding wire for the external connection feed back to the circuit, and a high frequency such as a stability coefficient and a gain is obtained. There is a problem that characteristics are deteriorated.

That is, in the surge protection circuit of the semiconductor integrated circuit, the problem that the high frequency characteristics such as the stability coefficient and the gain are deteriorated by the resonance of the stray capacitance of the surge protection diode and the inductance component due to the bonding wire for external connection ( There is a second problem).

An object of the present invention is to provide a semiconductor integrated circuit in which an inductance component of a bonding wire does not cause a high frequency characteristic even when used at a high frequency in consideration of the first problem.

Further, in consideration of the second problem, the present invention does not deteriorate the high frequency characteristics such as the stability coefficient and the gain due to the resonance of the inductance component due to the stray capacitance of the surge protection diode and the bonding wire for external connection. It is an object of the present invention to provide a surge protection circuit.

[0010]

In order to solve the above-mentioned problems, a first aspect of the present invention (corresponding to claim 1) is to provide a circuit including a semiconductor element and a reference potential of the circuit connected to the circuit. And a capacitance that causes series resonance with an inductance component of a lead terminal connecting the grounding electrode and an external grounding body, wherein the capacitance is a resonance frequency of the series resonance. , Wherein the impedance between the grounding electrode and the external grounding body is substantially zero.

Further, the second invention (corresponding to claim 2)
The semiconductor integrated circuit according to the first aspect, wherein the circuit is a circuit of a front end portion of a wireless communication circuit, and the capacitance is formed by a metal plate.

Further, a third aspect of the present invention (corresponding to claim 3)
Is a semiconductor integrated circuit according to the first or second aspect of the present invention, further comprising a substrate having the circuit formed on a surface thereof, wherein the capacitance is formed inside the substrate.

Further, the fourth invention (corresponding to claim 4)
Is a semiconductor integrated circuit according to the first or second aspect of the present invention, wherein the capacitance is formed in the circuit.

Further, the fifth invention (corresponding to claim 5)
In the semiconductor integrated circuit according to a fourth aspect of the present invention, the circuit has a plurality of wiring layers, and the capacitance is formed by all or a part of the plurality of wiring layers. is there.

Further, a sixth aspect of the present invention (corresponding to claim 6)
Wherein the plurality of wiring layers are a first wiring layer connected to the ground electrode, and a second wiring layer on which a lead wiring to the ground electrode is formed. An interlayer film is formed between the wiring layer and the second wiring layer, and the capacitance is formed by the first wiring layer and the second wiring layer using the lead wiring. A fifth aspect of the present invention is a semiconductor integrated circuit according to the fifth aspect.

A seventh aspect of the present invention (corresponding to claim 7)
The circuit has a wiring layer connected to the ground electrode and formed with a lead wire to the ground electrode, and the capacitance is formed by the wiring layer using the lead wire A semiconductor integrated circuit according to a fourth aspect of the present invention, wherein:

Further, an eighth aspect of the present invention (corresponding to claim 8)
The semiconductor integrated circuit according to any one of the fourth to seventh aspects of the present invention, wherein the capacitance is formed by an MIM structure.

A ninth aspect of the present invention (corresponding to claim 9).
The semiconductor integrated circuit according to any one of the fourth to seventh aspects of the present invention, wherein the capacitance is formed by an interdigital structure.

According to a tenth aspect of the present invention (corresponding to claim 10), the circuit has a lead-out wiring for grounding which is drawn out to the grounding electrode, and the capacitance is equal to that of the grounding electrode. A semiconductor integrated circuit according to a third aspect of the present invention, wherein the semiconductor integrated circuit is formed by a lead wiring.

According to an eleventh aspect of the present invention (corresponding to claim 11), there is provided a semiconductor integrated circuit comprising: a circuit between an input circuit of a predetermined transistor circuit and a power supply; A surge protection diode provided between the output circuit of the transistor and the power supply unit, and between the output circuit and the ground unit, and a path between the input circuit and the output circuit in a high frequency range. And a passive element for increasing the impedance of a path passing through the surge protection diode.

According to a twelfth aspect of the present invention (corresponding to claim 12), the passive element is a capacitance and an inductance, and the passive element includes a floating capacitance component of the diode for surge protection and the surge element. An eleventh aspect of the present invention is characterized in that the protection diode is arranged so as to cause parallel resonance between the protection diode and an inductance component of an external connection lead terminal for connecting the grounding portion and the power supply portion, respectively. The surge protection circuit according to the above.

According to a thirteenth aspect of the present invention (corresponding to claim 13), the passive element is an inductance, and the passive element includes a stray capacitance component of the surge protection diode, the grounding portion, and the ground. An surge protection circuit according to an eleventh aspect of the present invention, wherein the surge protection circuit is arranged so as to suppress series resonance with an inductance component of an external connection lead terminal for connecting to a power supply unit.

According to a fourteenth aspect of the present invention (corresponding to claim 14), the passive element is a resistor, and the passive element includes a floating capacitance component of the surge protection diode, the grounding portion, and the ground. An surge protection circuit according to an eleventh aspect of the present invention, wherein the surge protection circuit is arranged so as to attenuate series resonance with an inductance component of an external connection lead terminal for connecting to a power supply unit.

For example, according to the present invention, a semiconductor integrated circuit provided on a semiconductor substrate has a structure in which a plurality of grounding electrodes are connected to an external grounding body via external connection lead terminals. Between the chip-side ground electrode and a lead terminal for connecting to the external grounding body, an inductance component of the lead terminal for connecting to the grounding body and a capacitance that causes series resonance at a desired frequency. And the impedance between the grounding electrode on the chip side and the external grounding body is substantially zero at the resonance frequency.

The present invention also provides a surge protection circuit between a power supply and a grounding portion of a transistor circuit of a semiconductor integrated circuit, wherein a surge protection diode between a power supply and a grounding portion is provided between an input circuit and an output circuit of the transistor circuit. And a passive element for increasing the impedance between the surge protection diode and the input circuit and the output circuit of the transistor circuit in a low frequency range and a high frequency range.

According to the present invention, the surge protection circuit resonates the inductor component of the external connection lead terminal and the capacitance component of the metal plate formed between the ground electrode and the external grounding body at a desired frequency. In the above, the impedance between the surge protection diode and the input circuit and the output circuit of the transistor circuit is made high to suppress the feedback, whereby the effect of improving the deterioration of the high frequency characteristics is obtained.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1A and 1B
2 shows a configuration of a receiving unit of a wireless communication circuit and a receiving front-end unit of the wireless communication circuit according to the first embodiment.

In FIG. 1A, reference numeral 11 denotes an antenna,
2 is a laminated RF filter, 13 is a switch, 14 is an IF filter, 15 is an LNA, 16 is an interstage laminated RF filter,
17 is a VCO, 18 is a MIXER, 19 is a demodulator, 20
Is a baseband LSI, 21 is a reception front end unit,
Reference numeral 22 denotes a receiving unit of the wireless communication circuit.

FIG. 1B shows the LNA 15 and the interstage laminated RF filter 16 of the reception front end 21 shown in FIG.
23 is a semiconductor integrated circuit in which the LNA 15, the MIXER 18 and the like are integrated into an IC, 24 is a laminated substrate on which the inter-stage laminated RF filter 16 and the like are formed, 25 is a bonding wire, and 26 is an external part of the semiconductor integrated circuit. A GND pad for connection, 27 is a capacitance formed in the laminated substrate, and 28 is a ground point.

FIG. 2 shows an example of an equivalent circuit diagram when a capacitor which causes series resonance with the inductance component generated by the bonding wire 25 as shown in FIG. 1B is formed in the laminated substrate.

In FIG. 1B, the semiconductor integrated circuit 23 is provided above the laminated substrate 24. The capacitance 27 is formed in the laminated substrate 24 by a metal plate or the like. The capacitance 27 is configured to cause series resonance with an inductance component generated by the bonding wire 25.
With this configuration, it is possible to improve deterioration of high frequency characteristics.

The GND pad 26 of the present embodiment is an example of the ground electrode of the present invention, and the semiconductor integrated circuit 23 of the present embodiment is an example of the circuit of the present invention. The substrate is an example of the substrate of the present invention, and the bonding wire 25 of the present embodiment is an example of the lead terminal of the present invention.

Further, the number of grounding electrodes of the present invention is not limited to one as in the GNP pad 26 in the present embodiment, but is two or three. In short, the number of grounding electrodes of the present invention is: It only needs to be one or more arbitrary numbers.

Further, the GNP pad 26 of the present embodiment
Are formed, a bonding wire 25 is connected to each GNP pad 26, and each is grounded to a ground point 28. In this case, the grounding point 28 may be the same point on the grounding body, or may be a plurality of points on the grounding body. Alternatively, the bonding wire 25 may be grounded inside the laminated substrate and then grounded to the grounding point 28. In this case, one capacitance may be formed with respect to the plurality of concentrated bonding wires 25. Then, this capacitance causes series resonance together with the impedance components of the plurality of bonding wires 25 that are converged. Also,
If the bonding wire 25 is not concentrated,
The capacitance which causes series resonance with the impedance component of the bonding wire 25 connecting each GNP pad 26 and the ground point 28 is set to the bonding wire 2.
One may be formed for every five.

Further, the semiconductor integrated circuit of the present invention is not limited to the one constituting the front end section 21 of the receiving section 22 of the wireless communication circuit in the present embodiment, and all or a part of the transmitting section of the wireless communication circuit may be used. In short, the semiconductor integrated circuit of the present invention, such as a component, may be used in any application as long as the impedance component of the lead terminal cannot be ignored.

As described above, according to the present embodiment, deterioration of high frequency characteristics is improved by forming a capacitance in the laminated substrate that causes series resonance with the inductor component generated by the bonding wire.

Since the capacitor capacitance is formed in the laminated substrate, a desired capacitance value is easily obtained.
Further, the effect of improving the degree of chip integration by arranging the semiconductor integrated circuit on the laminated substrate can be obtained.

(Embodiment 2) FIGS. 3A and 3B are partial cross-sectional views showing the inside of a semiconductor integrated circuit IC according to a second embodiment. 3A and 3B, 32 is a capacitance forming portion, 33 is a first wiring layer, 34 is a ground wiring, 35 is a second wiring layer, 36 is an interlayer film, and 37 is a drawing to a ground pad. Reference numeral 38 denotes a portion inside the semiconductor integrated circuit IC, and 48 denotes a contact portion.

The capacitance forming section 32 shown in FIG.
FIG. 1 shows the first embodiment in the first wiring layer and the second wiring layer using the ground lead wiring 34.
It is formed so as to cause a series resonance at a desired frequency with the inductance component generated by the bonding wire 25 of (b). With such a configuration, it is possible to improve the deterioration of the high frequency characteristics.

The capacitance forming portion 32 shown in FIG.
Is designed to cause series resonance at a desired frequency with an inductance component generated by the bonding wire 25 shown in FIG. 1B representing the first embodiment by the second wiring layer using the ground extraction wiring 34. And has an MIM structure. With this configuration, it is possible to improve deterioration of high frequency characteristics.

In FIG. 3A, it is described that the capacitance is formed by the first wiring layer 33 and the second wiring layer 35 by using the ground wiring 34. However, the present invention is not limited to this. When the semiconductor integrated circuit is composed of three or more wiring layers, the capacitance may be formed by all or a part of the plurality of wiring layers.

Further, the number of the grounding electrodes of the present invention is not limited to one like the contact portion 48 and the outlet 37 to the ground pad in the present embodiment, but is two or three. The number of the grounding electrodes may be one or more arbitrary numbers.

Further, the contact portion 48 of the present embodiment
When a plurality of outlets 37 to the ground pad are formed, corresponding to the contact portions 48 and the outlets 37 to the ground pad, respectively, are shown in FIG. 3A or FIG. 3B. Such a capacitance forming unit 32
May be provided.

Further, the first wiring layer 33 and the second wiring layer 35 of the present embodiment are examples of the circuit of the present invention, and the contact portion 48 and the outlet 37 to the ground pad of the present embodiment are the same as those of the present invention. The second wiring layer 35 of the present embodiment is an example of the circuit of the present invention.

As described above, according to the present embodiment, the capacitance that causes series resonance with the inductance component generated by the bonding wire 25 is integrated inside the semiconductor integrated circuit IC by using the ground lead-out wiring 34. First wiring layer 33 and second wiring layer 3 of circuit IC
By being formed in parallel with the semiconductor substrate of the semiconductor integrated circuit by 5, the deterioration of the high frequency characteristics is improved.

Further, such a semiconductor integrated circuit IC is
It can be formed by a conventional process, and the effect that the chip area is not different from the conventional one can be obtained because the ground extraction wiring 34 is used for capacitance.

Further, a capacitor is formed by a single layer of the ground lead-out wiring 34 in a direction perpendicular to the semiconductor substrate of the semiconductor integrated circuit and in series with the inductance component generated by the bonding wire 25, so that high-frequency operation is achieved. Deterioration of characteristics is improved.

Further, such a semiconductor integrated circuit IC is
It can be formed by a conventional process, and since the ground lead-out wiring 34 is used for a capacitor closet, the effect that the chip area is not different from the conventional one can be obtained.

(Embodiment 3) FIGS. 4A and 4B are partial cross-sectional views showing the inside of a semiconductor integrated circuit IC according to a third embodiment. 4A and 4B, reference numeral 39 denotes an interdigital capacitor forming section.

The interdigital capacitance forming section 39 shown in FIG. 4A uses the ground lead-out wiring 34 in the first wiring layer and the second wiring layer in the first wiring layer shown in FIG. It is formed of an interdigital type so as to cause series resonance at a desired frequency with the inductance component generated by the bonding wire 25 of b). With such a configuration, it is possible to improve deterioration of high frequency characteristics.

The interdigital capacitance forming section 39 of FIG. 4B uses the ground wiring 34 and a second wiring layer to form the first embodiment of FIG.
It is formed of an interdigital type so as to cause a series resonance at a desired frequency with an inductor component generated by the bonding wire 25 of (b). With such a configuration, it is possible to improve deterioration of high frequency characteristics.

In FIG. 4A, the capacitance is formed between the first wiring layer and the second wiring layer by using the ground lead wiring. However, the present invention is not limited to this. When the semiconductor integrated circuit is composed of three or more wiring layers, the capacitance may be formed by all or a part of the plurality of wiring layers.

Further, the number of the grounding electrodes of the present invention is not limited to one like the contact part 48 and the outlet 37 to the ground pad in the present embodiment, but is two or three. The number of the grounding electrodes may be one or more arbitrary numbers.

Further, the contact portion 48 according to the present embodiment.
When a plurality of outlets 37 to the ground pad are formed, corresponding to the respective contact portions 48 and the outlets 37 to the ground pad, as shown in FIG. 4A or FIG. 4B, respectively. Such a capacitance forming unit 32
May be provided.

Further, the first wiring layer 33 and the second wiring layer 35 of the present embodiment are examples of the circuit of the present invention, and the contact portion 48 and the outlet 37 to the ground pad of the present embodiment are the same as those of the present invention. The second wiring layer 35 of the present embodiment is an example of the circuit of the present invention.

As described above, according to the present embodiment, the capacitance which causes the series resonance with the inductance component generated by the bonding wire is used inside the semiconductor integrated circuit IC by utilizing the ground lead-out wiring. By forming the first wiring layer and the second wiring layer in parallel with the semiconductor substrate of the semiconductor integrated circuit, deterioration of high-frequency characteristics is improved.

Further, such a semiconductor integrated circuit IC is
It can be formed by a conventional process, and the effect that the chip area is not different from the conventional one can be obtained because the ground extraction wiring 34 is used for capacitance.

Further, a capacitor which causes series resonance with the inductance component generated by the bonding wire 25 in a direction perpendicular to the semiconductor substrate of the semiconductor integrated circuit is formed by a single layer of the grounding lead wiring, so that high-frequency characteristics are obtained. Is improved.

Further, such a semiconductor integrated circuit IC is
It can be formed by a conventional process, and the effect that the chip area is not different from the conventional one can be obtained since the grounding lead wiring is used for the capacitor closet.

(Embodiment 4) FIGS. 5A and 5B show a semiconductor integrated circuit IC according to a fourth embodiment and a part of a cross-sectional view inside the semiconductor integrated circuit IC. In FIG.
Reference numeral 40 denotes a part of a cross-sectional view of the semiconductor integrated circuit.

The capacitance forming section 32 shown in FIG. 5 uses the ground lead 34 and the GND pad to
It is formed so as to cause series resonance at a desired frequency with an inductor component generated by the bonding wire 25 according to the embodiment of the present invention, and by adopting such a configuration, it is possible to realize improvement of deterioration of high frequency characteristics.

The GND pad of the present embodiment is an example of the ground electrode of the present invention.

Further, the number of grounding electrodes of the present invention is not limited to six like the GND pad in the present embodiment, but one, two, seven, twelve, etc. The number of electrodes need only be one or more arbitrary numbers.

As described above, according to the present embodiment, the inductance component generated by the bonding wire 25 and the capacitance that causes series resonance at a desired frequency are formed by the grounding lead wire 34 and the GND pad. Deterioration of high frequency characteristics is improved.

Further, such a semiconductor integrated circuit IC is
Since it can be formed by a conventional process, the ground area 34 is used for the capacitance, the chip area is not different from the conventional one. Further, since the capacitance can be formed by the number of GND pads, the desired capacitance value can be reduced. The effect of being obtained is obtained.

(Embodiment 5) FIGS. 6 (a), (b),
(C) shows a part of the semiconductor integrated circuit according to the fifth embodiment. 6A, 6B and 6C, reference numeral 41 denotes an inductance, and 45 denotes a resistance.

According to FIG. 6A, the surge protection circuit 43
Between the input and output of the transistor circuit, which is a part 42 of the semiconductor integrated circuit, the capacitance 27 and the inductance 41 that resonate in parallel so that the impedance between the surge protection diode 43 and the input circuit and the output circuit increases. Are located.

That is, in the high frequency range, the path between the input circuit and the output circuit, that is, the path through the surge protection diode 43 is arranged to have a high impedance.

Therefore, the capacitor 27 and the inductance 41 suppress feedback due to series resonance between the stray capacitance of the surge protection diode and the inductance component of the bonding wire 25 of FIG. 1B of the first embodiment. I do. With such a circuit configuration, deterioration of high-frequency characteristics such as a stability coefficient and a maximum available power gain can be improved.

According to FIG. 6B, the surge protection circuit 43
Between the input and output of the transistor circuit which is a part 42 of the semiconductor integrated circuit, there is formed an inductance 41 for increasing the impedance between the surge protection diode 43 and the input and output circuits.

That is, in a high-frequency range, a path between the input circuit and the output circuit, which passes through the surge protection diode 43, is arranged to have a high impedance.

Therefore, the inductance 41 suppresses feedback due to series resonance between the stray capacitance of the surge protection diode and the inductance component of the bonding wire 25 of FIG. 1B according to the first embodiment. With such a circuit configuration, it is possible to improve deterioration of high-frequency characteristics such as a stability coefficient and a maximum available power gain.

According to FIG. 6C, the surge protection circuit 43
A resistor 45 is formed between the input and output of the transistor circuit which is a part 42 of the semiconductor integrated circuit. That is, in the high frequency range, the impedance is arranged such that the impedance of the path between the input circuit and the output circuit, which passes through the surge protection diode, is high.

Accordingly, the resistor 45 is provided between the stray capacitance of the surge protection diode and the first embodiment shown in FIG.
(B) Attenuation of feedback due to series resonance with an inductance component due to the bonding wire.

By adopting such a circuit configuration, it is possible to improve deterioration of high-frequency characteristics such as a stability coefficient and a maximum available power gain.

As described above, according to the present embodiment, the parallel resonance between the surge protection diode and the input and output circuits is performed between the input and output of the surge protection circuit and the transistor circuit which is a part of the semiconductor integrated circuit. By inserting a capacitor and an inductor as described above, a high impedance between the surge protection diode and the input circuit and the output circuit is realized, and the feedback of the transistor circuit is suppressed. With such a configuration, deterioration of high frequency characteristics such as a stability coefficient and a maximum available power gain is improved.

Further, by inserting an inductance such that the impedance between the surge protection diode and the input circuit and the output circuit is increased between the input and output of the surge protection circuit and the transistor circuit which is a part of the semiconductor integrated circuit. , Suppressing the feedback of the transistor circuit. With such a configuration, deterioration of high-frequency characteristics such as a stability coefficient and a maximum available power gain is improved with a small number of elements, so that an effect that a surge protection circuit can be easily formed can be obtained.

Further, a resistor is inserted between the surge protection circuit and the transistor circuit which is a part of the semiconductor integrated circuit so that the impedance between the surge protection diode and the input circuit and the output circuit becomes high. Thereby, the feedback of the transistor circuit is attenuated and suppressed. With such a configuration, the stability coefficient,
Since the deterioration of the high-frequency characteristics such as the maximum available power gain can be improved with a small number of elements, the effect that the IC can be easily realized is obtained.

[0080]

As is clear from the above description. The present invention can provide a semiconductor integrated circuit in which an inductance component of a bonding wire does not cause high-frequency characteristics even when used at a high frequency.

Further, the present invention can provide a surge protection circuit in which high frequency characteristics such as a stability coefficient and a gain are not deteriorated by resonance of a stray capacitance of a surge protection diode and an inductance component due to a bonding wire for external connection. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a reception unit of a wireless communication circuit and a reception front-end unit of the wireless communication circuit according to a first embodiment.

FIG. 2 is a configuration diagram of a part of a semiconductor integrated circuit according to a second embodiment;

FIG. 3 is a sectional view of a part of the inside of a semiconductor integrated circuit IC showing a third embodiment;

FIG. 4 is a sectional view of a part of the inside of a semiconductor integrated circuit IC showing a fourth embodiment;

FIG. 5 is a sectional view of a semiconductor integrated circuit IC according to a fifth embodiment;

FIG. 6 is a configuration diagram of a part of a semiconductor integrated circuit according to a sixth embodiment;

FIG. 7 is a bird's-eye view of a pad-ground bonding method of a semiconductor integrated circuit according to the related art.

FIG. 8 is a diagram showing a method for reducing the inductance component of a bonding wire according to the related art.

FIG. 9 shows a surge protection circuit for a semiconductor integrated circuit according to the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 antenna 12 multilayer RF filter 13 switch 14 IF filter 15 LNA 16 interstage multilayer RF filter 17 VCO 18 MIXER 19 demodulator 20 baseband LSI 21 reception front end unit 22 reception unit of wireless communication circuit 23 semiconductor integrated circuit 24 multilayer substrate 25 Bonding wire 26 Inside of laminated substrate 27 Capacitance 28 Grounding point 29 Inductor by bonding wire 30 NPN transistor 31 Signal source 32 Capacitance forming part 33 First wiring layer 34 Ground wiring 35 Second wiring layer 36 Interlayer film 37 Ground pad 38 Internal of semiconductor integrated circuit IC 39 Interdigital capacitance forming section 40 Part of sectional view of semiconductor integrated circuit 41 Inductor 42 Semiconductor integrated circuit Some 43 surge protection diode 44 power source 45 resistor 46 ground plane 47 ground post 48 contacts portion

Continued on the front page (72) Inventor Toshiaki Ando 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. ) 5F038 AZ05 BH03 BH04 BH11 BH13 EZ20

Claims (14)

[Claims] 1. A circuit including a semiconductor element, a ground electrode connected to the circuit for maintaining a reference potential of the circuit, and a lead terminal connected to the ground electrode and an external grounding body. A capacitance that causes series resonance with the component, wherein the capacitance is configured such that at the resonance frequency of the series resonance, the impedance between the grounding electrode and the external grounding body is substantially zero. A semiconductor integrated circuit characterized by: 2. The semiconductor integrated circuit according to claim 1, wherein said circuit is a circuit of a front end portion of a wireless communication circuit, and said capacitance is formed by a metal plate. 3. The semiconductor integrated circuit according to claim 1, further comprising a substrate having a surface on which the circuit is formed, wherein the capacitance is formed inside the substrate. 4. The semiconductor integrated circuit according to claim 1, wherein said capacitance is formed in said circuit. 5. The semiconductor integrated circuit according to claim 4, wherein the circuit has a plurality of wiring layers, and the capacitance is formed by all or a part of the plurality of wiring layers. 6. The plurality of wiring layers, a first wiring layer connected to the grounding electrode, and a second wiring layer formed with a lead-out wiring to the grounding electrode.
An interlayer film is formed between the first wiring layer and the second wiring layer, and the capacitance is determined by using the lead-out wiring. 6. The semiconductor integrated circuit according to claim 5, wherein said semiconductor integrated circuit is formed by said first wiring layer and said second wiring layer. 7. The circuit has a wiring layer connected to the grounding electrode and formed with a lead-out wiring to the grounding electrode, and the capacitance is obtained by using the lead-out wiring. The semiconductor integrated circuit according to claim 4, wherein the semiconductor integrated circuit is formed of a layer. 8. The semiconductor integrated circuit according to claim 4, wherein said capacitance is formed by an MIM structure. 9. The semiconductor integrated circuit according to claim 4, wherein said capacitance is formed by an interdigital structure. 10. The circuit according to claim 1, wherein the circuit has a lead wire for grounding, which is drawn to the ground electrode, and the capacitance is formed by the ground electrode and the lead wire. Item 4. A semiconductor integrated circuit according to item 3. 11. A power supply section between an input circuit of a predetermined transistor circuit and a power supply section, a power supply section between the input circuit and a ground section, an output circuit of the transistor and a power supply section, and A surge protection diode provided between the output circuit and the grounding unit; and a high-frequency path having a high impedance between a path between the input circuit and the output circuit and a path passing through the surge protection diode. A surge protection circuit comprising: a passive element. 12. The passive element is a capacitance and an inductance, and the passive element includes a stray capacitance component of the surge protection diode, the surge protection diode, the ground unit, and the power supply unit. 12. The surge protection circuit according to claim 11, wherein the surge protection circuit is arranged so as to cause parallel resonance with an inductance component of an external connection lead terminal for connection. 13. The passive element is an inductance, and the passive element is an external connection lead terminal for connecting a stray capacitance component of the surge protection diode to the ground section and the power supply section, respectively. 12. The surge protection circuit according to claim 11, wherein the surge protection circuit is arranged so as to suppress series resonance with the inductance component of (1). 14. The passive element is a resistor, and the passive element is an external connection lead terminal for connecting a stray capacitance component of the surge protection diode to the grounding section and the power supply section. 12. The surge protection circuit according to claim 11, wherein the surge protection circuit is arranged to attenuate a series resonance with the inductance component of (1).