JP2002118146A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in the form of a chip size package which can reliably connect a semiconductor chip and an interposer substrate with a high reliability. SOLUTION: In connection between a semiconductor chip 10 having an electrode 11 and an interposer substrate 12, an anisotropic conductive film 13 wherein resin particles 22 are disposed is disposed between the chip and substrate and heated to form a junction thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a semiconductor chip is mounted on an interposer substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art A chip size package has been used as a package in which a semiconductor package constituting a semiconductor device is miniaturized and lightened to the utmost. In such a chip size package, a semiconductor element (chip) is mounted on an interposer substrate that is slightly larger than the semiconductor element. In such a chip size package, the electrodes of the semiconductor chip are connected to the electrodes on the interposer substrate by flip-chip connection. Then, a resin is sealed and sealed in a gap between the semiconductor chip and the interposer substrate.

[0003]

Such a conventional chip size package has a strong structure due to an adhesive filled between the semiconductor chip and the interposer substrate, but has a structure that does not easily absorb stress. Therefore, when a semiconductor device including such a chip size package is mounted on a motherboard, a difference in thermal expansion between the chip size package and the motherboard may damage solder connection bumps and the like connecting the semiconductor device to the motherboard. And leave a problem for reliability.

In the chip size package as described above, since the electrodes of the semiconductor chip and the electrodes of the interposer substrate are flip-chip connected, they must be correctly aligned, thereby providing highly accurate positioning. Need. In addition, if a resin is sealed between the semiconductor chip and the interposer substrate, it takes a long time for the process, which causes a problem that productivity is reduced.

The present invention has been made in view of the above problems, and provides a semiconductor device which can easily absorb stress when mounted on a motherboard and has excellent productivity, and a method of manufacturing the same. The purpose is to do.

[0006]

A main invention relating to a semiconductor device has a semiconductor chip provided with a predetermined circuit and having electrodes provided on an outer surface thereof, and an interposer substrate on which the semiconductor chip is mounted. The semiconductor element and the interposer substrate are joined to each other via an anisotropic conductive layer, and the electrode of the semiconductor element and the electrode of the interposer substrate are connected to each other by the anisotropic conductive layer. The present invention relates to a semiconductor device characterized by the above.

Here, an insulating resin layer having a wiring layer may be formed on a surface of the interposer substrate opposite to a surface on which the semiconductor chip is mounted. Further, an insulating resin layer having a wiring layer may be formed by laminating a plurality of layers.
Such an insulating resin layer is preferably made of a material having a low elastic coefficient. Further, external connection electrodes are formed on the outer surface of the outermost insulating resin layer, and mounted on the motherboard using such external connection electrodes. It is preferable to use a thin substrate having a thickness of 0.5 mm or less, more preferably 0.3 mm or less, of the interposer substrate. Further, it is preferable that the wiring of the wiring layer provided in the insulating resin layer has a curved shape, whereby the tensile stress accompanying the difference in thermal expansion is absorbed by deformation.

A main invention relating to a manufacturing method is that a semiconductor chip provided with a predetermined circuit is mounted on an interposer substrate via an anisotropic conductive layer, and electrodes of the semiconductor chip are connected via the anisotropic conductive layer. And connecting the electrodes to electrodes of the interposer substrate. Here, portions other than the electrodes of the semiconductor chip and portions other than the electrodes of the interposer substrate are insulated from each other by the anisotropic conductive film.

Another major invention relating to a manufacturing method includes a step of mounting a semiconductor chip provided with a predetermined circuit on an interposer substrate via an anisotropic conductive layer, and a step of mounting the semiconductor chip of the interposer substrate. Forming an insulating resin layer on a surface opposite to the surface of the insulating resin layer, forming a conductive layer on the outer surface of the insulating resin layer, and forming a wiring by selectively removing the conductive layer. And a method for manufacturing a semiconductor device, comprising:

Here, a step of forming the insulating resin layer,
By repeating the step of forming the conductive layer and the step of forming the wiring a plurality of times, an insulating resin layer having a wiring layer on the surface of the interposer substrate opposite to the surface on which the semiconductor chip is mounted is formed. It may be formed by laminating a plurality of layers. It is preferable to form an external connection electrode on the outer surface of the outermost insulating resin layer. In addition, it is preferable that a solder resist is applied to a region other than the external connection electrode on the outer surface of the outermost insulating resin layer. Further, it is possible to form a solder ball on the external connection electrode. Alternatively, a plurality of semiconductor chips may be mounted on an interposer substrate in an assembled state, and a single-layer or multilayer insulating resin layer having a wiring layer may be formed, and then cut into individual pieces corresponding to the respective semiconductor chips.

A preferred embodiment of the invention included in the present application is to connect a semiconductor chip to a thin interposer substrate by flip-chip bonding and to improve the reliability thereof. That is, in general, in the manufacture of a chip size package, a semiconductor chip is bonded on an interposer substrate.However, a multilayer substrate is required from the structure of the chip, or a certain thickness is taken into consideration in order to reduce stress with a mounted motherboard, for example, Interposer substrates of 0.5 mm or more tend to be used. On the other hand, in a preferred embodiment of the present application, the interposer substrate is 0.5
A single-layer thin substrate having a thickness of not more than 0.3 mm, more preferably not more than 0.3 mm is used to ensure reliable connection and improve the reliability of flip-chip bonding.

Here, the connection between the semiconductor chip and the interposer substrate is made by using an anisotropic conductive film interposed therebetween. The anisotropic conductive film is obtained by mixing resin particles whose outer surfaces are covered with a conductive layer in a matrix resin. When thermocompression bonding is performed using such an anisotropic conductive film, conductivity is generated in the film thickness direction and insulation is generated in the plane direction. Conduction can be achieved and insulation between the electrode patterns can be formed simultaneously.

[0013] An insulating resin layer is formed on the surface of the interposer substrate on which the semiconductor chip is mounted on the surface opposite to the surface on which the semiconductor chip is mounted by using a substrate build-up technique, and via formation, copper plating, and wiring are performed. A wiring layer is formed by performing the formation. As the insulating resin at this time, it is preferable to use a rubber-like resin having an ultra-low elastic modulus. The insulating resin layer has an appropriate thickness.
Stack in three layers. This makes it possible to absorb the difference in the coefficient of thermal expansion between the semiconductor chip connected to the thin interposer substrate and the motherboard. It is preferable that the wiring shape of the wiring layer formed on the insulating resin layer be a curved shape avoiding a linear shape so that the deformation due to the difference in thermal expansion does not generate tensile stress.

According to the semiconductor device of this aspect, it is possible to connect the electrode of the semiconductor chip and the electrode of the interposer substrate by flip-chip connection using an anisotropic conductive film. It is possible to stabilize and improve the reliability. In particular, because the interposer substrate is thin and can be simplified,
The joining conditions are stable and the reliability is improved.

In addition, since the insulating resin layer having the wiring layer is formed on the interposer substrate connected to the semiconductor chip by such an anisotropic conductive film, the insulating resin layer is not affected by thermal stress after mounting on the motherboard. A flexible structure results in improved reliability during use. In addition, since there is a degree of freedom in wiring, it is possible to approach the wafer size of the semiconductor chip without limit.
As a result, a very small chip size package can be provided. Further, such a semiconductor device can be applied to a wide range of modularization of a multi-chip module or the like.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to an embodiment shown in the drawings. FIG. 1 shows the bonding between the semiconductor chip 10 and the interposer substrate 12. An electrode 11 made of, for example, an aluminum pack is formed on the bonding surface side of the semiconductor 10. Then, such a semiconductor chip 10 is joined to the interposer substrate 12 via the anisotropic conductive layer 13.

After bonding with the interposer substrate 12, insulating resin layers 16 and 17 are built up on the semiconductor chip 10 as shown in FIG. An external connection electrode 18 is formed on the outer surface of the outermost insulating resin layer 17. Such an external connection electrode 18 becomes an electrode of the semiconductor device, and when the semiconductor device is mounted on a mother board, conduction is achieved by the external connection electrode 18.

As described above, the semiconductor device of this embodiment is
The thin interposer substrate 12 is used,
The semiconductor chip 1 is placed on such an interposer substrate 12.
0 is mounted.

The connection between the semiconductor chip 10 and the interposer substrate 12 is made by the anisotropic conductive film 1 shown in FIGS.
3 is performed. As shown in FIG. 3, the anisotropic conductive film 13 is made of a matrix resin such as an epoxy resin, and has resin particles 22 dispersed therein. Each of the resin particles 22 has a spherical shape as shown in FIG. 4, a metal layer 23 made of metal plating is formed on an outer peripheral portion thereof, and a thin insulating film 24 is further formed to cover the outer peripheral surface. I have.

When heating and pressurization are performed with such an anisotropic conductive film 13 interposed between the semiconductor chip 10 and the interposer substrate 12, the electrodes 11 of the semiconductor chip 10 and the interposer substrate 12 as shown in FIG. The resin particles 22 are crushed by the height of these electrodes 11 and 27 between the electrodes 27 and 27, and the outer insulating coating 24 is broken to expose the metal layer 23. As a result, the electrodes 11 of the semiconductor chip 10 and the interposer substrate 1 are formed by the resin particles 22.
An electrical connection with the second electrode 27 is achieved. On the other hand, in a region where the electrodes 11 and 27 are not present, since the gap between the semiconductor chip 10 and the interposer substrate 12 is large, the resin particles 22 maintain the spherical shape as they are, Short circuits are prevented.
That is, conduction in regions other than the electrodes 11 and 27 is prevented, and thereby selective electrical connection is achieved.

As described above, the anisotropic conductive film 13 is used for bonding the semiconductor chip 10 and the interposer substrate 12, conducting the electrodes 11 and 27, and insulating the region where the electrodes 11 and 27 are not formed. Three functions will be achieved simultaneously. That is, when thermocompression bonding is performed with the anisotropic conductive film 13 sandwiched between the semiconductor chip 10 and the interposer substrate 12, the anisotropic conductive film 13 has conductivity in the thickness direction and Will exhibit electrical anisotropy having insulating properties. Thereby, permanent adhesion between the opposing electrodes 11 and 27, conduction between the electrodes 11 and 27, and insulation between the semiconductor chip 10 and the interposer substrate 12 in a region where the electrodes 11 and 27 are not formed are simultaneously achieved. Is done.

Thereafter, as shown in FIGS. 6 to 8, insulating resin layers 16 and 17 are thereafter formed on the surface of the interposer substrate 12 opposite to the surface on which the semiconductor chip 10 is mounted by using a substrate build-up technique. Form. At this time, the interlayer connection means 34 and 36 are formed in the insulating layers 16 and 17 by forming vias, and the wiring 33 is formed by etching the copper plating formed on the surface of the insulating layer 16, thereby improving the reliability. To form a high chip size package.

Here, the wiring 3 formed on the insulating resin layer 16
3 has a curved shape as shown in FIG. 7B, avoiding a linear shape as shown in FIG. 7A. The reason why the wiring 33 having such a curved shape is formed is that stress is released by deformation, thereby preventing disconnection.

FIG. 9 shows a manufacturing process of such a semiconductor device. Semiconductor chips are manufactured from silicon wafers. That is, a semiconductor chip is obtained by performing stud bump bonding after dicing the silicon wafer or dicing after forming the plating bump. Alternatively, KGD procurement that selects and supplies only good chips may be used. Also in this case, stud bump bonding is performed.

On the other hand, the interposer substrate is manufactured by providing wiring on one or both sides of the substrate material, manufacturing a single-sided substrate or a double-sided substrate in an aggregated state, and cutting the substrate into a predetermined size.

Thereafter, the interposer substrate 1 in the assembled state
The semiconductor chip 10 is adhered to the respective interposer substrates 12 via the anisotropic conductive film 13 on the base 2, a die bonder is performed, and the semiconductor chip 10 and the interposer substrate 12 are bonded by heating and bonding. Perform in. Thereafter, the insulating resin layers 16 and 17 having the wiring layers 33 and 18 are sequentially formed on the surface of the interposer substrate 12 opposite to the surface on which the semiconductor chip 10 is mounted by buildup. Thereafter, the interposer substrate 12 in the assembled state is cut and individual pieces corresponding to the respective semiconductor chips 10 are cut out to obtain a chip size package. Such a chip size package is subjected to a predetermined inspection process.

Next, this step will be described in more detail. FIG.
0 indicates a manufacturing process when the interposer substrate 12 is a double-sided through-hole substrate. Here, the interposer substrate 12 is a thin substrate having a thickness of 0.3 mm or less, and has a simple shape as much as possible. In the case of a double-sided substrate, the interposer substrate 12 is provided with an interlayer connection means 2 such as a through hole.
9 leads the wiring such as the land 30 to both sides.

On the other hand, when the interposer substrate 12 is a single-sided substrate, as shown in FIG.
After bonding the semiconductor chip 10 by 3, vias are formed on the interposer substrate 12 from the surface opposite to the mounting surface of the semiconductor chip 10 by laser light or the like, copper plating is performed, a photosensitive agent is applied, exposure and The development is performed, and the wiring 28 connected to the interlayer connection means 29 is formed on the surface on the opposite side of the interposer substrate 12 by an etching process.

There is no difference in the process of forming the insulating resin layers 16 and 17 between the case where the interposer substrate 12 composed of a double-sided through-hole substrate shown in FIG. 10 is used and the case where the interposer substrate 12 composed of a single-sided substrate is used. The operation will be described. An insulating resin is applied to the back surface of the interposer substrate 12 on which the semiconductor chip 10 is not mounted to form an insulating resin layer 16. As the insulating resin, a resin having elasticity even at the time of curing and being in a rubber-like state is selected. The thickness of the insulating resin layer 16 is set to 50 μm or more. If the ability to drill a via by laser is high, a thicker insulating resin layer 16 may be formed.

After a via is formed in the insulating resin layer 16 by a laser or photo process, the inner peripheral surface of the via is plated with copper. The copper plating is 10 to 20 μm, and the interlayer connection means 34 is formed by such copper plating.
Thereafter, the copper plating is etched by a photo process to form the wiring layer 33. The wiring 33 is not formed in a linear shape as shown in FIG. 7A as described above, but in a curved shape as shown in FIG.

Thereafter, an insulating resin is further applied to form a second insulating resin layer 17. Such an insulating resin layer 1
7, an interlayer connection means 36 is formed in the same manner as in the case of the first insulating resin layer 16 described above, and an external connection electrode 18 formed with such an interlayer connection means 36 is formed. The number of layers of the insulating resin layer is preferably two or more, and a three-layer structure may be employed. The number of layers may be selected in relation to the bump density.

Thereafter, a solder resist 3 is applied to cover the outer surface of the outermost insulating resin layer 17 except for the solder joint.
7 is applied to form lands. Here, an LGA (Land grid arra) using a land-like connecting means is used.
When used as y), it is preferable to apply gold flash plating to the external connection electrodes 18 constituting the lands. B using a hemispherical solder projection as a connecting means
In the case of a GA (Ball grid array), a solder ball is formed on the external connection electrode 18 constituting a land. Solder balls are formed by printing cream solder, melting the solder in a reflow oven or a ball mount reflow oven, and forming hemispherical solder balls by surface tension.

FIGS. 12 to 14 show the connection between the semiconductor chip 10 and the interposer substrate 12 in such a manufacturing process more specifically. Interposer substrate 1
2 is shown.

15 to 17 show a first build-up layer made of an insulating resin layer 16 on the surface of the interposer substrate 12 on which the semiconductor chip 10 is mounted, on the surface opposite to the surface on which the semiconductor chip 10 is mounted. And a second buildup layer comprising an insulating layer 17 are sequentially formed. FIG. 18 shows an arrangement of patterns of the semiconductor chip 10, the interposer substrate 12, the insulating resin layer 16, and the insulating resin layer 17 in the semiconductor device according to the embodiment.

As described above, the semiconductor device of this embodiment is
In forming the wiring of the build-up layers 16 and 17 formed on the interposer substrate 12, a structure in which two or more layers are formed and stress distortion is released by the elasticity of the wiring material and the flexibility of the insulating resin is adopted. . Especially insulating resin layer 1
In routing the wirings 33 formed on the wirings 6 and 17, in particular, avoid a linear shape as shown in FIG. 7A, and make a loop or a curved shape as shown in FIG. 7B. Is applied so as to cope with distortion and to have a stress relaxation function. In order to cope with the problem of the electric characteristics at this time, sufficient care is taken in designing. Further, the design is made to have flexibility by the thickness and the curvature of the copper foil constituting the wiring 33.

Such a semiconductor device can be developed in various ways. That is, development to a multi-chip module in which a plurality of semiconductor chips 10 of the same type or different types are arranged on a common interposer substrate 12 is possible.
For example, a heterogeneous IC such as a logic IC or a memory IC can be mounted on the interposer substrate 12 and connected by a wiring layer on the interposer substrate 12 to form a multi-chip module package having one function. At this time, it is also possible to seal the chip mount side with a resin and adjust the appearance as a package.

In addition, a small component such as a chip capacitor is mounted on the interposer substrate 12 in addition to the semiconductor chip 10 to provide a module having one function, thereby enabling a component having a higher function to be provided.

[0038]

The main invention of the present application is a semiconductor chip provided with a predetermined circuit and having an electrode provided on an outer surface thereof,
An interposer substrate on which a semiconductor chip is mounted,
A semiconductor having a semiconductor element and an interposer substrate joined to each other via an anisotropic conductive layer, and an electrode of the semiconductor element and an electrode of the interposer substrate being connected to each other by an anisotropic conductive layer It concerns the device.

Therefore, according to such a semiconductor device, the semiconductor element and the interposer substrate are joined to each other via the anisotropic conductive layer, and both electrodes are connected to each other. Therefore, the connection condition between the electrode of the semiconductor chip and the electrode of the interposer substrate is stabilized, and the reliability is improved.

A main invention relating to a manufacturing method is that a semiconductor chip provided with a predetermined circuit is mounted on an interposer substrate via an anisotropic conductive layer, and electrodes of the semiconductor chip are mounted via the anisotropic conductive layer. And connected to the electrodes of the interposer substrate.

Accordingly, it is possible to provide a method of manufacturing a semiconductor device in which the connection between the semiconductor chip and the interposer substrate is extremely easily and stably performed.

Another major invention relating to a manufacturing method includes a step of mounting a semiconductor chip provided with a predetermined circuit on an interposer substrate via an anisotropic conductive layer, and a step of mounting the semiconductor chip on the interposer substrate. Forming a conductive layer on the outer surface of the insulating resin layer, and forming a wiring by selectively removing the conductive layer. What you did.

Therefore, according to such a method of manufacturing a semiconductor device, it is possible to stably manufacture a semiconductor device in which an insulating resin layer is built up on the surface of the interposer substrate opposite to the surface on which the semiconductor chip is mounted. Will be possible.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a mounting of a semiconductor chip on an interposer substrate.

FIG. 2 is a longitudinal sectional view showing an operation of forming a build-up layer on a surface of the interposer substrate opposite to a surface on which the semiconductor chip is mounted.

FIG. 3 is an enlarged sectional view of an anisotropic conductive film.

FIG. 4 is an enlarged vertical cross-sectional view of resin particles dispersed in an anisotropic conductive film.

FIG. 5 is an enlarged vertical sectional view showing a connection between electrodes by an anisotropic conductive film.

FIG. 6 is a longitudinal sectional view of a main part of the completed semiconductor device.

FIG. 7 is a plan view of a wiring formed on an insulating resin layer.

FIG. 8 is an external perspective view of a main part of the semiconductor device.

FIG. 9 is a block diagram showing a manufacturing process.

FIG. 10 is a longitudinal sectional view illustrating a manufacturing process when an interposer substrate including a double-sided through-hole substrate is used.

FIG. 11 is a longitudinal sectional view illustrating a manufacturing process when an interposer substrate formed of a single-sided substrate is used.

FIG. 12 is an external perspective view showing connection of a semiconductor chip to an interposer substrate.

FIG. 13 is an external perspective view of an interposer substrate on which a semiconductor chip is mounted.

FIG. 14 is a plan view of the same.

FIG. 15 is an external perspective view showing a build-up state of the semiconductor device.

FIG. 16 is an external perspective view of a built-up semiconductor device.

FIG. 17 is a plan view of a principal part of the semiconductor device.

FIG. 18 is a plan view showing a pattern of each layer constituting the semiconductor device.

[Explanation of symbols]

10 ‥‥ semiconductor chip, 11 ‥‥ electrode (pad), 12
{Interposer substrate, 13} Anisotropic conductive film (layer), 16, 17} Insulating resin layer, 18} External connection electrode, 22} Resin particles, 23} Metal layer, 24}
Insulation coating, 27 electrode, 28 wiring, 29 interlayer connection, 30 land, 33 wiring, 34 interlayer connection, 36 interlayer connection, 37 solder resist

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H01L 23/31

Claims (15)

[Claims] 1. A semiconductor chip provided with a predetermined circuit and having an electrode provided on an outer surface thereof; and an interposer substrate on which the semiconductor chip is mounted, wherein the semiconductor element and the interposer substrate are different from each other. A semiconductor device, wherein the semiconductor device is joined to each other via an anisotropic conductive layer, and the electrode of the semiconductor element and the electrode of the interposer substrate are connected to each other by the anisotropic conductive layer. 2. An insulating resin layer having a wiring layer is formed on a surface of the interposer substrate opposite to a surface on which the semiconductor chip is mounted.
3. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein an insulating resin layer having a wiring layer is formed by laminating a plurality of layers. 4. The semiconductor device according to claim 2, wherein the insulating resin layer is made of a material having a low elastic coefficient. 5. The semiconductor device according to claim 2, wherein an external connection electrode is formed on an outer surface of the outermost insulating resin layer. 6. The interposer substrate has a thickness of 0.5 m.
2. The semiconductor device according to claim 1, wherein m is equal to or less than m. 7. The wiring according to claim 1, wherein the wiring of the wiring layer provided on the insulating resin layer has a curved shape.
3. The semiconductor device according to claim 1. 8. A semiconductor chip provided with a predetermined circuit is mounted on an interposer substrate via an anisotropic conductive layer, and an electrode of said semiconductor chip is mounted on said interposer substrate via said anisotropic conductive layer. And a method of manufacturing a semiconductor device. 9. The semiconductor device according to claim 8, wherein a portion other than the electrode of the semiconductor chip and a portion other than the electrode of the interposer substrate are insulated from each other by the anisotropic conductive film. Method. 10. A step of mounting a semiconductor chip provided with a predetermined circuit on an interposer substrate via an anisotropic conductive layer, and a surface of the interposer substrate opposite to a surface on which the semiconductor chip is mounted. Forming an insulating resin layer, forming a conductive layer on an outer surface of the insulating resin layer, and selectively removing the conductive layer to form a wiring. Manufacturing method of a semiconductor device. 11. A surface on which the semiconductor chip of the interposer substrate is mounted by repeating a step of forming the insulating resin layer, a step of forming the conductive layer, and a step of forming the wiring a plurality of times. The method of manufacturing a semiconductor device according to claim 10, wherein an insulating resin layer having a wiring layer on a surface on the opposite side is formed by laminating a plurality of layers. 12. The method according to claim 10, wherein an external connection electrode is formed on an outer surface of the outermost insulating resin layer. 13. The method of manufacturing a semiconductor device according to claim 12, wherein a solder resist is applied to other regions except for the external connection electrodes on the outer surface of the outermost insulating resin layer. . 14. The method according to claim 12, wherein a solder ball is formed on the external connection electrode. 15. A method of mounting a plurality of semiconductor chips on an interposer substrate in a collective state, forming a single-layer or multi-layer insulating resin layer having a wiring layer, and then cutting into individual pieces corresponding to the respective semiconductor chips. The method of manufacturing a semiconductor device according to claim 10, wherein: