JP2002111402A - Amplifier circuit - Google Patents

Abstract

(57) Abstract: In a conventional amplifier circuit having a negative feedback circuit composed of a parallel connection circuit of a resistor and a capacitor, the capacitance value of the negative feedback circuit is reduced in order to realize a high-speed circuit. Therefore, the influence of the parasitic capacitance attached to each part of the circuit cannot be ignored. SOLUTION: An amplifier circuit according to the present invention is configured so that a parasitic capacitance associated with a collector of a transistor Q2 constituting an output stage 10 of an amplifier BA1 does not become an input-side parasitic capacitance via a negative feedback circuit F1. It has a diode D1 whose anode is connected to the collector and whose cathode is connected to the output terminal of the amplifier BA1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit having a negative feedback circuit composed of a parallel connection circuit of a resistor and a capacitor, and more particularly to a reduction in a parasitic capacitance whose influence cannot be ignored as the circuit speeds up. It relates to an amplifier circuit.

[0002]

2. Description of the Related Art Here, a conventional amplifier circuit is a CD.
-An explanation will be given using a light receiving amplifier circuit used for a ROM drive, a DVD drive, or the like as an example. FIG. 11 is a circuit diagram showing one configuration example of a conventional light receiving amplifier circuit. The light-receiving amplifier circuit 1 'is an amplification circuit that amplifies a signal (input voltage) detected by the photodiode 2 constituting the light-receiving element of the optical pickup and sends the signal to the next-stage signal processing unit (not shown). An operational amplifier A1 is provided as a first-stage amplifier.

A predetermined reference voltage _Vref is applied to a positive-phase input terminal (+) of the operational amplifier A 1, and a negative-phase input terminal (−) is connected to a cathode of the photodiode 2. Note that the anode of the photodiode 2 is connected to the ground. Therefore, the output voltage transmitted from the operational amplifier A1 is a voltage obtained by amplifying the difference voltage between the input voltage obtained from the photodiode 2 and the reference voltage _Vref .

The output terminals of the operational amplifier A1 are connected to buffer amplifiers BA1 'and BA2' via a plurality of non-saturated switch circuits sw1 and sw2. The switching of the switch circuits sw1 and sw2 is controlled so as to connect one of the buffer amplifiers BA1 ′ and BA2 ′ to the operational amplifier A1. Buffer amplifier BA1 ', BA2'
Are connected to the signal processing unit (not shown) at the next stage and the like as output terminals of the light receiving amplifier circuit 1 ', while the negative-phase input terminals of the operational amplifier A1 are connected via negative feedback circuits F1 and F2, respectively. It is also connected to the terminal (-).

FIG. 12 is a circuit diagram showing a configuration example of the negative feedback circuit F1 (F2). As shown in the figure, the negative feedback circuit F1 (F2) is configured by a parallel connection circuit of a gain resistor R _f and a phase compensation capacitance C _f .

In the light receiving amplifier circuit 1 'having the above-described circuit configuration, the buffer amplifier BA1' (BA2 ')
Is returned to the opposite-phase input terminal (-) of the operational amplifier A1 through the negative feedback circuit F1 (F2) in the opposite phase, so that the frequency characteristics and S / N of the light receiving amplifier circuit 1 'are improved. be able to. Further, the gain can be stably maintained even when the temperature or the power supply voltage fluctuates.

In the light-receiving amplifier circuit 1 'having the above structure, a plurality of buffer amplifiers BA1' and BA2 'selectable by the switch circuits sw1 and sw2 are connected to the output terminal of the operational amplifier A1. The control is performed according to a change in the amount of light incident on the photodiode 2. By performing such switching control, the buffer amplifiers BA1 ′ and BA2 ′ are appropriately selected and the gain is adjusted so that the output of the light receiving amplifier circuit 1 ′ is not saturated even if the amount of light incident on the photodiode 2 changes. Can be switched.

[0008]

In recent years, as the rotational speed of a CD-ROM drive, a DVD drive, or the like has been increased, a higher-speed light receiving amplifier circuit has been demanded. In order to speed up the operation of the light receiving amplifier circuit, it is necessary to improve the frequency response of the circuit. Here, the negative feedback circuit F
In the above-described light receiving amplifier circuit 1 ′ where 1 (F2) is a parallel connection circuit of a gain resistor R _f and a phase compensation capacitance C _f ,
It is possible to improve the frequency response by increasing the cut-off frequency f _c of the negative feedback circuit F1 (F2). In addition,
Cut-off frequency f _c of the negative feedback circuit F1 (F2) is expressed by the following equation (1).

(Equation 1)

From the above equation (1), the negative feedback circuit F1
In order to increase the cut-off frequency f _c of the (F2) may can be seen that if reducing the capacitance value of the gain resistor R _f of the resistor value or the phase compensation capacitance C _f. However, the gain resistance R
The resistance value of _f is determined in advance by the amount of light incident on the photodiode 2 (that is, the input voltage to the light-receiving amplifier circuit 1 ') and the output voltage to be extracted from the light-receiving amplifier circuit 1', and cannot be largely changed. Therefore, in order to increase the speed of the light receiving amplifier circuit 1 ', it is necessary to reduce the capacitance value of the phase compensation capacitance _Cf.

Conventionally, the capacitance value of the phase compensation capacitance C _f of a negative feedback circuit F1 (F2) is set to dominant size as there is no need to consider the influence of the parasitic capacitance associated with the respective portions of the circuit ing. However, _if the capacitance value of the phase compensation capacitance _Cf is reduced in order to realize a high-speed circuit, the influence of the parasitic capacitance cannot be ignored, and the characteristics of the light receiving amplifier circuit 1 ′ are affected by the parasitic capacitance. There is a risk that it will.

Among the parasitic capacitances associated with each part of the circuit, the buffer amplifier BA1 '(BA2') is particularly problematic.
Capacitance associated with the output stage of the negative feedback circuit F1 (F2)
Element (gain resistor R _f or phase compensation capacitance C _f) constituting the parasitic capacitance associated with itself, and a parasitic capacitance associated with the input lines of the light receiving amplifier circuit 1 '(cathode wirings) from the photodiode 2.

First, the buffer amplifier BA1 '(BA
The parasitic capacitance associated with the output stage 2 ′) will be described.
FIG. 13 is a circuit diagram showing a configuration example of the output stage of the buffer amplifier BA1 '(BA2'). As shown in the figure, the output stage 10 'of the buffer amplifier BA1' (BA2 ') is
It has NP transistors Q1, Q2, Q3. PN
The base of the P transistor Q1 is a buffer amplifier BA1 '.
The output voltage of the operational amplifier A1 is given to the input terminal of (BA2 '). Also, the PNP transistor Q1
Is connected to ground and the emitter is P
It is connected to the collector of NP transistor Q2.

The connection node between the emitter of the PNP transistor Q1 and the collector of the PNP transistor Q2 corresponds to the output terminal of the buffer amplifier BA1 '(BA2'), and the signal processing unit (not shown) at the next stage And the like, and also connected to the negative-phase input terminal (-) of the operational amplifier A1 via the negative feedback circuit F1 (F2).

The PNP transistors Q2 and Q3 are connected to the output stage 1
It constitutes a current mirror serving as a constant current source of 0 '.
The base of the PNP transistor Q2 is connected to the base and the collector of the PNP transistor Q3, and the collector of the PNP transistor Q3 is connected to the ground via the constant current source I1. Also, the PNP transistor Q
Each of the emitters 2 and Q3 is connected to a power supply voltage line.

As described above, the maximum output voltage of the constant current source using the collector output of the PNP transistor is higher than the maximum output voltage of the constant current source using the emitter output of the NPN transistor. It is advantageous to ensure.

The buffer amplifier BA1 'having the above configuration
In (BA2 '), the collector of the PNP transistor Q2 constituting the constant current source of the output stage 10' has a large parasitic capacitance due to its configuration. FIG. 14 is a sectional structural view showing one configuration example of the PNP transistor Q2.

As shown in FIG. 1, an N-type well 101, a P-type well 102,
An N-type well 103 and a P-type well 104 are formed. Each terminal of a collector (C), a base (B), and an emitter (E) of the PNP transistor Q2 is connected to a P-type well 102, an N-type well 103, and a P-type well, respectively. It has been pulled out of the mold well 104. The N-type well 101 is separated from other elements by P-type diffusion layers 105 and 106.

[0018] Here, although the parasitic capacitance C _x is associated with the PN junction between the P-type well 102 and the N-type well 101 constituting the collector of the PNP transistor Q2,
Capacitance value of the parasitic capacitance C _x increases in proportion to the area of the PN junction. Therefore, the parasitic capacitance C _x associated with the collector of the PNP transistor Q2 has a considerably large capacitance value than the parasitic capacitance associated with the base and emitter.

The buffer amplifier BA1 '(BA
In 2 '), the collector of the PNP transistor Q2 large parasitic capacitance C _x thus is associated is connected directly to the output terminal of itself. Therefore, the negative feedback circuit F1
Influence of the parasitic capacitance C _x and continue to reduce the capacitance value of the phase compensation capacitance C _f constituting the (F2) can not be ignored, characteristics of the light receiving amplifier circuit 1 'from being affected by the parasitic capacitance C _x.

In particular, a plurality of buffer amplifiers BA1 'and BA2' selectable by switch circuits sw1 and sw2.
, The parasitic capacitance C _x associated with the output stage of the unselected buffer amplifier BA1 ′ (BA2 ′) also becomes a parasitic capacitance on the input side through the negative feedback circuit F1 (F2). The effect is greater.

Next, a description will be given parasitic capacitance associated with the negative feedback circuit elements constituting the F1 (F2) (the gain resistor R _f or phase compensation capacitance C _f) itself. First, FIG. 15 is a cross-sectional structure diagram showing a configuration example of a conventional gain resistor _Rf . As shown in the figure, an N-type well 111 and a P-type well 112 are formed on a P-type substrate 110 in order from the deepest one. Both terminals of the gain resistor _Rf are drawn out from both ends of the P-type well 112, respectively.
Corresponds to the gain resistance _Rf . The N-type well 111
Are separated from other elements by P-type diffusion layers 113 and 114. Thus the gain resistor R _f consisting of a structure, a large parasitic capacitance C _x is associated between the P-type substrate 110 and the N-type well 111.

FIG. 16 is a sectional view showing an example of a configuration of a conventional phase compensation capacitor _Cf. As shown in this figure,
An N-type well 121 is formed on a P-type substrate 120. The N-type well 121 is separated from other elements by P-type diffusion layers 122 and 123, and an insulating film 124 is formed on the P-type diffusion layer 122. N-type well 121
A nitride film 125 is formed on the insulating film 124, and a metal layer 126 is formed on the nitride film 125. Both terminals of the phase compensation capacitor C _f are N-type well 1
21 and the metal layer 126, and a phase compensation capacitance C _f required between the N-type well 121 and the metal layer 126 with the nitride film 125 interposed therebetween is formed. Thus the phase compensation capacitor C _f made of such structure, large parasitic capacitance C _x is associated between the P-type substrate 120 and the N-type well 121.

Next, the parasitic capacitance associated with the input wiring (cathode wiring) from the photodiode 2 to the light receiving amplifier circuit 1 'will be described. FIG. 17 is a plan view and a sectional structural view showing an example of the arrangement of a conventional light receiving amplifier circuit 1 'and photodiode 2. As shown in the plan view of (a) in the figure, the light receiving amplifier circuit 1 ′ and the photodiode 2 are connected by a cathode wiring 133, and the portions other than the photodiode 2 are uniformly covered by a light shielding metal layer 135. The light shielding metal layer 135 prevents unnecessary disturbance light from entering the light receiving amplifier circuit 1 '.

FIG. 2B shows AA ′ shown in FIG.
It is sectional drawing. As shown in FIG.
An N-type semiconductor layer 131 is formed thereon, and an insulating film 132 is formed thereon. Light receiving amplifier circuit 1 '
A cathode wiring 133 connecting the photodiode and the photodiode 2 is formed on the insulating film 132. Cathode wiring 133
An insulating film 133 is further formed thereon, and a light shielding metal layer 135 uniformly covers the insulating film 133. In such a structure, a large parasitic capacitance _Cx is attached between the cathode wiring 133 and the P-type semiconductor layer 131 and between the cathode wiring 133 and the light shielding metal layer 135.

As described above, the high speed of the light receiving amplifier circuit 1 '
Phase compensation capacitance C _fThe capacitance value of
The parasitic capacitance C_xInfluence cannot be ignored
And the characteristic of the light receiving amplifier circuit 1 ′ is_xBy
May be influenced by

The present invention has been made in view of the above-described problems, and in an amplifier circuit having a negative feedback circuit comprising a parallel connection circuit of a resistor and a capacitor, a reduction in a parasitic capacitance whose influence cannot be ignored as the circuit speeds up is realized. It is an object of the present invention to provide a modified amplifier circuit.

[0027]

In order to achieve the above object, in an amplifier circuit according to the present invention, an operational amplifier for amplifying a difference voltage between an input voltage and a reference voltage is connected to an output terminal of the operational amplifier. A buffer amplifier in which a constant current source constituting its own output stage is formed of a PNP transistor;
A negative feedback circuit comprising a parallel connection circuit of a resistor and a capacitor, wherein the amplifier circuit returns a part of the output of the buffer amplifier to the input side of the operational amplifier via the negative feedback circuit; A diode is provided between the output terminal of the buffer amplifier, the anode of the diode is connected to the collector of the PNP transistor, and the cathode is connected to the output terminal of the buffer amplifier.

The PNP transistor forming the constant current source at the output stage of the buffer amplifier is a first PNP transistor, and a second PNP transistor is provided between the first PNP transistor and the output terminal of the buffer amplifier. The collector of the transistor is the first PNP
A configuration may be employed in which the collector is connected to the transistor, the base is connected to the output terminal of the buffer amplifier, and the emitter is grounded.

Alternatively, an NPN transistor is provided between the PNP transistor constituting the constant current source at the output stage of the buffer amplifier and the output terminal of the buffer amplifier, and the collector and the base of the NPN transistor are connected to the collector of the PNP transistor. And the emitter may be connected to the output terminal of the buffer amplifier.

A plurality of buffer amplifiers selectable by a switch circuit are connected to the output terminal of the operational amplifier, and the negative feedback circuit is provided between the output terminal of each buffer amplifier and the input terminal of the operational amplifier. Good.

Further, in the amplifier circuit having the above configuration, it is preferable that the resistor constituting the negative feedback circuit is formed on a LOCOS oxide film on a semiconductor substrate. Further, it is preferable that the capacitance constituting the negative feedback circuit is formed on a LOCOS oxide film. At this time, it is preferable that the two capacitors formed on the LOCOS oxide film are connected in series on the LOCOS oxide film side to form the capacitors constituting the negative feedback circuit.

In the amplifier circuit having the above structure, it is preferable that the input wiring to the operational amplifier is formed on the LOCOS oxide film on the semiconductor substrate. Further, it is preferable to apply a light-shielding metal to a portion except on the input wiring to the operational amplifier.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a description will be given of a light-receiving amplifier circuit used in a CD-ROM drive, a DVD drive or the like as an amplifier circuit according to the present invention. FIG.
FIG. 2 is a circuit diagram showing a configuration example of a light receiving amplifier circuit according to the present invention. As shown in the figure, the light-receiving amplifier circuit 1 according to the present invention has substantially the same configuration as the conventional light-receiving amplifier circuit 1 '(see FIG. 11), and the negative feedback circuit F1 (F2) is also the same as the conventional one. , And a parallel connection circuit of a gain resistor R _f and a phase compensation capacitance C _f (see FIG. 12).

Therefore, portions having the same configuration and operation as those of the prior art are denoted by the same reference numerals as in FIGS. 11 and 12, and the description thereof will be omitted. Hereinafter, buffer amplifiers BA1 (BA2) which are characteristic portions of the present invention will be described. , The parasitic capacitance associated with the elements (gain resistor R _f , phase compensation capacitance C _f ) constituting the negative feedback circuit F1 (F2), and the photodiode 2 to the light receiving amplifier A description will be given with emphasis on a configuration for reducing the parasitic capacitance accompanying the input wiring (cathode wiring) to the circuit 1.

First, the reduction of the parasitic capacitance associated with the output stage of the buffer amplifier BA1 (BA2) will be described. FIG. 2 is a circuit diagram showing a first embodiment of the output stage of the buffer amplifier BA1 (BA2). As shown in the drawing, the output stage 10 of the buffer amplifier BA1 (BA2) in the present embodiment has substantially the same configuration as the output stage 10 '(see FIG. 13) of the conventional buffer amplifier BA1' (BA2 '). I have.

Therefore, the portions having the same configuration and operation as those of the prior art are denoted by the same reference numerals as those in FIG. 13 and the description thereof will be omitted. Here, the parasitic capacitance associated with the collector of the PNP transistor Q2 is determined by the negative feedback circuit F1 ( A description will be given with emphasis on the diode D1 provided as means for preventing the parasitic capacitance on the input side of the operational amplifier A1 via F2).

As shown in the figure, a diode D1 as a parasitic capacitance reducing means is provided between the collector of the PNP transistor Q2 and the output terminal of the buffer amplifier BA1 (BA2), and its anode is connected to the PNP transistor Q2.
And the cathode is a buffer amplifier BA
1 (BA2).

FIG. 3 is a sectional structural view showing one configuration example of the diode D1. As shown in the figure, an N-type well 12, a P-type well 13, and an N-type
A mold well 14 is formed, and the anode (A) and cathode (K) terminals of the diode D1 are drawn from the P-type well 13 and the N-type well 14, respectively. Note that the N-type well 12 is separated from other elements by P-type diffusion layers 15 and 16.

Here, the P-type well 13 forming the anode of the diode D1 and the N-type well 1 forming the cathode of the diode D1.
4 is accompanied by a parasitic capacitance associated with a PN junction.
However, since the junction area between the P-type well 13 and the N-type well 14 is much smaller than the PN junction area of the parasitic capacitance associated with the collector of the PNP transistor Q2 (see FIG. 14), the capacitance value is also smaller than the PNP transistor Q2. Is very small compared to the parasitic capacitance associated with the collector.

As described above, in the output stage 10 of the buffer amplifier BA1 (BA2) in the present embodiment, the collector of the PNP transistor Q2 accompanied by a large parasitic capacitance is not directly connected to the output terminal of the buffer amplifier BA1 (BA2). , The cathode of the diode D1 having a small parasitic capacitance is connected to the output terminal of the buffer amplifier BA1 (BA2).

With such a configuration, the parasitic capacitance associated with the output stage 10 of the buffer amplifier BA1 (BA2) is in series with the parasitic capacitance associated with the diode D1 and the parasitic capacitance associated with the collector of the PNP transistor Q2. Since it is a combined capacitance, its capacitance value is governed by the capacitance value of the parasitic capacitance associated with the diode D1. Therefore,
Parasitic capacitance associated with the collector of PNP transistor Q2 is reduced by diode D1, resulting in PN
It is possible to prevent the parasitic capacitance associated with the collector of the P transistor Q2 from becoming the parasitic capacitance on the input side of the operational amplifier A1 via the negative feedback circuit F1 (F2).

FIG. 4 is a circuit diagram showing a second embodiment of the output stage of the buffer amplifier BA1 (BA2). As shown in the figure, the buffer amplifier BA1 (B
The output stage 20 of A2) is the output stage 1 of the first embodiment described above.
0 (see FIG. 2).

Therefore, portions having the same configuration and operation as those in the first embodiment described above are denoted by the same reference numerals as those in FIG. 2 and the description thereof is omitted. Here, the parasitic capacitance associated with the collector of the PNP transistor Q2 is reduced. Negative feedback circuit F1
A description will be given with emphasis on the PNP transistor Q4 provided as means for preventing the input side of the operational amplifier A1 from becoming a parasitic capacitance via (F2).

As shown in the figure, the PNP transistor Q4, which is a parasitic capacitance reducing means, is provided between the collector of the PNP transistor Q2 and the output terminal of the buffer amplifier BA1 (BA2). , The base is connected to the output terminal of the buffer amplifier BA1 (BA2), and the emitter is connected to the ground.

Here, the structure of the PNP transistor Q4 is the same as that of the PNP transistor Q2 shown in FIG.
Parasitic capacitance accompanies each between the base and the emitter and between the base and the collector of the PNP transistor Q4.
However, as is apparent from FIG. 14, the PN junction area of the parasitic capacitance between the base and emitter and between the base and collector of the PNP transistor Q4 is PNP.
Parasitic capacitance PN associated with the collector of transistor Q2
Since it is very small compared to the junction area, its capacitance value is also PN
It is much smaller than the parasitic capacitance associated with the collector of P transistor Q2.

As described above, in the output stage 20 of the buffer amplifier BA1 (BA2) in the present embodiment, the collector of the PNP transistor Q2 having a large parasitic capacitance is not directly connected to the output terminal of the buffer amplifier BA1 (BA2). The base of the PNP transistor Q4 having a small parasitic capacitance is connected to the output terminal of the buffer amplifier BA1 (BA2).

With such a configuration, the parasitic capacitance associated with the output stage 20 of the buffer amplifier BA1 (BA2) is the parasitic capacitance associated with the base of the PNP transistor Q4 and the parasitic capacitance associated with the collector of the PNP transistor Q2. , And the capacitance value is P
It is governed by the capacitance value of the parasitic capacitance attached to the base of NP transistor Q4. Therefore, the parasitic capacitance associated with the collector of the PNP transistor Q2 is reduced by the PNP transistor Q4, and the parasitic capacitance associated with the collector of the PNP transistor Q2 is reduced by the negative feedback circuit F2.
1 (F2) can be prevented from becoming a parasitic capacitance on the input side of the operational amplifier A1.

FIG. 5 is a circuit diagram showing a third embodiment of the output stage of the buffer amplifier BA1 (BA2). As shown in the figure, the buffer amplifier BA1 (B
The output stage 30 of A2) is the output stage 1 of the first embodiment described above.
0 (see FIG. 2).

Therefore, portions having the same configuration and operation as those in the first embodiment described above are denoted by the same reference numerals as those in FIG. 2 and their description is omitted. Here, the parasitic capacitance associated with the collector of the PNP transistor Q2 is reduced. Negative feedback circuit F1
A description will be given with emphasis on the NPN transistor Q5 provided as a means for preventing the parasitic capacitance on the input side of the operational amplifier A1 via (F2).

As shown in the figure, the NPN transistor Q5, which is a parasitic capacitance reducing means, is provided between the collector of the PNP transistor Q2 and the output terminal of the buffer amplifier BA1 (BA2).
The collector is connected to the P transistor Q2, and the emitter is connected to the output terminal of the buffer amplifier BA1 (BA2).

FIG. 6 is a sectional structural view showing an example of the configuration of the NPN transistor Q5. As shown in the figure, an N-type well 32, a P-type well 33, and an N-type well 34 are formed on a P-type substrate 31 in order from the deepest, and the collector (C) and the base (B) of the NPN transistor Q5 are formed. ) And the terminals of the emitter (E) are drawn out from the N-type well 32, the P-type well 33, and the N-type well 34, respectively. In addition,
The N-type well 32 is separated from other elements by P-type diffusion layers 35 and 36.

Here, a parasitic capacitance associated with the PN junction accompanies between the P-type well 33 forming the base of the NPN transistor Q5 and the N-type well 34 forming the emitter. However, since the junction area between the P-type well 33 and the N-type well 34 is much smaller than the PN junction area of the parasitic capacitance associated with the collector of the PNP transistor Q2 (see FIG. 14), the capacitance value is also smaller than the PNP transistor Q2. Is very small compared to the parasitic capacitance associated with the collector.

As described above, in the output stage 30 of the buffer amplifier BA1 (BA2) in the present embodiment, the collector of the PNP transistor Q2 having a large parasitic capacitance is not directly connected to the output terminal of the buffer amplifier BA1 (BA2). The emitter of the NPN transistor Q5 having a small parasitic capacitance is connected to the output terminal of the buffer amplifier BA1 (BA2).

With such a configuration, the parasitic capacitance associated with the output stage 30 of the buffer amplifier BA1 (BA2) includes the parasitic capacitance associated with the emitter of the NPN transistor Q5 and the parasitic capacitance associated with the collector of the PNP transistor Q2. , And the capacitance is governed by the capacitance of the parasitic capacitance associated with the emitter of the NPN transistor Q5. Accordingly, the parasitic capacitance associated with the collector of the PNP transistor Q2 is reduced by the NPN transistor Q5, and the parasitic capacitance associated with the collector of the PNP transistor Q2 is reduced via the negative feedback circuit F1 (F2) on the input side of the operational amplifier A1. Parasitic capacitance can be prevented.

Next, a description will be given of the reduction of the parasitic capacitance accompanying the element (gain resistor R _f or phase compensation capacitance C _f ) itself constituting the negative feedback circuit F1 (F2). First, FIG.
FIG. 3 is a sectional structural view showing one configuration example of a gain resistor _{Rf according} to the present invention. As shown in FIG.
OCOS (LOCalized Oxidation of Silicon) oxide film 4
1 (hereinafter referred to as a LOCOS oxide film 41), on which a P-type (or N-type) semiconductor 42 is formed. Both terminals of the gain resistor _Rf are P-type (N
P) (P type)
(Type) The semiconductor 42 corresponds to the gain resistor _Rf .

The gain resistor R having such a structure_fTo
Is between the P-type substrate 40 and the P-type (N-type) semiconductor 42.
Parasitic capacitance is attached across the cost oxide film 41,
Is the conventional gain resistance R_f(See Fig. 15)
This is a very small value as compared with the parasitic capacitance that occurs. like this
And a gain resistor R constituting a negative feedback circuit F1 (F2). _f
Formed on the LOCOS oxide film 41, the gain resistance
Anti-R_fParasitic capacitance associated with the
The raw capacitance is supplied to the operational amplifier A via the negative feedback circuit F1 (F2).
1 can be prevented from becoming a parasitic capacitance on the input side.
You.

FIG. 8 shows a phase compensation capacitor C according to the present invention.
FIG. 3 is a cross-sectional structure diagram showing one configuration example of _f . As shown in the figure, a LOCOS oxide film 51 is formed on a P-type substrate 50, and an N-type semiconductor layer 52 is formed thereon. N
A nitride film 53 is formed on the mold semiconductor layer 52, and a metal layer 54 is formed on the nitride film 53. Both terminals of the phase compensation capacitance C _f are drawn out from the N-type semiconductor layer 52 and the metal layer 54, respectively, and the phase compensation capacitance C _f required between the N-type semiconductor layer 52 and the metal layer 54 with the nitride film 53 interposed therebetween. Is formed.

The phase compensation capacitor C having such a structure_f
Between the P-type substrate 50 and the N-type semiconductor layer 52.
Parasitic capacitance accompanies the oxide film 51.
The value is the conventional phase compensation capacitance C_f(See Fig. 16)
This is a very small value compared to the parasitic capacitance. like this
The phase compensation capacitance C constituting the negative feedback circuit F1 (F2)
_fIs formed on the LOCOS oxide film 51,
Amount C_fCan reduce the parasitic capacitance associated with
The parasitic capacitance is supplied to the operational amplifier via the negative feedback circuit F1 (F2).
It is possible to prevent the parasitic capacitance on the input side of the
it can.

[0059] FIG. 9 is a cross-sectional view and an equivalent circuit diagram showing another configuration example of the phase compensation capacitance C _f according to the present invention. As shown in the sectional structural view of FIG. 2A, a LOCOS oxide film 61 is formed on a P-type substrate 60, and an N-type semiconductor layer 62 is formed thereon. Nitride films 63a and 63b are separately formed on the N-type semiconductor layer 62, and metal layers 64a and 64b are formed on the nitride films 63a and 63b, respectively.

[0060] are drawn respectively both terminals of the phase compensation capacitance C _f metal layer 64a, a 64b. That is,
The required phase compensation capacitance C _f is obtained by connecting two capacitances C _a and C _b formed between the N-type semiconductor layer 62 and the metal layers 64 a and 64 b with the nitride films 63 a and 63 b interposed therebetween in series on the LOCOS oxide film 61 side. It is formed by connecting. (B) in the figure shows an equivalent circuit diagram thereof.

The phase compensation capacitor C _f having such a structure is provided.
, The LOCOS parasitic capacitance C _x across the oxide film 61 is associated, a capacitance of the conventional phase compensation capacitance C _f (see FIG. 16 between the P-type substrate 60 and the N-type semiconductor layer 62 ) Is much smaller than the parasitic capacitance associated with ()). Also,
Metal layer 64a that is not involved any two terminals on the parasitic capacitance C _x of the aforementioned phase compensation capacitor C _f in the present embodiment, 6
4b. With such a configuration, the parasitic capacitance associated with the phase compensation capacitance C _f can be further reduced, and the parasitic capacitance is reduced by the negative feedback circuit F1.
It is possible to prevent the input side of the operational amplifier A1 from becoming a parasitic capacitance via (F2).

Next, the reduction of the parasitic capacitance associated with the input wiring (cathode wiring) from the photodiode 2 to the light receiving amplifier circuit 1 will be described. FIG. 10 is a plan view and a cross-sectional structure diagram showing one arrangement example of the light receiving amplifier circuit 1 and the photodiode 2 according to the present invention. As shown in the plan view of (a) in the figure, the light receiving amplifier circuit 1 and the photodiode 2 are connected by a cathode wiring 74, and a portion except on the photodiode 2 and the cathode wiring 74 is covered by a light shielding metal layer 76. ing. This light-shielding metal layer 76
Thus, unnecessary disturbance light is prevented from entering the light receiving amplifier circuit 1.

(B) in the figure is AA 'shown in (a) in the figure.
It is sectional drawing. As shown in the figure, an N-type semiconductor layer 71 is formed on a P-type substrate 70, and a LOCOS oxide film 72 is partially formed thereon. N-type semiconductor layer 7
An insulating film 73 is formed on the first and LOCOS oxide films 72, and a cathode wiring 74 connecting the light receiving amplifier circuit 1 and the photodiode 2 is formed on the insulating film 73. Note that the cathode wiring 74 is provided so as to be located on the LOCOS oxide film 72. An insulating film 75 is further formed on the cathode wiring 74, and the light-shielding metal layer 76 on the insulating film 75 is formed so as to cover a portion except on the cathode wiring 74.

In such a structure, a parasitic capacitance accompanies the locos oxide film 72 between the cathode wiring 74 and the N-type semiconductor layer 71. The capacitance value is the same as that of the conventional cathode wiring (see FIG. 17). ) Is much smaller than the parasitic capacitance associated with ()). As described above, by forming the cathode wiring 74 connecting the light receiving amplifier circuit 1 and the photodiode 2 on the LOCOS oxide film 72, the parasitic capacitance associated with the cathode wiring 74 can be reduced, and the parasitic capacitance can be reduced by the operational amplifier. A parasitic capacitance on the input side of A1 can be prevented.

In the present embodiment, since the light shielding metal layer 76 is formed so as to cover a portion excluding the portion above the cathode wiring 74, the parasitic capacitance between the cathode wiring 74 and the light shielding metal layer 76 is also large. The parasitic capacitance can be prevented from becoming the parasitic capacitance on the input side of the operational amplifier A1.

[0066]

In the amplifier circuit according to the present invention, an operational amplifier for amplifying a difference voltage between an input voltage and a reference voltage;
The constant current source connected to the output terminal of the operational amplifier and constituting its own output stage includes a buffer amplifier composed of a PNP transistor and a negative feedback circuit composed of a parallel connection circuit of a resistor and a capacitor. In the amplifier circuit for returning a part of the to the input side of the operational amplifier via the negative feedback circuit, a diode is provided between the collector of the PNP transistor and the output terminal of the buffer amplifier,
The anode of the diode is connected to the collector of the PNP transistor, and the cathode is connected to the output terminal of the buffer amplifier.

With such a configuration, the parasitic capacitance associated with the output stage of the buffer amplifier becomes a series combined capacitance of the parasitic capacitance associated with the diode and the parasitic capacitance associated with the collector of the PNP transistor. Therefore, the capacitance value is governed by the capacitance value of the parasitic capacitance associated with the diode. Therefore, the parasitic capacitance associated with the collector of the PNP transistor is reduced by the diode, and the parasitic capacitance associated with the collector of the PNP transistor becomes the parasitic capacitance on the input side of the operational amplifier via the negative feedback circuit. Can be prevented.

The PNP transistor forming the constant current source at the output stage of the buffer amplifier is a first PNP transistor, and a second PNP transistor is provided between the first PNP transistor and the output terminal of the buffer amplifier. The collector of the transistor is the first PNP
The same effect as described above can be obtained even if the collector is connected to the transistor, the base is connected to the output terminal of the buffer amplifier, and the emitter is grounded.

Alternatively, an NPN transistor is provided between the PNP transistor forming the constant current source at the output stage of the buffer amplifier and the output terminal of the buffer amplifier, and the collector and base of the NPN transistor are connected to the collector of the PNP transistor. And an emitter connected to the output terminal of the buffer amplifier, the same effect as described above can be obtained.

A plurality of buffer amplifiers selectable by a switch circuit are connected to the output terminal of the operational amplifier, and the negative feedback circuits are provided between the output terminal of each buffer amplifier and the input terminal of the operational amplifier. It is particularly effective to apply the present invention to an amplifier circuit. In the amplifier circuit having such a configuration, the parasitic capacitance associated with the output stage of the buffer amplifier that is not selected also becomes an input-side parasitic capacitance through the negative feedback circuit, but by applying the present invention, Since all the parasitic capacitances associated with each output stage of the buffer amplifier can be reduced, the effect of reducing the parasitic capacitances appears more remarkably.

Further, in the amplifier circuit having the above configuration, it is preferable that the resistor constituting the negative feedback circuit is formed on a LOCOS oxide film on a semiconductor substrate. With such a configuration, it is possible to reduce the parasitic capacitance associated with the resistor, and to prevent the parasitic capacitance from becoming the input-side parasitic capacitance of the operational amplifier via the negative feedback circuit. it can.

In the amplifier circuit having the above configuration, it is preferable that the capacitance forming the negative feedback circuit is formed on a LOCOS oxide film on a semiconductor substrate. With this configuration, it is possible to reduce the parasitic capacitance associated with the capacitance, and prevent the parasitic capacitance from becoming the input-side parasitic capacitance of the operational amplifier via the negative feedback circuit. it can.

At this time, it is preferable that the two capacitors formed on the LOCOS oxide film are connected in series on the LOCOS oxide film side to form the capacitors constituting the negative feedback circuit. With such a configuration, the parasitic capacitance associated with the capacitance can be further reduced, and the parasitic capacitance is prevented from becoming the parasitic capacitance on the input side of the operational amplifier via the negative feedback circuit. be able to.

In the amplifier circuit having the above configuration, it is preferable that the input wiring to the operational amplifier be formed on the LOCOS oxide film on the semiconductor substrate. With such a configuration, the parasitic capacitance associated with the input wiring can be reduced, and the parasitic capacitance can be prevented from becoming the parasitic capacitance on the input side of the operational amplifier.

Further, in the amplifier circuit having the above-described configuration, it is preferable that a light-shielding metal is applied to a portion excluding an input wiring to the operational amplifier. With such a configuration, the parasitic capacitance between the input wiring and the light-shielding metal can be significantly reduced, and the parasitic capacitance is prevented from becoming the parasitic capacitance on the input side of the operational amplifier. can do.

Even if the capacitance value of the capacitor constituting the negative feedback circuit is reduced in order to realize a high-speed circuit by reducing the parasitic capacitance associated with each part of the amplifier circuit by the above-described respective configurations, The characteristics of the amplifier circuit are not affected by the parasitic capacitance.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of a light receiving amplifier circuit according to the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of an output stage of a buffer amplifier BA1 (BA2).

FIG. 3 is a cross-sectional structure diagram illustrating a configuration example of a diode D1.

FIG. 4 is a circuit diagram showing a second embodiment of an output stage of a buffer amplifier BA1 (BA2).

FIG. 5 is a circuit diagram showing a third embodiment of an output stage of a buffer amplifier BA1 (BA2).

FIG. 6 is a sectional structural view showing one configuration example of an NPN transistor Q5.

FIG. 7 is a cross-sectional structure diagram illustrating a configuration example of a gain resistor R _{f according to} the present invention.

8 is a sectional view showing a configuration example of the phase compensation capacitance C _f according to the present invention.

9 is a sectional view and an equivalent circuit diagram showing another configuration example of the phase compensation capacitance C _f according to the present invention.

FIG. 10 is a plan view and a cross-sectional structure diagram showing an example of an arrangement of a light receiving amplifier circuit 1 and a photodiode 2 according to the present invention.

FIG. 11 is a circuit diagram illustrating a configuration example of a conventional light receiving amplifier circuit.

FIG. 12 is a circuit diagram illustrating a configuration example of a negative feedback circuit F1 (F2).

FIG. 13 is a circuit diagram illustrating a configuration example of an output stage of a buffer amplifier BA1 ′ (BA2 ′).

FIG. 14 is a sectional structural view showing one configuration example of a PNP transistor Q2.

FIG. 15 is a cross-sectional structure diagram illustrating a configuration example of a conventional gain resistor _Rf .

FIG. 16 is a cross-sectional structure diagram showing a configuration example of a conventional phase compensation capacitor _Cf.

FIG. 17 is a plan view and a cross-sectional structure diagram showing an example of an arrangement of a conventional light receiving amplifier circuit 1 ′ and a photodiode 2.

[Explanation of symbols]

Reference Signs List 1 light receiving amplifier circuit 2 photodiode (light receiving element) A1 operational amplifier sw1, sw2 switch circuit BA1, BA2 buffer amplifier F1, F2 negative feedback circuit R _f gain resistance C _f phase compensation capacitance 10, 20, 30 buffer amplifier BA1 (BA2)
Output stage Q1, Q2, Q3 PNP transistor I1 constant current source D1 diode Q4 PNP transistor Q5 NPN transistor 11, 31, 40, 50, 60, 70 P-type substrate 12, 14, 32, 34 N-type well 13, 33P Mold well 15, 16, 35, 36 P-type diffusion layer 41, 51, 61, 72 LOCOS oxide film 42 P-type (N-type) semiconductor 52, 62, 71 N-type semiconductor layer 53, 63a, 63b Nitride film 54, 64a , 64b Metal layer 73, 75 Insulation layer 74 Cathode wiring 76 Light shielding metal layer

Continuing on the front page F-term (reference) 5J090 AA01 AA47 AA56 CA18 CA65 DN02 FA20 HA02 HA19 HA25 HA29 HA38 HA44 KA03 KA05 MA13 MN01 MN04 QA02 TA01 5J092 AA01 AA47 AA56 CA18 CA65 FA20 HA02 HA19 HA25 HA29 HA38 MA01 KA03 KA03

Claims (9)

[Claims] 1. An operational amplifier for amplifying a difference voltage between an input voltage and a reference voltage, a buffer amplifier connected to an output terminal of the operational amplifier, and a constant current source constituting an output stage of the operational amplifier comprising a PNP transistor; A negative feedback circuit comprising a capacitor connected in parallel, and an amplifier circuit for returning a part of the output of the buffer amplifier to the input side of the operational amplifier via the negative feedback circuit, wherein the collector of the PNP transistor and the buffer An amplifier circuit comprising: a diode provided between the output terminal of an amplifier; an anode of the diode connected to a collector of the PNP transistor; and a cathode connected to an output terminal of the buffer amplifier. 2. An operational amplifier for amplifying a difference voltage between an input voltage and a reference voltage, a buffer amplifier connected to an output terminal of the operational amplifier, and a constant current source constituting an output stage of the operational amplifier comprising a first PNP transistor; And a negative feedback circuit comprising a parallel connection circuit of a capacitor and a capacitor, wherein a part of the output of the buffer amplifier is returned to the input side of the operational amplifier via the negative feedback circuit. A second PNP transistor is provided between the second PNP transistor and the output terminal of the second PNP.
An amplifier circuit comprising: a collector of a transistor connected to a collector of a first PNP transistor; a base connected to an output terminal of the buffer amplifier; and an emitter grounded. 3. An operational amplifier for amplifying a difference voltage between an input voltage and a reference voltage, a buffer amplifier connected to an output terminal of the operational amplifier, and a constant current source constituting an output stage of the operational amplifier including a PNP transistor; A negative feedback circuit comprising a parallel connection circuit of capacitors, and an amplifier circuit for returning a part of the output of the buffer amplifier to the input side of the operational amplifier via the negative feedback circuit. An amplifier circuit, comprising: an NPN transistor provided between the output terminal and an output terminal of the buffer amplifier; a collector and a base of the NPN transistor connected to a collector of the PNP transistor; 4. An output terminal of the operational amplifier is connected to a plurality of buffer amplifiers selectable by a switch circuit, and the negative feedback circuit is provided between an output terminal of each buffer amplifier and an input terminal of the operational amplifier. The amplifier circuit according to any one of claims 1 to 3, further comprising: 5. The amplifier circuit according to claim 1, wherein said resistor constituting said negative feedback circuit is formed on a LOCOS oxide film on a semiconductor substrate. 6. The amplifier circuit according to claim 1, wherein said capacitor constituting said negative feedback circuit is formed on a LOCOS oxide film on a semiconductor substrate. 7. The capacitor constituting the negative feedback circuit is formed by connecting two capacitors formed on the LOCOS oxide film in series on the semiconductor substrate on the LOCOS oxide film side. The amplifier circuit according to claim 6, wherein 8. The amplifier circuit according to claim 1, wherein an input wiring to said operational amplifier is formed on a LOCOS oxide film on a semiconductor substrate. 9. The amplifier circuit according to claim 1, wherein a light-shielding metal is applied to a portion of the semiconductor substrate other than on an input wiring to the operational amplifier.