JP2002110746A - Method for aligning ic of surface-mounting structure and printed wiring board - Google Patents
Method for aligning ic of surface-mounting structure and printed wiring boardInfo
- Publication number
- JP2002110746A JP2002110746A JP2000299477A JP2000299477A JP2002110746A JP 2002110746 A JP2002110746 A JP 2002110746A JP 2000299477 A JP2000299477 A JP 2000299477A JP 2000299477 A JP2000299477 A JP 2000299477A JP 2002110746 A JP2002110746 A JP 2002110746A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- mounting
- mounter
- carbon paper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子機器における
表面実装技術に係わるものであり、詳しくは表面実装構
造のＩＣをプリント配線板に装着する際の位置合わせの
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mounting technology for an electronic device, and more particularly to a method for positioning an IC having a surface mounting structure on a printed wiring board.
【０００２】[0002]
【従来の技術】電子機器の軽薄短小化を支える技術の一
つに表面実装技術がある。表面実装構造の電気部品を自
動装着装置（以下、マウンタと記す）を用いてプリント
配線板に装着する技術において、表面実装構造のＩＣを
プリント配線板に装着する際の、該ＩＣの電極とプリン
ト配線板のＩＣ用パッドとの位置合わせには次の方法が
ある。2. Description of the Related Art Surface mounting technology is one of the technologies that support the miniaturization of electronic devices. In a technology for mounting an electric component having a surface mount structure on a printed wiring board using an automatic mounting device (hereinafter, referred to as a mounter), an electrode and a print of the IC having the surface mount structure when the IC is mounted on the printed wiring board. There are the following methods for positioning the wiring board with the IC pads.
【０００３】第一の方法は、所定のマウンタを用いて該
ＩＣをプリント配線板に載置し、はんだリフロー等の工
法で該ＩＣの電極とプリント配線板のＩＣ用パッドを接
続する。然る後に、ＩＲ顕微鏡やＸ線検査装置を用い、
或いは接続面の断面観察により、接続の位置ずれの間隔
と方向を測り、マウンタの位置出しを補正する方法であ
る。In a first method, the IC is mounted on a printed wiring board using a predetermined mounter, and the electrodes of the IC are connected to the IC pads of the printed wiring board by a method such as solder reflow. Then, using an IR microscope or X-ray inspection device,
Alternatively, it is a method of measuring the interval and direction of the positional displacement of the connection by observing the cross section of the connection surface, and correcting the positioning of the mounter.
【０００４】第二の方法は、プリント配線板のＩＣ用パ
ッドに両面テープを貼り、所定のマウンタを用いて該Ｉ
Ｃをプリント配線板に載置する。然る後にＩＲ顕微鏡や
Ｘ線検査装置を用い、該ＩＣの電極とプリント配線板の
ＩＣ用パッドの位置ずれの間隔と方向を測り、マウンタ
の位置出しを補正するものである。A second method is to attach a double-sided tape to an IC pad of a printed wiring board and use a predetermined mounter to mount the IC on the IC pad.
C is placed on a printed wiring board. Thereafter, using an IR microscope or an X-ray inspection device, the distance and direction of the positional shift between the electrodes of the IC and the IC pads of the printed wiring board are measured, and the positioning of the mounter is corrected.
【０００５】[0005]
【発明が解決しようとする課題】表面実装技術は電子機
器生産における必須の技術であるが、マウンタ等の設備
の取得、要員の確保、工程の増加等による新たな負担も
求められている。表面実装構造のＩＣを装着する位置合
わせの方法を前述したが、ＩＲ顕微鏡やＸ線検査装置を
用いる方法は、これらの設備を備え、設備の操作に慣熟
した要員の確保が必要になる。また接続面の断面観察に
よる方法は、サンプルを切断し断面を研摩する前処理の
工程を必要とする。本発明は、表面実装構造のＩＣ装着
において、前記の負担を軽減する簡便な位置合わせ方法
を提供することにある。The surface mounting technology is an indispensable technology in the production of electronic equipment, but a new burden is required due to acquisition of equipment such as a mounter, securing of personnel, increase in the number of processes, and the like. The positioning method for mounting the IC having the surface mount structure has been described above. However, the method using the IR microscope or the X-ray inspection apparatus includes these facilities and requires personnel who are familiar with the operation of the facilities. The method of observing the cross section of the connection surface requires a pretreatment step of cutting the sample and polishing the cross section. An object of the present invention is to provide a simple positioning method for reducing the above-mentioned burden when mounting an IC having a surface mounting structure.
【０００６】[0006]
【課題を解決するための手段】表面実装構造のＩＣとプ
リント配線板の位置合わせ方法は、表面実装構造のＩＣ
をプリント配線板に装着する自動装着装置を用いた装着
における該ＩＣとプリント配線板との位置合わせの方法
であって、自動装着装置のＸＹテーブルに搬送したカー
ボン紙を載せたプリント配線板に、自動装着装置の装着
ヘッドにより該ＩＣを載置し、載置の押圧によりプリン
ト配線板に印された該ＩＣ電極のカーボン紙による転写
跡と、プリント配線板のＩＣ用パッドとの位置ずれを測
定して位置ずれの補正データを生成し、自動装着装置の
位置ずれ補正データとすることを特徴とする。SUMMARY OF THE INVENTION A method for aligning a surface-mounted IC with a printed wiring board is disclosed in US Pat.
A method of aligning the IC and the printed wiring board in mounting using an automatic mounting device for mounting the printed wiring board on a printed wiring board, wherein the carbon paper transported to the XY table of the automatic mounting device is placed on a printed wiring board. The IC is mounted by the mounting head of the automatic mounting device, and the displacement between the transfer mark of the IC electrode, which is marked on the printed wiring board by carbon paper due to the pressing of the mounting, and the IC pad of the printed wiring board is measured. Then, the correction data of the positional deviation is generated and used as the positional deviation correction data of the automatic mounting device.
【０００７】[0007]
【発明の実施の形態】本発明の一実施の形態を、図１乃
至図２の模式図を用いて説明する。同図は表面実装構造
のＩＣに、フリップチップ構造のＩＣを用いた実施例で
ある。なお本発明は、同図以外の表面実装構造のＩＣ及
びその他の表面実装部品にも容易に適用できることは言
うまでもない。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the schematic diagrams of FIGS. FIG. 1 shows an embodiment in which an IC having a flip-chip structure is used as an IC having a surface mounting structure. Needless to say, the present invention can be easily applied to an IC having a surface mounting structure other than that shown in FIG.
【０００８】図１の参照符号は、１はプリント配線板、
１１はプリント配線板１のＩＣ用パッド、２はフリップ
チップ構造のＩＣ、２１はＩＣ２の電極（バンプ）、３
はカーボン紙である。図２の参照符号は、図１に対応す
る部分は同図と同一の符号を用い、新たな３１は電極２
１の転写跡である。なお、転写跡３１については後述す
る。1 is a printed wiring board,
11 denotes an IC pad of the printed wiring board 1, 2 denotes an IC having a flip-chip structure, 21 denotes an electrode (bump) of the IC 2, 3
Is carbon paper. The reference numerals in FIG. 2 are the same as those in FIG. 1 for the portions corresponding to FIG.
This is the transfer trace of No. 1. The transfer trace 31 will be described later.
【０００９】図１−ａ乃至図１−ｂは第１の手順の要部
を示し、所定の位置に配置された部材の断面（図１−
ａ）と上面図（図１−ｂ）である。第１の手順（図１−
ａ乃至図１−ｂ参照）で、プリント配線板１のＩＣ２を
装着する部分にカーボン紙３を載せる。カーボン紙３
は、カーボン面がプリント配線板１と接し、またカーボ
ン紙３が脱落しないように、図示しない少量の接着剤を
プリント配線板１のカーボン紙を載せる部分に事前に塗
布しておく。FIGS. 1A and 1B show a main part of the first procedure, and show a cross section (FIG. 1) of a member arranged at a predetermined position.
a) and a top view (FIG. 1-b). The first procedure (FIG. 1)
a to FIG. 1B), the carbon paper 3 is placed on the portion of the printed wiring board 1 where the IC 2 is to be mounted. Carbon paper 3
In order to prevent the carbon surface from being in contact with the printed wiring board 1 and the carbon paper 3 from falling off, a small amount of an adhesive (not shown) is applied in advance to the portion of the printed wiring board 1 on which the carbon paper is to be placed.
【００１０】第２の手順で、前記第１の手順によるプリ
ント配線板１をマウンタのＸＹテーブルに搬送し位置決
めする。In a second procedure, the printed wiring board 1 from the first procedure is transported to an XY table of a mounter and positioned.
【００１１】図１−ｃ乃至図１−ｄは第３の手順の要部
を示し、所定の位置に配置された部材の断面（図１−
ｃ）と上面図（図１−ｄ）である。第３の手順（図１−
ｃ乃至図１−ｄ参照）で、ＩＣ２をマウンタの装着ヘッ
ドで吸着し、ＸＹテーブルにあるプリント配線板１の所
定の位置に載置する。この時、ＩＣ２の電極２１はカー
ボン紙３を押圧し、プリント配線板１の表面に電極２１
の位置を示す転写跡３１が印される。FIGS. 1C to 1D show a main part of the third procedure, and show a cross section of a member arranged at a predetermined position (FIG.
c) and a top view (FIG. 1-d). The third procedure (FIG. 1)
c to FIG. 1-d), the IC 2 is sucked by the mounting head of the mounter, and is mounted at a predetermined position of the printed wiring board 1 on the XY table. At this time, the electrode 21 of the IC 2 presses the carbon paper 3 and the electrode 21
A transfer mark 31 indicating the position is marked.
【００１２】図２は、プリント配線板１のＩＣ用パッド
１１と、この近傍に印されたカーボン紙３によるＩＣ２
の電極２１の転写跡３１を模式的に示している。第４の
手順（図２参照）で、プリント配線板１に装着するＩＣ
２の電極２１とプリント配線板１のＩＣ用パッド１１の
相対的な位置ずれの補正データを生成する。拡大鏡等に
より転写跡３１の中心とＩＣ用パッド１１の中心の偏差
をＸ軸とＹ軸について測定する。この測定値により位置
ずれの補正データを生成し、マウンタに入力する。FIG. 2 shows an IC pad 11 of a printed wiring board 1 and an IC 2 made of carbon paper 3 marked in the vicinity thereof.
The transfer trace 31 of the electrode 21 of FIG. In the fourth procedure (see FIG. 2), an IC to be mounted on the printed wiring board 1
The correction data of the relative displacement between the second electrode 21 and the IC pad 11 of the printed wiring board 1 is generated. The deviation between the center of the transfer mark 31 and the center of the IC pad 11 is measured for the X axis and the Y axis using a magnifying glass or the like. Correction data of the displacement is generated based on the measured values, and is input to the mounter.
【００１３】[0013]
【発明の効果】本発明は、実施の形態として一例を述べ
たとおり、表面実装構造のＩＣとプリント配線板の位置
合わせにおいて、次の効果を奏するものである。本発明
によれば、ＩＲ顕微鏡やＸ線顕微鏡等の機器を用いず、
また断面観察の工程も不要になるため、極めて簡便にＩ
Ｃとプリント配線板の位置合わせを行なうことができ
る。さらに、カーボン紙の印すＩＣ電極の転写跡の濃淡
によって、ＩＣ電極とプリント配線板の平面性を知るこ
ともでき、接続の信頼性改善に寄与することにもなる。As described above, the present invention has the following effects in the alignment between a surface-mounted IC and a printed wiring board. According to the present invention, without using equipment such as an IR microscope or an X-ray microscope,
In addition, since the step of observing the cross section is not required, the I
C and the printed wiring board can be aligned. Further, the flatness of the IC electrode and the printed wiring board can be known from the density of the transfer trace of the IC electrode marked by the carbon paper, which contributes to the improvement of connection reliability.
【図１】図１は本発明の一実施形態の模式図であり、本
発明による位置合わせ方法の要部を示す。FIG. 1 is a schematic view of an embodiment of the present invention, showing a main part of an alignment method according to the present invention.
【図２】図２は、プリント配線板に印されたカーボン紙
による表面実装構造のＩＣ電極の転写跡と、プリント配
線板のＩＣ用パッドとの位置ずれを模式的に示した図で
ある。FIG. 2 is a diagram schematically showing a transfer trace of an IC electrode of a surface mounting structure made of carbon paper marked on a printed wiring board and a positional shift between an IC pad of the printed wiring board.
１ プリント配線板 １１ ＩＣ用パッド ２ フリップチップ構造のＩＣ ２１ 電極（バンプ） ３ カーボン紙 ３１ 転写跡 DESCRIPTION OF SYMBOLS 1 Printed wiring board 11 IC pad 2 IC of flip chip structure 21 Electrode (bump) 3 Carbon paper 31 Transfer mark
Claims (1)
装着する自動装着装置を用いた装着における該ＩＣとプ
リント配線板との位置合わせの方法であって、自動装着
装置のＸＹテーブルに搬送したカーボン紙を載せたプリ
ント配線板に、自動装着装置の装着ヘッドにより該ＩＣ
を載置し、載置の押圧によりプリント配線板に印された
該ＩＣ電極のカーボン紙による転写跡と、プリント配線
板のＩＣ用パッドとの位置ずれを測定して位置ずれの補
正データを生成し、自動装着装置の位置ずれ補正データ
とすることを特徴とした表面実装構造のＩＣとプリント
配線板の位置合わせ方法。1. A method for aligning an IC having a surface mounting structure with a printed wiring board in mounting using an automatic mounting apparatus for mounting the IC on a printed wiring board, wherein the IC is transferred to an XY table of the automatic mounting apparatus. The IC is mounted on a printed wiring board on which carbon paper is mounted by using a mounting head of an automatic mounting device.
Is placed, and the imprint of the IC electrode marked on the printed wiring board by the pressing of the mounting paper by the carbon paper and the misalignment between the printed circuit board and the IC pad are measured to generate misregistration correction data. A method for aligning an IC having a surface-mounted structure with a printed wiring board, the data being used as positional deviation correction data for an automatic mounting device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000299477A JP2002110746A (en) | 2000-09-29 | 2000-09-29 | Method for aligning ic of surface-mounting structure and printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000299477A JP2002110746A (en) | 2000-09-29 | 2000-09-29 | Method for aligning ic of surface-mounting structure and printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002110746A true JP2002110746A (en) | 2002-04-12 |
Family
ID=18781278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000299477A Pending JP2002110746A (en) | 2000-09-29 | 2000-09-29 | Method for aligning ic of surface-mounting structure and printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002110746A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106679547A (en) * | 2016-12-27 | 2017-05-17 | 浙江超威创元实业有限公司 | Method for detecting parallelism of seals |
| US10720365B2 (en) | 2016-07-20 | 2020-07-21 | Samsung Electronics Co., Ltd. | Method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby |
| CN114924405A (en) * | 2022-05-05 | 2022-08-19 | 大连藏龙光电子科技有限公司 | Equipment calibration method applied to CCD microscope mounting product |
| CN117878015A (en) * | 2024-01-04 | 2024-04-12 | 深圳维盛半导体科技有限公司 | Parallelism adjustment method for flip chip |
-
2000
- 2000-09-29 JP JP2000299477A patent/JP2002110746A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10720365B2 (en) | 2016-07-20 | 2020-07-21 | Samsung Electronics Co., Ltd. | Method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby |
| CN106679547A (en) * | 2016-12-27 | 2017-05-17 | 浙江超威创元实业有限公司 | Method for detecting parallelism of seals |
| CN106679547B (en) * | 2016-12-27 | 2019-01-11 | 浙江超威创元实业有限公司 | A method of the detection end socket depth of parallelism |
| CN114924405A (en) * | 2022-05-05 | 2022-08-19 | 大连藏龙光电子科技有限公司 | Equipment calibration method applied to CCD microscope mounting product |
| CN114924405B (en) * | 2022-05-05 | 2024-05-07 | 大连藏龙光电子科技有限公司 | Device calibration method applied to CCD microscope mounting product |
| CN117878015A (en) * | 2024-01-04 | 2024-04-12 | 深圳维盛半导体科技有限公司 | Parallelism adjustment method for flip chip |
| CN117878015B (en) * | 2024-01-04 | 2024-10-22 | 深圳维盛半导体科技有限公司 | Parallelism adjustment method for flip chip |
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