JP2002110735A - Method for mounting flip-chip and plasma processing apparatus - Google Patents

Method for mounting flip-chip and plasma processing apparatus

Info

Publication number
JP2002110735A
JP2002110735A JP2000293044A JP2000293044A JP2002110735A JP 2002110735 A JP2002110735 A JP 2002110735A JP 2000293044 A JP2000293044 A JP 2000293044A JP 2000293044 A JP2000293044 A JP 2000293044A JP 2002110735 A JP2002110735 A JP 2002110735A
Authority
JP
Japan
Prior art keywords
plasma
gas
semiconductor chip
mounting substrate
reaction tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000293044A
Other languages
Japanese (ja)
Other versions
JP3937711B2 (en
Inventor
Noriyuki Yasuike
則之 安池
Masaharu Yasuda
正治 安田
Koji Sawada
康志 澤田
Kazunari Kuzuhara
一功 葛原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2000293044A priority Critical patent/JP3937711B2/en
Publication of JP2002110735A publication Critical patent/JP2002110735A/en
Application granted granted Critical
Publication of JP3937711B2 publication Critical patent/JP3937711B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8191—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for mounting a flip-chip that enables reinforcement effects of a bump and enables high sealing property of a gap between the semiconductor chip and a mounting substrate. SOLUTION: The semiconductor chip 14 and the mounting substrate 15 are connected with a bump 16. Then, by supplying plasma 13 blew by the plasma processing apparatus A into the gap 30 between the semiconductor chip 14 and the mounting substrate 15, the surface of semiconductor chip 14 and the surface of mounting substrate 15 and the surface of bump 16 are cleaned. Then, an underfill material is injected. Contaminations such as organic substances, by which a flow of the underfill material to be injected into the gap 30 is obstructed at injecting the underfill material, and by which an adhesion of the underfill material is obstructed, are removed by plasma processing.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、実装基板の表面に
半導体チップを実装する際に用いられるフリップチップ
実装方法及びこのフリップチップ実装方法の際に用いら
れるプラズマ処理装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip mounting method used for mounting a semiconductor chip on the surface of a mounting substrate and a plasma processing apparatus used for the flip-chip mounting method.

【０００２】[0002]

【従来の技術】従来より、半導体チップ（半導体素子）
を実装基板に実装することによって半導体パッケージ
（半導体装置）を製造することが行われているが、半導
体チップを実装基板に実装するにあたっては、半導体パ
ッケージの小型化などの目的でフリップチップ実装方法
が用いられている。この実装方法は、例えば、半導体チ
ップの表面の電極上にバンプを形成した後、このバンプ
と実装基板の表面の電極とを位置合わせして接触させた
状態で実装基板の表面に半導体チップを載置し、バンプ
を加熱溶融させた後固化することによって、半導体チッ
プの電極と実装基板の電極とを電気的に接続するように
するものである。2. Description of the Related Art Conventionally, semiconductor chips (semiconductor elements)
A semiconductor package (semiconductor device) is manufactured by mounting a semiconductor chip on a mounting board. When mounting a semiconductor chip on a mounting board, a flip-chip mounting method is used to reduce the size of the semiconductor package. Used. In this mounting method, for example, after forming a bump on an electrode on the surface of a semiconductor chip, the semiconductor chip is mounted on the surface of the mounting substrate in a state where the bump and the electrode on the surface of the mounting substrate are aligned and contacted. The bumps are heated, melted, and then solidified to electrically connect the electrodes of the semiconductor chip and the electrodes of the mounting board.

【０００３】また、上記のようなフリップチップ実装方
法において、アンダーフィルが行われている。アンダー
フィルは実装基板とこれに実装された半導体チップとの
間に形成される間隙を樹脂封止することであり、アンダ
ーフィルにより間隙にアンダーフィル材（封止樹脂）を
形成することによって、バンプを保護することができ、
アンダーフィル材でバンプを補強して半導体チップと実
装基板の接合強度を高めたり、アンダーフィル材で間隙
を密閉して大気中の水分が間隙に侵入するのを防止して
半導体パッケージの耐湿性を向上させたりすることがで
きるものである。In the flip chip mounting method as described above, underfill is performed. Underfill is to seal the gap formed between the mounting substrate and the semiconductor chip mounted thereon with resin, and by forming an underfill material (sealing resin) in the gap by underfill, a bump is formed. Can be protected,
The underfill material reinforces the bumps to increase the bonding strength between the semiconductor chip and the mounting board, and the underfill material closes the gap to prevent moisture in the air from entering the gap and improve the moisture resistance of the semiconductor package. It can be improved.

【０００４】[0004]

【発明が解決しようとする課題】しかし、従来のフリッ
プチップ実装方法では、半導体チップの表面や実装基板
の表面やバンプの表面に有機物（例えば、バンプや回路
等を形成する際に用いる銀ペースト材に含まれている有
機物成分や実装基板を洗浄液（例えば、アセトンなど）
で洗浄したときに実装基板の表面の残存する洗浄液な
ど）等が付着して汚染されているために、実装基板と半
導体チップの間の間隙においてアンダーフィル材が流れ
にくくなってアンダーフィル材の未注入部分が生じた
り、半導体チップの表面や実装基板の表面やバンプの表
面に対するアンダーフィル材の密着性が低くなったりす
ることがあり、これにより、アンダーフィル材によるバ
ンプの補強や間隙の密閉が不十分になることがあった。However, in the conventional flip chip mounting method, an organic material (for example, a silver paste material used for forming bumps, circuits, etc.) is formed on the surface of a semiconductor chip, the surface of a mounting substrate, or the surface of a bump. Cleaning liquid (for example, acetone, etc.)
Cleaning liquid remaining on the surface of the mounting substrate, etc.) adheres and is contaminated, so that the underfill material hardly flows in the gap between the mounting substrate and the semiconductor chip, and the unfilled underfill material Injected parts may occur, or the adhesion of the underfill material to the surface of the semiconductor chip, the surface of the mounting substrate, or the surface of the bump may be reduced. Sometimes it was not enough.

【０００５】本発明は上記の点に鑑みてなされたもので
あり、バンプの補強効果や半導体チップと実装基板の間
隙の密閉性を高くすることができるフリップチップ実装
方法を提供することを目的とするものである。The present invention has been made in view of the above points, and an object of the present invention is to provide a flip chip mounting method capable of enhancing the effect of reinforcing bumps and sealing the gap between a semiconductor chip and a mounting substrate. Is what you do.

【０００６】また、本発明はフリップチップ実装方法に
好適に使用することができるプラズマ処理装置を提供す
ることを目的とするものである。Another object of the present invention is to provide a plasma processing apparatus which can be suitably used for a flip chip mounting method.

【０００７】[0007]

【課題を解決するための手段】本発明の請求項１に係る
フリップチップ実装方法は、半導体チップ１４と実装基
板１５をバンプ１６により接合した後、プラズマ処理装
置Ａから吹き出されるプラズマ１３を半導体チップ１４
と実装基板１５の間隙３０に供給することによって半導
体チップ１４の表面と実装基板１５の表面とバンプ１６
の表面を洗浄し、この後、アンダーフィルを行うことを
特徴とするものである。According to a first aspect of the present invention, there is provided a flip chip mounting method, comprising: bonding a semiconductor chip to a mounting substrate by bumps; Chip 14
The surface of the semiconductor chip 14, the surface of the mounting substrate 15 and the bump 16
Is cleaned, and then underfill is performed.

【０００８】本発明の請求項２に係るプラズマ処理装置
Ａは、請求項１に記載のフリップチップ実装方法に用い
るプラズマ処理装置Ａであって、筒状の反応管７の片側
を吹き出し口１２として開放し、反応管７の外側に複数
個の電極９、１０を配設し、希ガスを含むプラズマ生成
用ガス８を反応管７に導入すると共に電極９、１０間に
電圧を印加することによって大気圧近傍の圧力下で反応
管７内に放電を発生させ、放電により反応管７内に生成
されたプラズマ１３を吹き出し口１２から吹き出すこと
を特徴とするものである。[0008] A plasma processing apparatus A according to a second aspect of the present invention is the plasma processing apparatus A used in the flip chip mounting method according to the first aspect, wherein one side of a cylindrical reaction tube 7 is used as an outlet 12. Opening, disposing a plurality of electrodes 9 and 10 outside the reaction tube 7, introducing a rare gas-containing plasma generating gas 8 into the reaction tube 7, and applying a voltage between the electrodes 9 and 10. Discharge is generated in the reaction tube 7 under a pressure close to the atmospheric pressure, and plasma 13 generated in the reaction tube 7 by the discharge is blown out from the blowout port 12.

【０００９】また、本発明の請求項３に係るプラズマ処
理装置Ａは、請求項２の構成に加えて、プラズマ生成用
ガス８を希ガスと酸素ガスの混合ガスとし、プラズマ生
成用ガス８に占める酸素ガスの混合比率を２〜５ｖｏｌ
％にすることを特徴とするものである。A plasma processing apparatus A according to a third aspect of the present invention, in addition to the configuration of the second aspect, uses the plasma generating gas 8 as a mixed gas of a rare gas and an oxygen gas, The mixing ratio of the occupied oxygen gas is 2 to 5 vol.
%.

【００１０】また、本発明の請求項４に係るプラズマ処
理装置Ａは、請求項２の構成に加えて、プラズマ生成用
ガス８を希ガスと水素ガスの混合ガスとし、プラズマ生
成用ガス８に占める水素ガスの混合比率を０．３〜３ｖ
ｏｌ％にすることを特徴とするものである。A plasma processing apparatus A according to a fourth aspect of the present invention, in addition to the configuration of the second aspect, uses the plasma generating gas 8 as a mixed gas of a rare gas and a hydrogen gas, The mixing ratio of the occupied hydrogen gas is 0.3-3v
ol%.

【００１１】[0011]

【発明の実施の形態】以下、本発明の実施の形態を説明
する。Embodiments of the present invention will be described below.

【００１２】図２に本発明のプラズマ処理装置Ａの一例
を示す。このプラズマ処理装置Ａは、反応管７の外側に
複数個（一対）の電極９、１０を上下に対向させて配置
することによって形成されており、電極９、１０の間に
対応する位置において反応管７内には放電空間２１が形
成されている。また、電極９、１０はインピーダンス整
合回路（図示省略）を介して電源１１と電気的に接続さ
れている。尚、電極９、１０はそれぞれ一個ずつ以上あ
れば何個あっても良い。そして、本発明のプラズマ処理
装置Ａは反応管７からプラズマ１３を吹き出す吹き出し
型のプラズマ処理装置Ａである。FIG. 2 shows an example of a plasma processing apparatus A according to the present invention. The plasma processing apparatus A is formed by arranging a plurality of (a pair of) electrodes 9 and 10 on the outside of a reaction tube 7 so as to face each other up and down. A discharge space 21 is formed in the tube 7. The electrodes 9 and 10 are electrically connected to a power supply 11 via an impedance matching circuit (not shown). The number of the electrodes 9 and 10 may be any number as long as the number is one or more. The plasma processing apparatus A of the present invention is a blow-out type plasma processing apparatus A that blows out the plasma 13 from the reaction tube 7.

【００１３】反応管７は高融点の誘電体材料（絶縁材
料）で扁平形状の略角筒状に形成されるものである。反
応管７を構成する誘電体材料の誘電率は放電空間２１に
おけるプラズマの低温化の重要な要素であって、具体的
には誘電体材料として石英、アルミナ、イットリア部分
安定化ジルコニウムなどのガラス質材料やセラミック材
料などを例示することができる。また、反応管７の上面
はガス導入口５１として略全面に亘って開放されている
と共に反応管７の下面は吹き出し口１２として略全面に
亘って開放されている。従って、この吹き出し口１２は
反応管７の幅広方向と平行方向に長くて幅の狭いスリッ
ト形状に形成されており、これにより、吹き出し口１２
を小さい孔（スポット形状）に形成する場合に比べて、
広い面積を一度に処理することができるものである。上
記の吹き出し口１２及びガス導入口５１は反応管７内の
放電空間２１と連通して形成されている。尚、反応管７
は円筒状に形成しても良い。The reaction tube 7 is made of a high melting point dielectric material (insulating material) and is formed in a flat, substantially rectangular tube shape. The dielectric constant of the dielectric material constituting the reaction tube 7 is an important factor in lowering the temperature of the plasma in the discharge space 21. Specifically, the dielectric material is a vitreous material such as quartz, alumina, or yttria partially stabilized zirconium. Examples include materials and ceramic materials. In addition, the upper surface of the reaction tube 7 is opened almost entirely as a gas inlet 51, and the lower surface of the reaction tube 7 is opened almost entirely as an outlet 12. Therefore, the outlet 12 is formed in a slit shape which is long and narrow in a direction parallel to the wide direction of the reaction tube 7, and thereby, the outlet 12
Compared to forming a small hole (spot shape)
A large area can be processed at a time. The outlet 12 and the gas inlet 51 are formed so as to communicate with the discharge space 21 in the reaction tube 7. The reaction tube 7
May be formed in a cylindrical shape.

【００１４】電極９、１０は、例えば、銅、アルミニウ
ム、真鍮、耐食性の高いステンレス鋼（ＳＵＳ３０４な
ど）などの導電性の金属材料で形成することができる。
また、電極９、１０はリング状（環状）に形成されてい
るが、その内周形状は反応管７の外周形状に合致するよ
うに形成されている。そして、電極９、１０の内側に反
応管７を挿着することによって、反応管７の外周に電極
９、１０を取り付けることができる。この時、各電極
９、１０の内周面は反応管７の外周面に全周に亘って接
触させるものであり、これにより、電極９、１０を反応
管７の外周面に全周に亘って接触させない場合に比べ
て、電極９、１０と反応管７の接触面積が大きくなって
接触性を向上させることができ、電極９、１０間に電圧
を印加した際に放電空間２１に放電が発生しやすくなっ
てプラズマ１３の生成効率を高めることができるもので
ある。また、反応管７の外側に電極９、１０を設けるこ
とによって、電極９、１０がプラズマ１３によるスパッ
タリングや腐食作用を受けないようにすることができ、
電極９、１０のスパッタリングにより生じる汚染物質で
実装基板１５や半導体チップ１４やバンプ１６が汚染さ
れないようにすることができると共に電極９、１０の長
寿命化を図ることができるものである。尚、電極９、１
０の間隔はプラズマを安定に生成するために３〜２０ｍ
ｍに設定するのが好ましい。The electrodes 9 and 10 can be formed of a conductive metal material such as copper, aluminum, brass, and stainless steel having high corrosion resistance (such as SUS304).
The electrodes 9 and 10 are formed in a ring shape (annular shape), and the inner peripheral shape is formed so as to match the outer peripheral shape of the reaction tube 7. Then, by inserting the reaction tube 7 inside the electrodes 9, 10, the electrodes 9, 10 can be attached to the outer periphery of the reaction tube 7. At this time, the inner peripheral surface of each of the electrodes 9 and 10 is brought into contact with the outer peripheral surface of the reaction tube 7 over the entire periphery, whereby the electrodes 9 and 10 are brought into contact with the outer peripheral surface of the reaction tube 7 over the entire periphery. The contact area between the electrodes 9 and 10 and the reaction tube 7 is increased as compared with the case where the electrodes 9 and 10 are not brought into contact with each other, so that the contact property can be improved. The plasma 13 is easily generated, and the generation efficiency of the plasma 13 can be increased. In addition, by providing the electrodes 9 and 10 outside the reaction tube 7, the electrodes 9 and 10 can be prevented from being subjected to sputtering or corrosive action by the plasma 13,
The mounting substrate 15, the semiconductor chip 14, and the bumps 16 can be prevented from being contaminated by contaminants generated by sputtering the electrodes 9 and 10, and the life of the electrodes 9 and 10 can be extended. The electrodes 9, 1
The interval of 0 is 3 to 20 m in order to generate plasma stably.
It is preferable to set m.

【００１５】電源１１としては、高周波電圧またはパル
ス電圧を発生し、且つ放電空間２１でプラズマ１３を連
続的に生成するのに必要な電圧を電極９、１０間に印加
することができるものを用いる。高周波電圧は休止時間
（電圧が一定で定常状態になっている時間）が無いかほ
とんど無い電圧波形（例えば、正弦波）を有するもので
あり、パルス電圧は休止時間のある電圧波形を有するも
のである。また、放電空間２１でプラズマ１３を連続的
に生成するのに必要な電圧は反応管７の厚みや放電空間
２１の大きさ等によって異なるので適宜設定すればよい
が、例えば、０．５〜５ｋＶに設定することができる。As the power supply 11, a power supply capable of generating a high-frequency voltage or a pulse voltage and applying a voltage necessary for continuously generating the plasma 13 in the discharge space 21 between the electrodes 9 and 10 is used. . The high-frequency voltage has a voltage waveform (for example, a sine wave) having no or almost no pause time (time during which the voltage is constant and in a steady state), and the pulse voltage has a voltage waveform having a pause time. is there. Further, the voltage required for continuously generating the plasma 13 in the discharge space 21 may be appropriately set because it varies depending on the thickness of the reaction tube 7 and the size of the discharge space 21, for example, 0.5 to 5 kV. Can be set to

【００１６】電極９、１０間に印加する電圧として高周
波電圧を用いると、電源１１として用いる電源装置の構
造を簡素化することができると共に電極９、１０間に印
加する電圧の周波数や放電空間２１に供給する電力の大
きさ等を容易に調整することができるので好ましい。ま
た、電極９、１０間に印加する電圧としてパルス電圧を
用いると、電源１１として用いる電源装置の構造が複雑
化するものの、電界による荷電粒子の加速が無い時間が
あるので、荷電粒子が放電空間２１に滞在する時間が長
くなり、放電空間２１における放電が容易に起こりやす
くなって放電効率が上がりプラズマ１３を容易に生成す
ることができるので好ましい。特に、Ｈｅを放電空間２
１に導入しない場合は、Ｈｅを放電空間２１に導入する
場合よりも絶縁破壊電圧が高くなり、放電が発生しにく
くなるので、パルス電圧を用いるのが好ましい。When a high frequency voltage is used as the voltage applied between the electrodes 9 and 10, the structure of the power supply device used as the power supply 11 can be simplified, and the frequency of the voltage applied between the electrodes 9 and 10 and the discharge space 21 This is preferable because the amount of power supplied to the device can be easily adjusted. When a pulse voltage is used as the voltage applied between the electrodes 9 and 10, the structure of the power supply device used as the power supply 11 becomes complicated, but there is a time during which the charged particles are not accelerated by the electric field. This is preferable because the time of staying in the discharge space 21 is prolonged, discharge in the discharge space 21 is easily caused, the discharge efficiency is increased, and the plasma 13 can be easily generated. In particular, He is supplied to the discharge space 2.
In the case where He is not introduced into 1, the breakdown voltage becomes higher than in the case where He is introduced into the discharge space 21, and it becomes difficult for discharge to occur. Therefore, it is preferable to use a pulse voltage.

【００１７】プラズマ生成用ガス（図２に矢印で示す）
８としては希ガスと酸素ガスあるいは希ガスと水素ガス
の混合ガスを用いる。希ガスと酸素ガスの混合ガスを用
いた場合は有機物の除去をおこなうことができ、希ガス
と水素ガスの混合ガスを用いた場合は有機物の除去と酸
化物（膜）を還元することにより酸化物の除去をおこな
うことができるものである。そして、このようにプラズ
マ生成用ガス８に酸素ガスあるいは水素ガスを含有させ
ると、プラズマ１３中の電子を酸素ガスあるいは水素ガ
スが吸着して自ら負イオンとなり、プラズマ１３中の電
子密度を下げる作用をするものである。一般的に、電子
の方がイオンに比べると移動度が大きくまた寿命もイオ
ンより長いので、本発明のようにジェット状のプラズマ
（プラズマジェット）を吹き出してプラズマ処理を行う
場合においては、チャージアップダメージは電子によっ
て主に引き起こされることが確認されている。Gas for plasma generation (indicated by an arrow in FIG. 2)
As 8, a mixed gas of a rare gas and an oxygen gas or a rare gas and a hydrogen gas is used. When a mixed gas of a rare gas and an oxygen gas is used, organic substances can be removed. When a mixed gas of a rare gas and a hydrogen gas is used, organic substances can be removed and oxidized by reducing an oxide (film). The object can be removed. When the oxygen gas or the hydrogen gas is contained in the plasma generating gas 8 as described above, the oxygen gas or the hydrogen gas adsorbs the electrons in the plasma 13 and becomes a negative ion by itself, thereby reducing the electron density in the plasma 13. It is what you do. In general, electrons have higher mobility than ions and longer lifetime than ions. Therefore, when plasma processing is performed by blowing out a jet-like plasma (plasma jet) as in the present invention, charge-up is caused. Damage has been found to be primarily caused by electrons.

【００１８】そこで、本発明では酸素ガスあるいは水素
ガスをプラズマ生成用ガス８に加えることによって、電
子が実装基板１５や半導体チップ１４やバンプ１６に到
達するまでに酸素ガスや水素ガスで吸着して消滅させる
ことができるようにしたものであり、これにより、電子
による半導体チップ１４へのチャージアップを少なくす
ることができるものである。また、酸素や水素の負イオ
ンは実装基板１５や半導体チップ１４やバンプ１６に到
達するまでに消滅するので、チャージアップに影響を及
ぼさない。このように本発明ではチャージアップの原因
である半導体チップ１４に到達する電子を減らすことが
できるので、半導体チップ１４をバンプ１６により実装
基板１５に接合した後にプラズマ処理した場合でも、半
導体チップ１４にチャージアップダメージの発生を抑え
て半導体チップ１４の特性不良を低減できるものであ
る。Therefore, in the present invention, by adding an oxygen gas or a hydrogen gas to the plasma generating gas 8, the electrons are adsorbed by the oxygen gas or the hydrogen gas until they reach the mounting substrate 15, the semiconductor chip 14 and the bumps 16. The semiconductor chip 14 can be made to disappear, so that the charge-up of the semiconductor chip 14 by electrons can be reduced. Further, negative ions of oxygen and hydrogen disappear before reaching the mounting substrate 15, the semiconductor chip 14, and the bumps 16, and thus do not affect the charge-up. As described above, according to the present invention, electrons reaching the semiconductor chip 14 that causes charge-up can be reduced. Therefore, even when the semiconductor chip 14 is bonded to the mounting substrate 15 by the bumps 16 and then subjected to plasma processing, the semiconductor chip 14 It is possible to reduce the characteristic failure of the semiconductor chip 14 by suppressing the occurrence of charge-up damage.

【００１９】ここで、チャージアップダメージを説明す
る。図３は半導体チップ１４の断面図であって、シリコ
ン単結晶基板１上に形成されたゲート電極２の概略図で
ある。チャージアップは、プラズマ中の荷電粒子３が半
導体チップ１４のゲート電極２と電気的に接続された配
線６に注入され、配線６とゲート電極２を介してゲート
酸化膜５に蓄積されることで起こる現象である。配線６
上には半導体チップ１４の表面を保護するためにパッシ
ベーション膜４が形成されているが、配線６のバンプ１
６が形成される部分であるボンディング部２０に対応す
る位置にはパッシベーション膜４が形成されておらず、
クリーニングなどのプラズマ処理時にはこのボンディン
グ部２０が直接プラズマに曝されることになって、ボン
ディング部２０がプラズマ中の荷電粒子３を拾うアンテ
ナの役割を果たすのである。Here, the charge-up damage will be described. FIG. 3 is a cross-sectional view of the semiconductor chip 14, which is a schematic view of the gate electrode 2 formed on the silicon single crystal substrate 1. The charge-up is performed by injecting the charged particles 3 in the plasma into the wiring 6 electrically connected to the gate electrode 2 of the semiconductor chip 14 and accumulating in the gate oxide film 5 via the wiring 6 and the gate electrode 2. It is a phenomenon that occurs. Wiring 6
A passivation film 4 is formed thereon to protect the surface of the semiconductor chip 14.
The passivation film 4 is not formed at a position corresponding to the bonding portion 20 where the film 6 is formed.
During plasma processing such as cleaning, the bonding portion 20 is directly exposed to plasma, and the bonding portion 20 plays a role of an antenna for picking up charged particles 3 in the plasma.

【００２０】そして、上記のチャージアップ現象が過度
に進むと、やがてゲート酸化膜５の物理特性に影響を及
ぼす。具体的には、ゲート酸化膜５の物理特性が変化し
た結果、ＭＯＳＦＥＴ（電解効果トランジスタ）の場合
にはｇｍ（コンダクタンス）やＶｔｈ（スレッシュホル
ド電圧）などが変動する。これがチャージアップダメー
ジと呼ばれる現象である。If the above-mentioned charge-up phenomenon proceeds excessively, the physical characteristics of the gate oxide film 5 will be affected. Specifically, as a result of a change in the physical characteristics of the gate oxide film 5, in the case of a MOSFET (field effect transistor), gm (conductance), Vth (threshold voltage), and the like change. This is a phenomenon called charge-up damage.

【００２１】プラズマ生成用ガス８として希ガスと酸素
ガスの混合ガスを用いる場合は、反応管７に導入される
プラズマ生成用ガス８の全体（希ガスと酸素ガスの合計
量）に占める酸素ガスの混合比率（プラズマ生成用ガス
８中の酸素濃度）は２〜５ｖｏｌ％に設定するのが好ま
しい。また、プラズマ生成用ガス８として希ガスと水素
ガスの混合ガスを用いる場合は、反応管７に導入される
プラズマ生成用ガス８の全体（希ガスと水素ガスの合計
量）に占める水素ガスの混合比率（プラズマ生成用ガス
８中の水素濃度）は０．３〜３ｖｏｌ％に設定するのが
好ましい。When a mixed gas of a rare gas and an oxygen gas is used as the plasma generating gas 8, the oxygen gas occupies the entire plasma generating gas 8 introduced into the reaction tube 7 (total amount of the rare gas and the oxygen gas). (Oxygen concentration in the plasma generation gas 8) is preferably set to 2 to 5 vol%. When a mixed gas of a rare gas and a hydrogen gas is used as the plasma generating gas 8, the hydrogen gas occupies the entire plasma generating gas 8 (total amount of the rare gas and the hydrogen gas) introduced into the reaction tube 7. The mixing ratio (the hydrogen concentration in the plasma generating gas 8) is preferably set to 0.3 to 3% by volume.

【００２２】プラズマ生成用ガス８に占める酸素ガスの
混合比率が２ｖｏｌ％未満であったり、プラズマ生成用
ガス８に占める水素ガスの混合比率が０．３ｖｏｌ％未
満であったりすると、酸素ガスや水素ガスによる電子の
吸着効果が低くなってチャージアップダメージを低減さ
せることができない恐れがあり、プラズマ生成用ガスに
占める酸素ガスの混合比率が５ｖｏｌ％を超えたり、プ
ラズマ生成用ガス８に占める水素ガスの混合比率が３ｖ
ｏｌ％を超えたりすると、酸素ガスや水素ガスによる電
子の吸着効果が高くなり過ぎて、酸素や水素のマイナス
イオンと希ガス（ＡｒやＨｅ）のプラスイオンとの衝突
によるイオンの消滅や放電空間２１内における電子密度
の低下が生じて放電効率が低下し、プラズマ１３による
有機物や酸化物等の除去（クリーニング）の効果が低下
する恐れがある。If the mixing ratio of the oxygen gas in the plasma generating gas 8 is less than 2 vol% or the mixing ratio of the hydrogen gas in the plasma generating gas 8 is less than 0.3 vol%, the oxygen gas or the hydrogen There is a possibility that the effect of adsorbing electrons by the gas is reduced and the charge-up damage cannot be reduced, and the mixing ratio of the oxygen gas in the plasma generating gas exceeds 5 vol% or the hydrogen gas in the plasma generating gas 8 Is 3v
%, the effect of adsorbing electrons by oxygen gas or hydrogen gas becomes too high, and the elimination of ions or the discharge space due to collision of negative ions of oxygen or hydrogen with positive ions of rare gas (Ar or He). There is a possibility that the electron efficiency in the inside 21 decreases, the discharge efficiency decreases, and the effect of removing (cleaning) organic substances and oxides by the plasma 13 decreases.

【００２３】プラズマ生成用ガス８の希ガスとしてはＨ
ｅ、Ｎｅ、Ａｒ、Ｋｒ、Ｘｅなどをそれぞれ単独で用い
たり複数種を併用したりすることができるが、安価なＡ
ｒのみを用いるのがコスト面で好ましい。電極９、１０
間に印加する電圧がパルス電圧の場合は放電効率が高い
ので、プラズマ生成用ガス８の希ガスとしてＡｒのみを
用いてもよい（もちろんＨｅを併用しても良い）。しか
しながら、電極９、１０間に印加する電圧が高周波電圧
の場合は放電効率がパルス電圧に比べて高くないので、
プラズマ生成用ガス８の希ガスとしてＨｅとＡｒを併用
するのが好ましい。このようにプラズマ生成用ガス８の
希ガスとしてＨｅとＡｒを併用すると、Ｈｅにより放電
空間２１における絶縁破壊電圧が低くなってそれだけ放
電効率を高くすることができてプラズマ１３を容易に生
成することができ、プラズマ１３の生成効率が高まって
有機物等の除去の性能を向上させることができるもので
ある。The rare gas of the plasma generating gas 8 is H
e, Ne, Ar, Kr, Xe, etc., can be used alone or in combination of a plurality of types.
It is preferable to use only r in terms of cost. Electrodes 9, 10
When the voltage applied in between is a pulse voltage, the discharge efficiency is high, so that only Ar may be used as the rare gas of the plasma generating gas 8 (of course, He may be used together). However, when the voltage applied between the electrodes 9 and 10 is a high-frequency voltage, the discharge efficiency is not high compared to the pulse voltage.
It is preferable to use He and Ar together as a rare gas of the plasma generating gas 8. As described above, when He and Ar are used in combination as the rare gases of the plasma generating gas 8, the dielectric breakdown voltage in the discharge space 21 is reduced by He, so that the discharge efficiency can be increased and the plasma 13 can be easily generated. Thus, the generation efficiency of the plasma 13 is increased, and the performance of removing organic substances and the like can be improved.

【００２４】プラズマ生成用ガス８の希ガスとしてＨｅ
とＡｒを併用する場合は、プラズマ生成用ガス８に占め
るＨｅの混合比率を３０ｖｏｌ％以下にするのが好まし
い。プラズマ生成用ガス８に占めるＨｅの混合比率が３
０ｖｏｌ％を超えるとコストアップにつながる恐れがあ
り、しかも、Ｈｅの方がＡｒよりも原子量が小さいため
にガス全体としての平均原子量が小さくなるものであ
り、よって、吹き出し口１２から吹き出されるプラズマ
１３の半導体チップ１４や実装基板１５やバンプ１６へ
の到達速度が低下して、半導体チップ１４や実装基板１
５やバンプ１６にプラズマ１３が到達する前に、クリー
ニングを行う活性種が死滅する割合が大きくなってクリ
ーニング性能が低下する恐れがある。従って、プラズマ
生成用ガス８に占めるＨｅの混合比率を３０ｖｏｌ％以
下にするのが好ましいが、放電効率を向上させるために
プラズマ生成用ガス８に占めるＨｅの混合比率は１０ｖ
ｏｌ％以上にするのが好ましい。He is a rare gas of the plasma generating gas 8
When both Ar and Ar are used, it is preferable that the mixing ratio of He in the plasma generating gas 8 is 30 vol% or less. The mixing ratio of He in the plasma generating gas 8 is 3
If the content exceeds 0 vol%, the cost may increase, and moreover, He has a smaller atomic weight than Ar, so that the average atomic weight of the gas as a whole becomes smaller. 13 reaches the semiconductor chip 14, the mounting substrate 15, and the bump 16, and the semiconductor chip 14 and the mounting substrate 1
Before the plasma 13 reaches the bumps 5 and the bumps 16, the rate at which the active species to be cleaned is killed increases, and the cleaning performance may be reduced. Therefore, the mixing ratio of He in the plasma generating gas 8 is preferably 30 vol% or less. However, in order to improve the discharge efficiency, the mixing ratio of He in the plasma generating gas 8 is 10 vol.
ol% or more is preferable.

【００２５】また、上記のようにプラズマ生成用ガス８
の希ガスとしてＡｒのみを用いる場合は、Ａｒの方がＨ
ｅよりも原子量が大きいために、Ｈｅと併用した場合に
比べて、ガス全体としての平均原子量が大きくなるもの
であり、よって、吹き出し口１２から吹き出されるプラ
ズマ１３の半導体チップ１４や実装基板１５やバンプ１
６への到達速度が向上して、半導体チップ１４や実装基
板１５やバンプ１６にプラズマ１３が到達する前に、ク
リーニングを行う活性種が死滅する割合が小さくなって
クリーニング性能を高くすることができる。As described above, the plasma generating gas 8
When only Ar is used as the rare gas of Ar, Ar is H
Since the atomic weight is larger than e, the average atomic weight of the gas as a whole becomes larger as compared with the case of using He in combination. Therefore, the semiconductor chip 14 and the mounting substrate 15 of the plasma 13 blown out from the blowout port 12 are formed. And bump 1
6, the rate at which active species for cleaning die before the plasma 13 reaches the semiconductor chip 14, the mounting substrate 15, and the bumps 16 is reduced, and the cleaning performance can be improved. .

【００２６】以下に、上記のプラズマ処理装置Ａを用い
た本発明のフリップチップ実装方法について説明する。
まず、図１（ａ）に示すように、半導体チップ１４の表
面に露出するボンディング部（電極）２０にスタッドバ
ンプ等のバンプ１６を形成する。バンプ１６は既知の各
種材料を用いて任意の方法で形成することができるが、
例えば、キャピラリ３１から金ワイヤ３２の先端を導出
すると共にこの金ワイヤ３２の先端をアーク放電等によ
りボール状に形成し、このボール状の金ワイヤ３２の先
端をボンディング部２０に熱圧着することによって、金
スタッドバンプであるバンプ１６を形成することができ
る。尚、バンプ１６は後述の実装基板１５の電極１９の
表面に形成しても良い。The flip chip mounting method of the present invention using the plasma processing apparatus A will be described below.
First, as shown in FIG. 1A, a bump 16 such as a stud bump is formed on a bonding portion (electrode) 20 exposed on the surface of the semiconductor chip 14. The bump 16 can be formed by any method using known various materials.
For example, the tip of the gold wire 32 is led out from the capillary 31, the tip of the gold wire 32 is formed into a ball shape by arc discharge or the like, and the tip of the ball-shaped gold wire 32 is thermocompression-bonded to the bonding portion 20. The bump 16 which is a gold stud bump can be formed. The bumps 16 may be formed on the surface of an electrode 19 of the mounting board 15 described later.

【００２７】次に、図１（ｂ）に示すように、上記のバ
ンプ１６の表面に銀ペーストなどの既知の導電性ペース
ト１７を塗布する。次に、図１（ｃ）に示すように、電
子回路基板等で形成される実装基板１５に上側から半導
体チップ１４を近づけて載置し、実装基板１５の表面に
形成された複数の電極１９と各電極１９に対応する所定
のバンプ１６及び導電性ペースト１７とを接触させるよ
うにする。次に、導電性ペースト１７に熱を加えるなど
して導電性ペースト１７を硬化させることによって、半
導体チップ１４のボンディング部２０と実装基板１５の
電極１９とを電気的に接続すると共に半導体チップ１４
と実装基板１５をバンプ１６及び硬化した導電性ペース
ト１７により接合する。Next, as shown in FIG. 1B, a known conductive paste 17 such as a silver paste is applied to the surface of the bump 16. Next, as shown in FIG. 1C, the semiconductor chip 14 is placed close to the mounting board 15 formed of an electronic circuit board or the like from above, and a plurality of electrodes 19 formed on the surface of the mounting board 15 are formed. And the predetermined bump 16 and the conductive paste 17 corresponding to each electrode 19 are brought into contact with each other. Next, the conductive paste 17 is cured by, for example, applying heat to the conductive paste 17 so that the bonding portion 20 of the semiconductor chip 14 and the electrode 19 of the mounting board 15 are electrically connected and the semiconductor chip 14 is hardened.
And the mounting substrate 15 are joined by the bumps 16 and the cured conductive paste 17.

【００２８】このように半導体チップ１４と実装基板１
５を接合した後、上記のプラズマ処理装置Ａを用いて有
機物等の除去（クリーニング）を行う。この有機物等の
除去は次のようにして行う。まず、ガス導入口５１から
反応管７内にプラズマ生成用ガス８を導入すると共にプ
ラズマ生成用ガス８を反応管７内で上から下に向かって
流して放電空間２１に導入する。次に、電源１１により
電極９、１０間に高周波電圧またはパルス電圧を印加す
ることによって、反応管７内の放電空間２１に高周波電
界またはパルス電界を印加して発生させ、この高周波電
界またはパルス電界により大気圧近傍の圧力下（９３．
３〜１０６．７ｋＰａ（７００〜８００Ｔｏｒｒ））で
放電空間２１にグロー状の放電を発生させる。この後、
グロー状の放電でプラズマ生成用ガス８がプラズマ化さ
れてプラズマ活性種を含むプラズマ１３が放電空間２１
で連続的に生成される。As described above, the semiconductor chip 14 and the mounting substrate 1
After the bonding of No. 5, organic substances and the like are removed (cleaned) using the plasma processing apparatus A described above. This removal of organic substances and the like is performed as follows. First, the plasma generating gas 8 is introduced into the reaction tube 7 from the gas inlet 51, and the plasma generating gas 8 flows from the top to the bottom in the reaction tube 7 to be introduced into the discharge space 21. Next, by applying a high-frequency voltage or a pulse voltage between the electrodes 9 and 10 by the power supply 11, a high-frequency or pulsed electric field is applied to the discharge space 21 in the reaction tube 7 to generate the high-frequency or pulsed electric field. Under atmospheric pressure (93.
A glow-like discharge is generated in the discharge space 21 at a pressure of 3 to 106.7 kPa (700 to 800 Torr). After this,
The plasma generating gas 8 is turned into plasma by the glow-like discharge, and the plasma 13 containing the plasma active species is formed in the discharge space 21.
Is generated continuously.

【００２９】そして、反応管７の吹き出し口１２の下側
に半導体チップ１４を接合した実装基板１５を配置し、
上記のようにして生成されたプラズマ１３を吹き出し口
１２から下方に向かってジェット状に連続的に流出さ
せ、図１（ｅ）及び図２に示すように、プラズマ１３を
半導体チップ１４を接合した実装基板１５に上側から吹
き付けて供給することによって、プラズマ１３中に生成
されたラジカル等の活性種のスパッタリングにより半導
体チップ１４の表面と実装基板１５の表面とバンプ１６
（硬化した導電性ペースト１７も含む）の表面に付着し
た有機物や酸化膜等を除去してクリーニングする。Then, a mounting substrate 15 to which the semiconductor chip 14 is bonded is disposed below the outlet 12 of the reaction tube 7.
The plasma 13 generated as described above is continuously jetted downward from the outlet 12 in the form of a jet, and the plasma 13 is bonded to the semiconductor chip 14 as shown in FIGS. The surface of the semiconductor chip 14, the surface of the mounting substrate 15, and the bumps 16 are sprayed on the mounting substrate 15 from above by supplying active species such as radicals generated in the plasma 13 by sputtering.
Organic substances, oxide films and the like attached to the surface of the conductive paste (including the cured conductive paste 17) are removed and cleaning is performed.

【００３０】この時、半導体チップ１４を接合した実装
基板１５に上側から吹き付けて供給されたプラズマ１３
は、半導体チップ１４の下側に回り込んで実装基板１５
の面方向に沿って進んで半導体チップ１４と実装基板１
５の間の間隙３０に側方から侵入するものであり、これ
により、半導体チップ１４と実装基板１５の対向する表
面（半導体チップ１４の下面と実装基板１５の上面）及
びバンプ１６（硬化した導電性ペースト１７も含む）の
表面にプラズマ１３が達してクリーニングすることがで
きるものである。尚、プラズマ１３を吹き出し口１２か
ら吹き出しながら吹き出し口１２の下側において半導体
チップ１４を接合した複数個の実装基板１５を連続的に
搬送することによって、インラインで連続的にクリーニ
ングすることができる。At this time, the plasma 13 supplied by spraying from above onto the mounting substrate 15 to which the semiconductor chip 14 has been bonded is supplied.
Goes around the lower side of the semiconductor chip 14 and
Of the semiconductor chip 14 and the mounting substrate 1
5 between the semiconductor chip 14 and the mounting substrate 15 (the lower surface of the semiconductor chip 14 and the upper surface of the mounting substrate 15) and the bump 16 (the hardened conductive material). The plasma 13 reaches the surface of the conductive paste 17 (including the conductive paste 17) and can be cleaned. In addition, by continuously transporting the plurality of mounting substrates 15 to which the semiconductor chips 14 are bonded under the outlet 12 while blowing out the plasma 13 from the outlet 12, cleaning can be continuously performed in-line.

【００３１】上記のようにクリーニングを行うにあたっ
て、電源１１により電極９、１０間に印加される高周波
電圧あるいはパルス電圧の周波数は１ｋＨｚ〜２００Ｍ
Ｈｚに設定するのが好ましい。高周波電圧あるいはパル
ス電圧の周波数が１ｋＨｚ未満であれば、放電空間２１
での放電を安定化させることができなくなり、プラズマ
処理を効率よく行うことができなくなる恐れがある。ま
た、高周波電圧あるいはパルス電圧の周波数が２００Ｍ
Ｈｚを超えると、放電空間２１でのプラズマの温度上昇
が著しくなり、反応管７や電極９、１０の寿命が短くな
る恐れがあり、しかも、電子回路基板１５や半導体チッ
プ１４が熱的損傷を受けたり、プラズマ処理装置が複雑
化及び大型化する恐れがある。In performing the cleaning as described above, the frequency of the high frequency voltage or the pulse voltage applied between the electrodes 9 and 10 by the power supply 11 is 1 kHz to 200 MHz.
Hz is preferable. If the frequency of the high frequency voltage or the pulse voltage is less than 1 kHz, the discharge space 21
In this case, the discharge of the plasma cannot be stabilized, and the plasma processing may not be performed efficiently. Also, the frequency of the high frequency voltage or the pulse voltage is 200M
If the frequency exceeds 100 Hz, the temperature of the plasma in the discharge space 21 rises remarkably, and the life of the reaction tube 7 and the electrodes 9 and 10 may be shortened. In addition, the electronic circuit board 15 and the semiconductor chip 14 may cause thermal damage. Or the plasma processing apparatus may be complicated and large.

【００３２】また、放電空間２１に供給される（印加さ
れる）電力の密度は２０〜３５００Ｗ／ｃｍ3に設定す
るのが好ましい。放電空間２１に供給される電力の密度
が２０Ｗ／ｃｍ3未満であれば、放電空間２１でプラズ
マ１３を充分に発生させることができなくなり、逆に、
放電空間２１に供給される電力の密度が３５００Ｗ／ｃ
ｍ3を超えると、放電空間２１で安定した放電を得るこ
とができなくなる恐れがある。尚、電力の密度（Ｗ／ｃ
ｍ3）は（放電空間２１に供給される電力／放電空間２
１の体積）で定義される。The density of the power supplied (applied) to the discharge space 21 is preferably set to 20 to 3500 W / cm 3 . If the density of the power supplied to the discharge space 21 is less than 20 W / cm 3 , the plasma 13 cannot be sufficiently generated in the discharge space 21, and conversely,
The density of the power supplied to the discharge space 21 is 3500 W / c
If it exceeds m 3 , stable discharge may not be obtained in the discharge space 21. The power density (W / c
m 3 ) is (power supplied to discharge space 21 / discharge space 2)
1 volume).

【００３３】上記のようにしてクリーニングを行った
後、アンダーフィルを行う。半導体チップ１４と実装基
板１５の間隙３０に注入するアンダーフィル材３３とし
ては液状樹脂や液状樹脂組成物など、アンダーフィル用
の既知の樹脂あるいは樹脂組成物を用いることができ、
例えば、エポキシ樹脂に炭酸カルシウムなどの充填材を
配合したエポキシ樹脂組成物を用いることができる。ま
た、アンダーフィル材３３の注入方法も任意であって、
例えば、図１（ｆ）に示すように、間隙３０の側面開口
にノズル３５を近づけてこのノズル３５からアンダーフ
ィル材３３を吹き出して間隙３０に注入することができ
る。そして、この後、間隙３０に注入したアンダーフィ
ル材３３を加熱などして硬化させることによって、図１
（ｇ）に示すような半導体パッケージを形成することが
できる。After the cleaning is performed as described above, an underfill is performed. As the underfill material 33 injected into the gap 30 between the semiconductor chip 14 and the mounting board 15, a known resin or resin composition for underfill, such as a liquid resin or a liquid resin composition, can be used.
For example, an epoxy resin composition in which a filler such as calcium carbonate is mixed with an epoxy resin can be used. Also, the method of injecting the underfill material 33 is optional,
For example, as shown in FIG. 1F, the nozzle 35 can be brought close to the side opening of the gap 30 and the underfill material 33 can be blown out from the nozzle 35 and injected into the gap 30. Then, the underfill material 33 injected into the gap 30 is cured by heating, etc.
A semiconductor package as shown in (g) can be formed.

【００３４】上記のような本発明のフリップチップ実装
方法では、実装基板１５と半導体チップ１４の間に形成
される間隙３０を挟んで対向する半導体チップ１４の表
面と実装基板１５の表面及びこの間隙３０に存在するバ
ンプ１６の表面に付着した有機物等を除去し、この後、
アンダーフィルを行うので、アンダーフィル材３３の流
れを阻害したりアンダーフィル材３３の密着を阻害した
りする有機物等の汚れをプラズマ処理により除去するこ
とによって、間隙３０においてアンダーフィル材３３が
流れやすくなってアンダーフィル材３３の未注入部分が
生じないようにすることができると共に半導体チップ１
４の表面や実装基板１５の表面やバンプ１６の表面に対
するアンダーフィル材３３の密着性を高くすることがで
きるものであり、これにより、アンダーフィル材３３に
よるバンプ１６の補強効果や間隙３０の密閉性を高くす
ることができるものである。従って、半導体チップ１４
と実装基板１５の接合強度が高くて耐湿性に優れる半導
体パッケージを形成することができるものである。In the flip chip mounting method of the present invention as described above, the surface of the semiconductor chip 14 and the surface of the mounting substrate 15 which face each other with the gap 30 formed between the mounting Organic substances and the like attached to the surface of the bump 16 existing in 30 are removed.
Since the underfill is performed, dirt such as an organic substance that hinders the flow of the underfill material 33 or the adhesion of the underfill material 33 is removed by plasma processing, so that the underfill material 33 easily flows in the gap 30. And the unfilled portion of the underfill material 33 can be prevented from being generated.
4 can improve the adhesion of the underfill material 33 to the surface of the mounting substrate 15 and the surface of the bump 16, whereby the reinforcing effect of the underfill material 33 on the bump 16 and the sealing of the gap 30 can be achieved. It is possible to enhance the nature. Therefore, the semiconductor chip 14
This makes it possible to form a semiconductor package having a high bonding strength between the substrate and the mounting substrate 15 and having excellent moisture resistance.

【００３５】また、本発明ではプラズマ処理装置Ａから
吹き出されるプラズマ１３を半導体チップ１４を接合し
た実装基板１５に吹き付けて供給するので、吹き付けに
よる圧力でプラズマ１３を狭い間隙３０の中心付近にま
で侵入させることができ、間隙３０の全体に亘って半導
体チップ１４の表面や実装基板１５の表面やバンプ１６
の表面に対するクリーニングを均一におこなうことがで
きるものである。また、半導体チップ１４と実装基板１
５をバンプ１６により接合した後、プラズマ１３による
クリーニングを行うので、半導体チップ１４と実装基板
１５の両方のクリーニングを一度におこなうことがで
き、半導体チップ１４と実装基板１５とを個別にクリー
ニングするのに比べて、効率よくクリーニングをおこな
うことができるものであり、しかも、クリーニングとア
ンダーフィルの間隔を短くすることができ、クリーニン
グ後に再度汚れが付着しにくくすることができるもので
ある。Further, in the present invention, since the plasma 13 blown out from the plasma processing apparatus A is blown and supplied to the mounting substrate 15 to which the semiconductor chip 14 is bonded, the plasma 13 is supplied to the vicinity of the center of the narrow gap 30 by the pressure of the blowing. The surface of the semiconductor chip 14, the surface of the mounting board 15, the bump 16
The cleaning of the surface can be performed uniformly. Also, the semiconductor chip 14 and the mounting substrate 1
Since the semiconductor chip 14 and the mounting substrate 15 can be cleaned at the same time because the cleaning with the plasma 13 is performed after the bonding of the semiconductor chip 14 and the mounting substrate 15 by the bumps 16, the semiconductor chip 14 and the mounting substrate 15 can be individually cleaned. As compared with the above, the cleaning can be performed more efficiently, the interval between the cleaning and the underfill can be shortened, and the dirt can hardly adhere again after the cleaning.

【００３６】[0036]

【実施例】以下本発明を実施例によって具体的に説明す
る。The present invention will be described below in detail with reference to examples.

【００３７】（実施例１）図１に示す構造のプラズマ処
理装置Ａを形成した。反応管７は石英ガラスで形成し
た。また、上側の電極９と下側の電極１０は銅製のもの
を用い、電極９が高圧電極に、電極１０が低圧（接地）
電極となるように電源１１と電気的に接続した。プラズ
マ生成用ガス８はＨｅとＡｒと酸素ガス（Ｏ2）の混合
ガスを用いた。この時、Ｈｅの流量は２リットル／分、
Ａｒの流量は１０リットル／分、酸素ガスの流量は０．
４リットル／分として反応管７に導入し、プラズマ生成
用ガス８に占める酸素ガスの混合比率を約３．２ｖｏｌ
％とした。Example 1 A plasma processing apparatus A having the structure shown in FIG. 1 was formed. The reaction tube 7 was formed of quartz glass. The upper electrode 9 and the lower electrode 10 are made of copper, and the electrode 9 is a high voltage electrode and the electrode 10 is a low voltage (ground).
It was electrically connected to the power supply 11 so as to become an electrode. As the plasma generating gas 8, a mixed gas of He, Ar, and oxygen gas (O 2 ) was used. At this time, the flow rate of He was 2 liters / minute,
The flow rate of Ar was 10 liters / minute, and the flow rate of oxygen gas was 0.1 L / min.
The mixture was introduced into the reaction tube 7 at a rate of 4 liters / minute, and the mixing ratio of the oxygen gas in the plasma generating gas 8 was about 3.2 vol.
%.

【００３８】そして、大気圧下で周波数が１３．５６Ｍ
Ｈｚ、７００Ｗの電力を電極９、１０間（放電空間２
１）に供給して電極９、１０間に高周波電圧（正弦波の
波形）を印加することにより、反応管７内の放電空間２
１でグロー状の放電を発生させると共にこの放電により
放電空間２１にプラズマ１３を生成し、このプラズマ１
３を吹き出し口１２からジェット状に吹き出すように形
成した。The frequency is 13.56M under atmospheric pressure.
Hz, 700 W power between the electrodes 9 and 10 (discharge space 2
1) to apply a high-frequency voltage (sinusoidal waveform) between the electrodes 9 and 10 so that the discharge space 2 in the reaction tube 7 is
1, a glow-like discharge is generated, and a plasma 13 is generated in the discharge space 21 by the discharge.
3 was formed so as to be jetted from the jet port 12 in a jet shape.

【００３９】（実施例２）プラズマ生成用ガス８として
ＨｅとＡｒと水素ガス（Ｈ2）の混合ガスを用いた。こ
の時、Ｈｅの流量は０．２９リットル／分、Ａｒの流量
は１．４６リットル／分、水素ガスの流量は０．０１７
リットル／分として反応管７に導入し、プラズマ生成用
ガス８に占める水素ガスの混合比率を約１．０ｖｏｌ％
とした。また、電極９、１０間（放電空間２１）に供給
する電力を１００Ｗとした。(Example 2 ) A mixed gas of He, Ar and hydrogen gas (H 2 ) was used as the plasma generating gas 8. At this time, the flow rate of He was 0.29 l / min, the flow rate of Ar was 1.46 l / min, and the flow rate of hydrogen gas was 0.017 l / min.
The reaction mixture was introduced into the reaction tube 7 at a rate of 1 liter / min.
And The electric power supplied between the electrodes 9 and 10 (discharge space 21) was 100 W.

【００４０】これら以外は実施例１と同様にした。The other conditions were the same as in Example 1.

【００４１】（実施例３）酸素ガスの流量を０．１２リ
ットル／分とし、プラズマ生成用ガス８に占める酸素ガ
スの混合比率を１．０ｖｏｌ％とした以外は、実施例１
と同様にした。(Example 3) Example 1 was repeated except that the flow rate of oxygen gas was 0.12 liter / min and the mixing ratio of oxygen gas in the plasma generating gas 8 was 1.0 vol%.
Same as.

【００４２】（実施例４）水素ガスの流量を０．００４
リットル／分とし、プラズマ生成用ガス８に占める水素
ガスの混合比率を約０．２２ｖｏｌ％とした以外は、実
施例２と同様にした。(Example 4) The flow rate of hydrogen gas was set to 0.004.
The procedure was the same as in Example 2, except that the liter / minute was used and the mixing ratio of the hydrogen gas in the plasma generating gas 8 was about 0.22 vol%.

【００４３】そして、上記の実施例１〜４のプラズマ処
理装置Ａを用いてＱｂｄ評価を行った。このＱｂｄ評価
は、Ｑｂｄ評価用の被処理物としてガラス基材エポキシ
樹脂基板である基板にＭＯＳＦＥＴのゲート酸化膜を形
成したものを用い、この被処理物にプラズマを５秒間供
給してプラズマ処理を行った後、ゲート酸化膜の寿命を
測定し、チャージアップダメージによるダメージをプラ
ズマ処理前後でのゲート酸化膜の寿命の差により評価し
た。結果を図４、５に示す。Then, Qbd evaluation was performed using the plasma processing apparatus A of the above-described Examples 1-4. This Qbd evaluation uses a glass substrate epoxy resin substrate on which a gate oxide film of a MOSFET is formed as a processing object for Qbd evaluation, and supplies plasma to the processing object for 5 seconds to perform plasma processing. After that, the life of the gate oxide film was measured, and the damage due to the charge-up damage was evaluated based on the difference in the life of the gate oxide film before and after the plasma treatment. The results are shown in FIGS.

【００４４】図４、５から明らかなように、実施例１、
２ではプラズマ処理前（未処理）のものに比べて、ゲー
ト酸化膜の寿命の低下がほどんどなく、チャージアップ
ダメージによるダメージが緩和されているのに対して、
実施例３、４ではプラズマ処理前（未処理）のものに比
べて、ゲート酸化膜の寿命が低下していて、チャージア
ップダメージによるダメージが発生しやすかった。As is apparent from FIGS.
In the case of No. 2, the life of the gate oxide film was hardly reduced and the damage due to the charge-up damage was reduced as compared with that before the plasma treatment (untreated).
In Examples 3 and 4, the life of the gate oxide film was shorter than that before the plasma treatment (untreated), and damage due to charge-up damage was more likely to occur.

【００４５】上記の実施例１〜４のプラズマ処理装置Ａ
を用いてクリーニング性能評価を行った。このクリーニ
ング性能評価は、クリーニング性能評価用の被処理物５
０としてウェハ２６の表面にネガタイプのレジスト２７
を塗布したものを用い、図６に示すように、この被処理
物５０にプラズマ１３を１秒間供給してプラズマ処理を
行った後、レジスト２７の膜厚を測定した。尚、このク
リーニング性能評価はレジスト２７を半導体チップ１４
の表面や実装基板１５の表面やバンプ１６の表面に付着
した有機成分のモデルとして想定している。結果を図７
に示す。The plasma processing apparatus A according to the first to fourth embodiments.
Was used to evaluate the cleaning performance. This cleaning performance evaluation is performed by using the cleaning target evaluation object 5.
0 as a negative resist 27 on the surface of the wafer 26
As shown in FIG. 6, a plasma 13 was supplied to the object 50 for 1 second to perform a plasma treatment, and then the film thickness of the resist 27 was measured. In this cleaning performance evaluation, the resist 27 was
It is assumed as a model of the organic component attached to the surface of the substrate, the surface of the mounting substrate 15, and the surface of the bump 16. Fig. 7 shows the results.
Shown in

【００４６】図７から明らかなように、実施例１〜４で
は、プラズマ処理によりレジスト２７が除去（エッチン
グ）されることで、プラズマ処理前よりもレジスト２７
の膜厚を大幅に薄くすることができ、有機物の汚れのク
リーニングをおこなうのに十分な性能を有することが確
認された。As is clear from FIG. 7, in the first to fourth embodiments, the resist 27 is removed (etched) by the plasma treatment, so that the resist 27 is removed more than before the plasma treatment.
It was confirmed that the film had a sufficient performance for cleaning organic dirt.

【００４７】そして、実施例１〜４のプラズマ処理装置
Ａを用いて、図１（ａ）〜（ｇ）に示す工程にしたがっ
て半導体パッケージを製造した結果、間隙３０において
アンダーフィル材３３の未注入部分が生じず、且つ半導
体チップ１４の表面や実装基板１５の表面やバンプ１６
の表面に対するアンダーフィル材３３の密着性が高くな
って、アンダーフィル材３３によるバンプ１６の補強効
果や間隙３０の密閉性を高くすることができた。Then, as a result of manufacturing a semiconductor package according to the steps shown in FIGS. 1A to 1G using the plasma processing apparatus A of the first to fourth embodiments, the underfill material 33 was not injected into the gap 30. No portion is formed, and the surface of the semiconductor chip 14, the surface of the mounting substrate 15,
The adhesiveness of the underfill material 33 to the surface of the bumps was increased, and the effect of reinforcing the bumps 16 by the underfill material 33 and the tightness of the gap 30 could be improved.

【００４８】[0048]

【発明の効果】上記のように本発明の請求項１の発明
は、半導体チップと実装基板をバンプにより接合した
後、プラズマ処理装置から吹き出されるプラズマを半導
体チップと実装基板の間隙に供給することによって半導
体チップの表面と実装基板の表面とバンプの表面を洗浄
し、この後、アンダーフィルを行うので、アンダーフィ
ルの際に間隙に注入するアンダーフィル材の流れを阻害
したりアンダーフィル材の密着を阻害したりする有機物
等の汚れをプラズマ処理により除去することによって、
間隙においてアンダーフィル材が流れやすくなってアン
ダーフィル材の未注入部分が生じないようにすることが
できると共に半導体チップの表面や実装基板の表面やバ
ンプの表面に対するアンダーフィル材の密着性を高くす
ることができ、バンプの補強効果や間隙の密閉性を高く
することができるものである。As described above, according to the first aspect of the present invention, after the semiconductor chip and the mounting substrate are joined by bumps, the plasma blown out from the plasma processing apparatus is supplied to the gap between the semiconductor chip and the mounting substrate. As a result, the surface of the semiconductor chip, the surface of the mounting substrate, and the surface of the bumps are cleaned, and then the underfill is performed. By removing dirt such as organic substances that hinder adhesion by plasma treatment,
It is possible to prevent the underfill material from flowing easily in the gap and prevent the unfilled portion of the underfill material from being generated, and to enhance the adhesion of the underfill material to the surface of the semiconductor chip, the surface of the mounting substrate, or the surface of the bump. Thus, the effect of reinforcing the bumps and the tightness of the gap can be enhanced.

【００４９】また本発明の請求項２の発明は、請求項１
に記載のフリップチップ実装方法に用いるプラズマ処理
装置であって、筒状の反応管の片側を吹き出し口として
開放し、反応管の外側に複数個の電極を配設し、希ガス
を含むプラズマ生成用ガスを反応管に導入すると共に電
極間に電圧を印加することによって大気圧近傍の圧力下
で反応管内に放電を発生させ、放電により反応管内に生
成されたプラズマを吹き出し口から吹き出すので、吹き
付けによる圧力でプラズマを狭い間隙の中心付近にまで
侵入させることができ、間隙の全体に亘って半導体チッ
プの表面や実装基板の表面やバンプの表面に対するクリ
ーニングを均一におこなうことができるものである。The second aspect of the present invention is the first aspect of the present invention.
A plasma processing apparatus used in the flip-chip mounting method according to the above, wherein one side of a cylindrical reaction tube is opened as a blow-out port, a plurality of electrodes are arranged outside the reaction tube, and plasma containing a rare gas is generated. A discharge gas is generated in the reaction tube at a pressure close to the atmospheric pressure by introducing a gas for use into the reaction tube and applying a voltage between the electrodes, and the plasma generated in the reaction tube by the discharge is blown out from the outlet, so that spraying is performed. With this pressure, the plasma can penetrate into the vicinity of the center of the narrow gap, and the surface of the semiconductor chip, the surface of the mounting substrate, and the surface of the bump can be uniformly cleaned over the entire gap.

【００５０】また本発明の請求項３の発明は、プラズマ
生成用ガスを希ガスと酸素ガスの混合ガスとし、プラズ
マ生成用ガスに占める酸素ガスの混合比率を２〜５ｖｏ
ｌ％にするので、プラズマ中に生じる電子を酸素ガスで
吸着して消滅させることができ、プラズマ処理時に半導
体チップに加わる電子によるチャージアップを少なくす
ることができて半導体チップのチャージアップダメージ
を低減することができるものである。According to a third aspect of the present invention, the plasma generating gas is a mixed gas of a rare gas and an oxygen gas, and the mixing ratio of the oxygen gas in the plasma generating gas is 2 to 5 vol.
Since it is 1%, electrons generated in the plasma can be eliminated by adsorbing the oxygen gas with oxygen gas, and charge-up due to electrons applied to the semiconductor chip during plasma processing can be reduced, thereby reducing charge-up damage of the semiconductor chip. Is what you can do.

【００５１】また本発明の請求項４の発明は、プラズマ
生成用ガスを希ガスと水素ガスの混合ガスとし、プラズ
マ生成用ガスに占める水素ガスの混合比率を０．３〜３
ｖｏｌ％にするので、プラズマ中に生じる電子を水素ガ
スで吸着して消滅させることができ、プラズマ処理時に
半導体チップに加わる電子によるチャージアップを少な
くすることができて半導体チップのチャージアップダメ
ージを低減することができるものである。According to a fourth aspect of the present invention, the plasma generating gas is a mixed gas of a rare gas and a hydrogen gas, and the mixing ratio of the hydrogen gas in the plasma generating gas is 0.3 to 3%.
Since the vol.% is set, the electrons generated in the plasma can be eliminated by adsorbing the hydrogen gas with the hydrogen gas, and the charge-up due to the electrons applied to the semiconductor chip during the plasma processing can be reduced, thereby reducing the charge-up damage of the semiconductor chip. Is what you can do.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態の一例を示す（ａ）〜
（ｇ）は概略の正面図である。FIGS. 1A to 1C show an example of an embodiment of the present invention.
(G) is a schematic front view.

【図２】同上のプラズマ処理装置の一例を示す斜視図で
ある。FIG. 2 is a perspective view showing an example of the plasma processing apparatus of the above.

【図３】チャージアップを説明する説明図である。FIG. 3 is an explanatory diagram illustrating charge-up.

【図４】同上の実施例１、３のＱｂｄ評価を示すグラフ
である。FIG. 4 is a graph showing Qbd evaluations of Examples 1 and 3 of the embodiment.

【図５】同上の実施例２、４のＱｂｄ評価を示すグラフ
である。FIG. 5 is a graph showing Qbd evaluations of Examples 2 and 4 of the Embodiment.

【図６】同上のクリーニング性能評価の実験を示す斜視
図である。FIG. 6 is a perspective view showing an experiment of cleaning performance evaluation according to the embodiment.

【図７】同上の実施例１〜４のクリーニング性能を示す
グラフである。FIG. 7 is a graph showing cleaning performance of Examples 1 to 4 of the Embodiment.

【符号の説明】[Explanation of symbols]

７ 反応管 ８ プラズマ生成用ガス ９ 電極 １０ 電極 １２ 吹き出し口 １３ プラズマ １４ 半導体チップ １５ 実装基板 １６ バンプ 7 Reaction tube 8 Plasma generating gas 9 Electrode 10 Electrode 12 Blow-out port 13 Plasma 14 Semiconductor chip 15 Mounting substrate 16 Bump

───────────────────────────────────────────────────── フロントページの続き (72)発明者 澤田 康志 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 葛原 一功 大阪府門真市大字門真1048番地松下電工株 式会社内 Ｆターム(参考） 5F044 LL11 RR19 5F061 AA01 BA03 CA05 CB12  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasushi Sawada 1048 Kazumasa Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd. F term (reference) 5F044 LL11 RR19 5F061 AA01 BA03 CA05 CB12

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップと実装基板をバンプにより
接合した後、プラズマ処理装置から吹き出されるプラズ
マを半導体チップと実装基板の間隙に供給することによ
って半導体チップの表面と実装基板の表面とバンプの表
面を洗浄し、この後、アンダーフィルを行うことを特徴
とするフリップチップ実装方法。After bonding a semiconductor chip and a mounting substrate with a bump, plasma blown out from a plasma processing apparatus is supplied to a gap between the semiconductor chip and the mounting substrate to thereby form a bump between the surface of the semiconductor chip, the surface of the mounting substrate, and the bump. A flip chip mounting method characterized by cleaning the surface and then performing underfill. 【請求項２】 請求項１に記載のフリップチップ実装方
法に用いるプラズマ処理装置であって、筒状の反応管の
片側を吹き出し口として開放し、反応管の外側に複数個
の電極を配設し、希ガスを含むプラズマ生成用ガスを反
応管に導入すると共に電極間に電圧を印加することによ
って大気圧近傍の圧力下で反応管内に放電を発生させ、
放電により反応管内に生成されたプラズマを吹き出し口
から吹き出すことを特徴とするプラズマ処理装置。2. A plasma processing apparatus used in the flip-chip mounting method according to claim 1, wherein one side of a cylindrical reaction tube is opened as a blowout port, and a plurality of electrodes are arranged outside the reaction tube. Then, a plasma generating gas containing a rare gas is introduced into the reaction tube and a voltage is applied between the electrodes to generate a discharge in the reaction tube under a pressure near the atmospheric pressure,
A plasma processing apparatus characterized in that plasma generated in a reaction tube by discharge is blown out from a blowout port. 【請求項３】 プラズマ生成用ガスを希ガスと酸素ガス
の混合ガスとし、プラズマ生成用ガスに占める酸素ガス
の混合比率を２〜５ｖｏｌ％にすることを特徴とする請
求項２に記載のプラズマ処理装置。3. The plasma according to claim 2, wherein the plasma generating gas is a mixed gas of a rare gas and an oxygen gas, and a mixing ratio of the oxygen gas in the plasma generating gas is 2 to 5 vol%. Processing equipment. 【請求項４】 プラズマ生成用ガスを希ガスと水素ガス
の混合ガスとし、プラズマ生成用ガスに占める水素ガス
の混合比率を０．３〜３ｖｏｌ％にすることを特徴とす
る請求項２に記載のプラズマ処理装置。4. The plasma generating gas according to claim 2, wherein a mixed gas of a rare gas and a hydrogen gas is used, and a mixing ratio of the hydrogen gas in the plasma generating gas is set to 0.3 to 3 vol%. Plasma processing equipment.
JP2000293044A 2000-09-26 2000-09-26 Flip chip mounting method Expired - Lifetime JP3937711B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000293044A JP3937711B2 (en) 2000-09-26 2000-09-26 Flip chip mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000293044A JP3937711B2 (en) 2000-09-26 2000-09-26 Flip chip mounting method

Publications (2)

Publication Number Publication Date
JP2002110735A true JP2002110735A (en) 2002-04-12
JP3937711B2 JP3937711B2 (en) 2007-06-27

Family

ID=18775888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000293044A Expired - Lifetime JP3937711B2 (en) 2000-09-26 2000-09-26 Flip chip mounting method

Country Status (1)

Country Link
JP (1) JP3937711B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059441A (en) * 2005-08-22 2007-03-08 Namics Corp Manufacturing method of semiconductor device
JP2012004603A (en) * 2004-09-15 2012-01-05 Seiko Epson Corp Mounting structure for semiconductor device, method for mounting semiconductor device and substrate
CN114823970A (en) * 2022-03-25 2022-07-29 昆明物理研究所 Method for increasing adhesiveness of photoresist on superlattice infrared focal plane chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012004603A (en) * 2004-09-15 2012-01-05 Seiko Epson Corp Mounting structure for semiconductor device, method for mounting semiconductor device and substrate
JP2007059441A (en) * 2005-08-22 2007-03-08 Namics Corp Manufacturing method of semiconductor device
JP4700438B2 (en) * 2005-08-22 2011-06-15 ナミックス株式会社 Manufacturing method of semiconductor device
CN114823970A (en) * 2022-03-25 2022-07-29 昆明物理研究所 Method for increasing adhesiveness of photoresist on superlattice infrared focal plane chip

Also Published As

Publication number Publication date
JP3937711B2 (en) 2007-06-27

Similar Documents

Publication Publication Date Title
US7078820B2 (en) Semiconductor apparatus and process of production thereof
JP2002110613A (en) Plasma cleaning apparatus and method
JP3312377B2 (en) Method and apparatus for joining with brazing material
JP3147137B2 (en) Surface treatment method and device, semiconductor device manufacturing method and device, and liquid crystal display manufacturing method
US6320155B1 (en) Plasma enhanced wire bonder
JPH11260597A (en) Plasma treatment apparatus and plasma treatment method
WO1994022628A1 (en) Combining method and apparatus using solder
KR100365898B1 (en) Plasma processing apparatus and processing method
KR101912578B1 (en) Passivation layer for semiconductor device packaging
US10399170B2 (en) Die attachment apparatus and method utilizing activated forming gas
JP2002001253A (en) Plasma cleaning apparatus and method, and soldering system and method
JP2007142297A (en) Method of manufacturing package component
JP3937711B2 (en) Flip chip mounting method
JP2002144231A (en) Surface treatment method and surface treatment device
JP4702157B2 (en) IC component mounting method and die bonding apparatus
US7176402B2 (en) Method and apparatus for processing electronic parts
JP3557682B2 (en) Semiconductor device manufacturing method and apparatus, and liquid crystal display manufacturing method
JPH11111694A (en) Method for plasma cleaning of chip-mounted substrate
JP2002118128A (en) Electronic component and manufacturing method thereof
JP2001023968A (en) Plasma processing system and plasma cleaning method
JP2002110639A (en) Plasma treatment device and plasma treatment method
JP2004363152A (en) Electronic component and method and device for processing the same
JP3427702B2 (en) Plasma processing equipment for electronic parts
JP2009231680A (en) Surface treatment method and surface treatment device of substrate, and method of manufacturing semiconductor package
Uner et al. The application of atmospheric pressure plasma to various steps in integrated circuit packaging

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050905

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061201

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061212

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070213

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070306

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070319

R151 Written notification of patent or utility model registration

Ref document number: 3937711

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100406

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100406

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100406

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110406

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120406

Year of fee payment: 5

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120406

Year of fee payment: 5

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120406

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130406

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130406

Year of fee payment: 6

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130406

Year of fee payment: 6

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130406

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140406

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250