JP2002109898A - Operation verifying method for memory test pattern, semiconductor test device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time of the operation verification of a memory test pattern and to eliminate misverification. SOLUTION: Address information needed to analyze the memory test pattern operation is read out of a memory test pattern source 2 to calculates address operation and a pattern operation analytic log 5 for the pattern operation analysis is generated; and address operation in command performance is extracted from the pattern operation analytic log 5 to generate a pattern operation grasping log 7. Further, the generation order and intervals between commands are extracted from the pattern operation analytic log 5 to generate a command performance interval grasping log 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for verifying the operation of a memory test pattern for verifying the operation of a test pattern of a semiconductor memory for greatly reducing the verification time.

[0002]

2. Description of the Related Art Conventionally, as a method of verifying the operation of a memory test pattern manually created based on a test specification describing the operation of a memory test pattern and the command execution order and interval, a pattern waveform observation using an oscilloscope waveform shown in FIG. And an operation verification method of a memory test pattern using a tool attached to the semiconductor test apparatus shown in FIG.

First, an operation verification by observing a pattern waveform using an oscilloscope waveform will be described with reference to FIG.

FIG. 6 shows a system for verifying an operation by observing a pattern waveform of an oscilloscope waveform. The system is used for electrically connecting the semiconductor test apparatus 100 and a semiconductor integrated circuit (memory) (not shown). DUT
(Device Under Test) Board 101, oscilloscope 103 used for tester waveform observation, oscilloscope 103
Probe 102 for electrically connecting the DUT board 101 to the
And performs operation verification of a memory test pattern of a semiconductor integrated circuit (memory) as a device under test.

In the system shown in FIG. 6, a semiconductor test apparatus 100 is operated in accordance with a memory test pattern to be verified, and a memory write, read, refresh operation,
Pause time, address increment (decrement)
Check the output waveforms of all pins of the address / I / O at the time of reset operation after the end of the operation and address increment. In this case, there are 30 to 50 points to be checked in one pattern and about 20 address / I / O pins,
Further, since it is necessary to carry out this verification for dozens of patterns, a large amount of time is spent for verifying the operation of the memory pattern, and there is a possibility that a problem such as a missing verification due to a human error may occur.

Next, an operation verification of a memory test pattern using software attached to a semiconductor test apparatus will be described with reference to FIGS. 7 and 8.

FIG. 7 is a system configuration diagram for verifying the operation of a memory test pattern using software.
A semiconductor test apparatus 100, an electronic computer 104 connected to the semiconductor test apparatus 100, and an address / I / O pin output of the semiconductor test apparatus displayed on a display unit on the electronic computer 104, or virtual operation by the electronic computer 104 The software is configured to display the result of the operation.

FIG. 8 shows a flowchart of the software attached to the semiconductor test apparatus.

First, a flowchart 105 of software for displaying address data output from a semiconductor test apparatus will be described. First, the semiconductor test apparatus 100 is set in advance so that the test state can be held in a pattern for verifying the operation, and the test is started by the semiconductor test apparatus 100 using a test program. Next, after the test state is held in the pattern for verifying the operation, the software for displaying the address / I / O information is activated on the semiconductor test apparatus 100 and the attached computer 104, and the semiconductor test apparatus 100 Read address / I / O information,
The state of the address / I / O pin ("H" or "L") is displayed for each pattern line as shown in FIG. 9, or the memory operation state (only four addresses are displayed for both X and Y addresses)
Is displayed as shown in FIG. And, using this information,
Check all points to check.

Next, a description will be given of a flowchart 106 of software for displaying a result of the virtual operation performed by the computer. A register for storing each register information held in the semiconductor test apparatus 100 necessary for the virtual operation of the pattern operation is set, the register information is calculated from the pattern program to be verified, and the address / I / O information is output. I do. The output format is the same as “software for displaying address data (FIG. 9)” in the semiconductor test.

[0011]

In the operation verification of the conventional memory test pattern, there are mainly problems such as (1) longer operation verification time and (2) increase in verification errors.

(1) Prolonging operation verification time In conventional operation verification, memory write, read, refresh operation, pause time, address increment (decrement) operation, and address / I / O at the time of reset operation after completion of address increment are performed. Output data of all pins (1
About 10 points per pattern, about 20 addresses / I / Os) for all patterns,
Further, it is necessary to perform the pattern operation up to the check point, which requires a great deal of time.

(2) Increase in Verification Mistakes In the conventional operation verification, since there are many points to be checked, the possibility of occurrence of verification mistakes has increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to reduce the operation verification time and eliminate verification errors in verifying the operation of a memory test pattern.

[0015]

According to the first aspect of the present invention, address information (jump count, address operation command, etc.) necessary for analyzing a memory test pattern operation is read from a memory test pattern source, and the address operation is calculated. It is characterized in that a pattern operation analysis log for pattern operation analysis is generated.

According to a second aspect of the present invention, an address operation at the time of executing a command (an address at the time of writing / reading to / from a memory, an address at the time of executing a jump command) is extracted from the pattern operation analysis log of the first aspect, and the operation is grasped. It is characterized by generating an easy-to-use format (pattern operation comprehension log).

A third aspect of the present invention is characterized in that a command generation order and an interval between commands are extracted from the pattern operation analysis log of the first aspect, and a command execution interval grasping log is generated.

According to a fourth aspect of the present invention, there is provided a semiconductor test apparatus for verifying the operation of a memory test pattern, wherein address information necessary for analyzing a memory test pattern operation is read from a memory test pattern source, and the address operation is calculated. Means for generating a pattern operation analysis log for determining and pattern operation analysis, and extracting the address operation at the time of command execution from the pattern operation analysis log, and generating a pattern operation grasp log. I do.

According to a fifth aspect of the present invention, there is provided a semiconductor test apparatus for verifying an operation of a memory test pattern, wherein address information necessary for analyzing a memory test pattern operation is read from a memory test pattern source, and the address operation is calculated. Means for generating a pattern operation analysis log for determining and analyzing pattern operation, and means for extracting a command generation order and an interval between commands from the pattern operation analysis log and generating a command execution interval grasping log. It is characterized by the following.

According to a sixth aspect of the present invention, there is provided a semiconductor device having a built-in self-test circuit, wherein address information necessary for analyzing a memory test pattern operation is read from a memory test pattern source, and the address operation is obtained by calculation. It is characterized by comprising means for generating a pattern operation analysis log for operation analysis, and means for extracting an address operation at the time of command execution from the pattern operation analysis log and generating a pattern operation grasp log.

According to a seventh aspect of the present invention, there is provided a semiconductor device having a built-in self-test circuit, wherein address information necessary for analyzing a memory test pattern operation is read from a memory test pattern source, and the address operation is obtained by calculation. Means for generating a pattern operation analysis log for operation analysis, and means for extracting a command generation order and an interval between commands from the pattern operation analysis log and generating a command execution interval grasp log. And

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows an automatic verification flow of a memory test pattern operation according to an embodiment of the present invention.

The verification of the memory test pattern operation according to the present embodiment is not performed by actually performing an address operation on a semiconductor test device, a self-test circuit in the semiconductor device, and an electronic computer as in the prior art. It is characterized in that an operation range is obtained by the above-described method, and the obtained address operation and command execution interval information are output in an easily understandable format.

The flow of the present embodiment is roughly divided into
(1) Information read / address operation calculation from memory test pattern source, (2) Output of pattern operation comprehension log, and (3) Output of command execution interval comprehension log, which will be described in order below.

(1) Information reading from memory test pattern / address operation calculation / pattern operation analysis log output (ST1 to ST4) First, in order to create a pattern operation analysis log 5 for pattern operation analysis, ST1 is used. , A label for each row, a pattern operation control instruction, a memory command, an address operation instruction,
Read data control instructions. Next, an address is calculated in ST3, and a pattern operation analysis log 5 is output in ST4.

FIG. 2 shows an example of a memory test pattern source.
FIG. 3 shows an output example of the pattern operation analysis log 5 obtained by calculating the address based on the read data. FIG. 2 shows a pattern in which “0” data is written in X addresses 0 to 2047 and Y addresses 0 to 15. Hereinafter, each item will be described.

Label: For example, an arbitrary label is created on a line to be specified as a jump destination by an unconditional jump command “JMP” in a pattern operation control instruction.

◎ Pattern operation control instruction This is an instruction for repeatedly outputting the address / I / O data generated by the semiconductor test device and the self-test circuit built in the semiconductor device.
When jumping, the number of jumps and the jump destination are also defined. The unconditional jump instruction (JM
P) means to jump unconditionally to the label "M1" 2048 times.

Memory command This command causes the memory to perform operations such as row address determination (ACT: Activate), column address determination (WT: Write), and write operation end (PRE: Precharge), and differs depending on the type of memory.

Address operation instruction Indicates an instruction for adding, subtracting, and resetting an address value generated by a semiconductor test device and a self-test circuit built in the semiconductor device.

Data control instruction Indicates an instruction to select "0" or "1" data to be written to the memory.

X / Y address start Indicates an X / Y address used first in the operation of the row.

X, Y address end Indicates the X / Y address used last in the operation of the row. (In FIG. 3, the address executed first time means the address executed 2048 times. Every time there is a JMP instruction, the address calculation at the time of the final jump is performed for the lines after the jump destination.)

(2) Log output of pattern operation comprehension (ST)
6) In order to output data in a format that makes it easy to grasp the memory test pattern operation, the pattern operation analysis log 5 extracts address operations and jump destination data at the time of write / read operations. Then, process the extracted data,
The pattern operation comprehension log 7 shown in FIG. 4 is output as a file.

(3) Command execution interval grasp log output (S
T8) In order to clarify the order in which the commands described in the memory test pattern are generated and the command execution interval,
The memory command and the command execution interval are extracted from the pattern operation analysis log, and the command execution interval grasping log 9 is filed.

As described above, according to the first embodiment, the address operation is analyzed based on the information of the memory test pattern source, the address operation and the command execution interval information are extracted, and the information is output in a format that can be easily grasped. Thus, the following effects can be obtained: (1) it is not necessary to perform the pattern operation many times, and the operation verification time is greatly reduced; and (2) operation verification errors are less likely to occur because no manual operation is required.

[0037]

As described above, according to the present invention, the address information necessary for analyzing the memory test pattern operation is read from the memory test pattern source, the address operation is obtained by calculation, and the pattern for pattern operation analysis is obtained. While generating an operation analysis log, (1) extracting an address operation at the time of command execution from the pattern operation analysis log,
A pattern operation comprehension log is generated, or (2) the command generation order and the interval between commands are extracted from the pattern operation analysis log to generate a command execution interval comprehension log. (A) There is no need to perform the pattern operation many times, and the operation verification time is greatly reduced. (B) Since there is no need for manual operation, there is an effect that an operation verification error hardly occurs.

[Brief description of the drawings]

FIG. 1 is an automatic verification flowchart of a memory test pattern operation according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a memory test pattern source used in the embodiment of the present invention.

FIG. 3 is a diagram showing an example of a pattern operation analysis log output created from the memory test pattern source of FIG. 2;

FIG. 4 is a diagram showing an example of a pattern operation grasping log output created from the pattern operation analysis log of FIG. 3;

FIG. 5 is a diagram showing an example of a command execution interval grasping log output created from the pattern operation analysis log of FIG. 3;

FIG. 6 is a diagram showing an operation verification system by observing a pattern waveform using an oscilloscope waveform.

FIG. 7 is a diagram showing a memory test pattern operation verification system using software attached to a semiconductor test apparatus.

FIG. 8 is a flowchart showing operation verification of a conventional memory test pattern.

9 is a diagram showing an output example of the state (“H” or “L”) of an address / I / O pin by the system of FIG. 6;

FIG. 10 is a diagram showing an example of an address operation output by the system of FIG. 6;

[Explanation of symbols]

ST1 Memory test pattern source read processing, 2
Memory pattern source file group, ST3 address operation calculation process, ST4 pattern operation analysis log output process, 5 pattern operation analysis log file, ST6 pattern operation grasp log information extraction / output process, 7 pattern operation grasp log file, ST8 command execution interval grasp Log information extraction / output processing, 9 Command execution interval grasp log file.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/16 330 G01R 31/28 B

Claims (7)

[Claims] 1. A method for reading address information necessary for analyzing a memory test pattern operation from a memory test pattern source, obtaining an address operation by calculation, and generating a pattern operation analysis log for pattern operation analysis. Operation test method for memory test patterns. 2. A method for verifying the operation of a memory test pattern, comprising extracting an address operation at the time of executing a command from the pattern operation analysis log according to claim 1, and generating a pattern operation grasping log. 3. A method for verifying the operation of a memory test pattern, wherein a command generation order and an interval between commands are extracted from the pattern operation analysis log according to claim 1, and a command execution interval grasping log is generated. . 4. A semiconductor test apparatus for verifying the operation of a memory test pattern, comprising: reading address information necessary for analyzing a memory test pattern operation from a memory test pattern source; And a means for extracting a pattern operation analysis log for generating a pattern operation analysis log from the pattern operation analysis log and generating a pattern operation grasp log. 5. A semiconductor test apparatus for verifying the operation of a memory test pattern, comprising: reading address information necessary for analyzing a memory test pattern operation from a memory test pattern source; Means for generating a pattern operation analysis log for generating a command execution interval and an interval between commands from the pattern operation analysis log, and generating a command execution interval grasping log. Semiconductor test equipment. 6. A semiconductor device having a built-in self-test circuit, comprising: reading address information necessary for analyzing a memory test pattern operation from a memory test pattern source; calculating an address operation by calculation; A semiconductor device comprising: means for generating a pattern operation analysis log; and means for extracting an address operation at the time of command execution from the pattern operation analysis log and generating a pattern operation grasp log. 7. A semiconductor device having a built-in self-test circuit, comprising: reading address information necessary for analyzing a memory test pattern operation from a memory test pattern source; calculating an address operation by calculation; A semiconductor device comprising: means for generating a pattern operation analysis log; and means for extracting a command generation order and an interval between commands from the pattern operation analysis log and generating a command execution interval grasp log.