JP2002108289A - Digital signal processing circuit and method, display device, liquid crystal display device and liquid crystal projector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that periodic longitudinal stripes is displayed on a screen caused by periodic noise superimposed on an analog signal line on a board. SOLUTION: In the digital signal processing circuit, a correction data setting block 24 is provided with a counter 33 for which an arbitrary count period is set and which receives horizontal synchronization signals HSYNC as reset inputs and conducts count operation and a selector 34 which selects beforehand set correction data based on the count value of the counter 33, and the block 24 periodically outputs the correction data. The correction data from the block 24 are added to digital data having signal processed by adder and subtractors 32-1 and 32-2 as offsets in the poststages of signal processing blocks 31-1 and 31-2 so that noise periodically superimposed on analog signals is canceled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal processing circuit and a processing method thereof, and a display device, a liquid crystal display device and a liquid crystal projector using the same.

[0002]

2. Description of the Related Art In recent years, in a display device, for example, a liquid crystal display (LCD), a digital signal processing (DSP) comprising a MOS process of a gate array as a signal processing system.
It is common to use an IC. Digital data that has been subjected to predetermined signal processing by the digital signal processing IC is converted into an analog signal by a D / A (digital / analog) converter, and then supplied to an LCD panel via an LCD driver.

In driving an LCD panel having liquid crystal cells arranged in a matrix, a vertical start pulse VST and a vertical display transfer pulse VC are used.
K, a horizontal start pulse HST, a horizontal display transfer pulse HCK, and other periodic pulses (clock pulses) are used. By driving with these periodic pulses, FIG.
As shown in the waveform diagram of FIG. 7, noise is added to the analog signal lines on the board on which the digital signal processing IC, the D / A converter, the LCD driver and the like are mounted at the edge timing.

As described above, the noise on the analog signal line on the substrate causes the horizontal display transfer pulse HCK among the periodic pulses to be generated even during the effective video period in which the display driving is actually performed. Since the clock pulse is used, when the LCD panel is driven for display based on an analog signal including noise caused by the horizontal display transfer pulse HCK, this noise component is displayed on the screen as periodic vertical streaks. .

That is, the horizontal display transfer pulse HCK is a pulse whose period is determined by the number of signal lines of the LCD panel, and its pulse width is “dot period (pixel driving period) × number of signal lines”. Then, noise generated at the timing of the change of the horizontal display transfer pulse HCK is applied to the analog signal line on the substrate, and the analog signal including the noise component is amplified, inverted, sampled and held by the LCD driver. Processing is performed.

In this sample / hold processing, the processing timing is determined by the master clock MCK of the system.
And the horizontal display transfer pulse HCK is also
Synchronous with the same master clock MCK. Therefore, the phase of the sample / hold processing timing and the phase of the noise on the analog signal due to the horizontal display transfer pulse HCK match.

As a result, in the LCD driver, a portion where the DC level fluctuates due to noise on the analog signal is sampled / held, so that the analog signal output from the LCD driver has a level corresponding to the noise. Will shift. This level difference appears as a vertical streak of the cycle of the number of signal lines on the LCD panel, and deteriorates the image quality.

Conventionally, as shown in FIG. 10, a D / A converter 101 and an LCD driver 1 are used to reduce noise caused by a periodic pulse that causes this vertical streak.
02, a low-pass filter 103 is formed by inserting a damping resistor R into the analog signal line L between the analog signal line L and a capacitor C between the output terminal of the resistor R and the ground. The method of removing was generally adopted.

[0009]

However, the resistance R
In the related art using the low-pass filter 103 including the capacitor C and the resistor R or the capacitor C, if the values of the resistor R and the capacitor C are set too large, the cutoff frequency of the low-pass filter 103 becomes low, and the filtering process extends to the original video signal. As a result, even the video signal is distorted, and the image displayed on the LCD panel 102 is blurred.

Therefore, since the values of the resistor R and the capacitor C cannot be inadvertently set large, it is difficult to completely eliminate noise. Moreover, the noise on the substrate is a minute level such as several tens of mV, and it is practically impossible to completely remove such a minute level of noise only by taking measures on the substrate.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a digital signal processing circuit capable of reliably removing noise on an analog signal due to a periodic pulse. And a processing method thereof, and a display device, a liquid crystal display device, and a liquid crystal projector using the same.

[0012]

A digital signal processing circuit according to the present invention converts an input analog video signal into an A / D signal.
A / D converter for (analog / digital) conversion,
What is claimed is: 1. A digital signal processing circuit arranged between a D / A converter for performing D / A conversion of digital data after signal processing, wherein a noise on an analog video signal after D / A conversion by said D / A converter is eliminated. A configuration including correction data setting means for periodically outputting correction data to be canceled, and adding means for adding correction data periodically output from the correction data setting means to digital data after signal processing as an offset; Has become. This digital signal processing circuit is used for a signal processing system in a display device such as a liquid crystal display device or a liquid crystal projector.

In the digital signal processing circuit having the above configuration or a display device using the same in a signal processing system, correction data for canceling noise on the analog video signal after D / A conversion is periodically generated. Such correction data is added as an offset to the digital data after the signal processing. As a result, when periodic noise is added to the analog video signal after the D / A conversion, the noise is canceled by the correction data previously added to the digital data. As a result, periodic noise on the analog video signal can be reliably canceled.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an example of the system configuration of the liquid crystal display device according to the present invention.

As shown in FIG.
A / D converters 11R, 11G, 11B provided for (red) G (green) B (blue), PLL (Phase Locked)
Loop) circuit 12, digital signal driver (DSD)
IC13, D / A converters 14R-1, 14R-2,
14G-1, 14G-2, 14B-1, 14B-2, L
CD drivers 15R-1, 15R-2, 15G-1, 1
5G-2, 15B-1, 15B-2 and LCD panels 16R, 16G, 16B.

In this system, the digital input to the digital signal driver IC 13 is 8-bit parallel, the signal processing inside the digital signal driver IC 2 and its digital output are 10-bit parallel, and the LCD drivers 15R-1, 15R-2, 15G- 1,15G-2,
It is assumed that the number of output CHs (channels) of 15B-1 and 15B-2 is 6, and the number of signal lines of the LCD panels 16R, 16G and 16B is 12. However, these numerical values are merely examples, and in particular, the number of signal lines between the LCD driver and the LCD panel, that is, the number of signal lines of the LCD panel is not limited to this.

A / D converters 11R, 11G, 11B
Are analog video signals Rin, Gin, Bin of R, G, B, respectively.
Are subjected to A / D conversion, and are output as digital data of a plurality of systems, for example, two systems. That is, as shown in FIG. 2, the digital data DATA synchronized with the master clock MCLK is demultiplexed into two-system digital data of port 1 and port 2 and output.
Here, in the A / D converters 11R, 11G, and 11B, the digital data DATA is demultiplexed into a plurality of systems, for example, two systems of digital data for the following reason.

That is, when considering a system having a high driving frequency, the A / D converters 11R, 11G, 11B
Can operate at high speed because it is usually formed by a bipolar process. However, the digital signal driver IC2 formed by a MOS process cannot operate if the driving frequency is too high, or noise can be reduced by unnecessary radiation caused by a high-frequency clock. Or increase. For this reason,
A / D conversion of input analog video signals Rin, Gin, Bin
When converting into digital data by the converters 11R, 11G, and 11B, the subsequent drive frequency is reduced by demultiplexing the data into a plurality of systems for each channel.

The PLL circuit 12 is provided with a horizontal synchronizing signal HS which is synchronously separated from an input analog video signal and applied.
A master clock MCLK, a horizontal synchronization signal HSYNC, and a vertical synchronization signal VSYNC used in the present system are generated based on the YNC and the vertical synchronization signal VSYNC,
This is given to the digital signal driver IC13.

The digital signal driver IC 13 includes:
Digital signal processing blocks 21R, 21G, 21B provided for R, G, B, serial I / F (interface) 22, timing generator (TG) 2
3 and a correction data setting block 24. Digital signal processing block 21R, 21
Specific configurations of the G, 21B and the correction data setting block 24 will be described later.

Various information (coefficients) is given to the serial I / F 22 as serial data from a microcomputer (not shown) that controls the entire system. And serial I / F22
Receives the serial data, controls the digital signal processing blocks 21R, 21G, 21B and the correction data setting block 24, and controls the timing of the timing generator 23.

The timing generator 23 has a PLL
The master clock MCLK, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC generated by the circuit 12 are supplied. The timing generator 23 outputs the master clock MCLK and the synchronization signals HSYNC and VSYNC.
Various timing signals are generated based on C, and all timing control of the present system is performed.

D / A converters 14R-1, 14R-
2.14G-1, 14G-2, 14B-1, 14B-2
Is a digital signal processing block 21R-21G-21B of the digital signal driver IC13, which separately performs digital-to-analog conversion on each of R, G, and B digital data subjected to various types of signal processing, and performs an LCD driver 15R-1. , 15R
-2,15G-1,15G-2,15B-1,15B-
Feed to 2.

The LCD drivers 15R-1, 15R
-2,15G-1,15G-2,15B-1,15B-
2 is a D / A converter 14R-1, 14R-2, 14
Amplification processing, 1H (H is a horizontal scanning period) inversion processing, and sampling for each of two analog video signals of R, G, and B supplied from G-1, 14G-2, 14B-1, and 14B-2. After performing a / hold process and the like, the data is supplied to the LCD panels 16R, 16G, and 16B.

The LCD panels 16R, 16G, 16B are:
LCD panels 16R, 16G, 16B in which pixels (not shown) including liquid crystal cells are arranged in a matrix,
It is driven based on periodic pulses such as a vertical start pulse VST, a vertical display transfer pulse VCK, a horizontal start pulse HST, and a horizontal display transfer pulse HCK generated by the timing generator 23, and according to an input analog video signal. Image display.

Next, a specific configuration of the digital signal processing blocks 21R, 21G, 21B and the correction data setting block 24, which are characteristic portions of the present invention, will be described.
Here, the digital signal processing blocks 21R, 21G, 2
1B and the correction data setting block 24 are characterized in that, in addition to the original signal processing, in order to remove the noise that periodically rides on the analog signal line on the substrate, the video signal is periodically offset in advance. The point is to perform the attaching process.

[First Embodiment] FIG. 3 is a block diagram showing a configuration example of a digital signal processing circuit (digital signal processing blocks 21R, 21G, 21B and a correction data setting block 24) according to a first embodiment of the present invention. It is. The digital signal processing block 2 corresponding to R, G, B
1R, 21G, and 21B have exactly the same configuration, and in the following description, they are commonly described as a digital signal processing block 21.

The digital signal processing block 21 has signal processing blocks 31-1 and 31- having an original signal processing function.
2 and adder / subtracters 32-1 and 32-2 arranged at the subsequent stage.
And Here, the signal processing blocks 31-1,
The original signal processing performed in 31-2 includes user adjustment,
White balance adjustment, OSD (On Screen Display) M
IX (processing for displaying another screen such as a menu screen on a display screen), and signal processing for performing normal image quality adjustment such as gamma correction.

The adders / subtracters 32-1 and 32-2 add or subtract the correction data set in the correction data setting block 24 to or from each digital data of the port 1 and the port 2 to obtain a video signal. To periodically perform offset processing. This offset is used to cancel noise on the analog video signal, as will be described later in detail.

The correction data setting block 24 is a counter 3 for setting the cycle of the offset to be added to the video signal.
3 and a selector 34 for selecting correction data based on the count value of the counter 33. The mode setting information and correction data used in the correction data setting block 24 are stored in the signal processing blocks 31-1 and 31-3.
Similarly, the serial I / F 22 according to the serial data input from the external microcomputer such as the coefficient used in 1-2.
(See FIG. 1).

In the correction data setting block 24, the counter 33 is for setting a fixed period for adding correction data to the video signal, and performs a count operation in synchronization with the master clock MCK. The reset is applied at the edge of the horizontal synchronization signal HSYNC. The count cycle of the counter 33 is such that the cycle of processing for adding correction data to the video signal is a horizontal display transfer pulse H which is one of the periodic pulses for driving the LCD panels 16R, 16G, and 16B.
It can be set by mode setting information given from the outside so as to match the pulse width (Δt) of CK.

The selector 34 uses the output value (count value) of the counter 33 as a select signal, and selects externally applied correction data by looking at the count value. As a result, as shown in the timing chart of FIG. 4, the correction data is periodically output from the correction data setting block 24 to the ports 1 and 2, respectively, and the adders / subtractors 32-1 and 32 of the digital signal processing block 21 are output. -2.

The timing chart of FIG. 4 shows an example in which the count cycle of the counter 33 is "6". In this example, 6 is assigned to port 1 and port 2.
12 correction data DATA1 to DATA1
2 is output periodically. As a result, the pulse width of the horizontal display transfer pulse HCK in this case (Δ
t) is equivalent to 12 clocks of the master clock MCK.

As the correction data to be given to the selector 34, data with a sign bit is used. As a result, either positive or negative offset value can be added to the video signal. Note that the noise that periodically gets on the analog signal line on the board is determined by the drive frequency of the system, components and wiring on the board, and the like, and thus occurs at a substantially constant level on the board.

Therefore, a fixed value (a polarity opposite to that of the noise) may be set as the offset (correction data) added in advance to the video signal in order to cancel the noise. Therefore, when the system is developed, the level of the noise on the analog signal line caused by the horizontal display transfer pulse HCK is quantitatively grasped, and correction data for canceling the noise is set in the selector 34 from an external microcomputer. To

Next, the operation of the digital signal processing block 21 and the correction data setting block 24 according to the first embodiment having the above configuration will be described with reference to the waveform diagram of FIG.

First, correction data and mode setting information are set from the external microcomputer to the correction data setting block 24 through the serial I / F 22. At this time, since the level of noise on the analog signal line due to the horizontal display transfer pulse HCK is almost constant,
A fixed value is set as the correction data. At this time,
As a matter of course, the correction data is set with a polarity opposite to that of the noise.

Here, the pulse width (.DELTA.t) of the horizontal display transfer pulse HCK is equal to, for example, 1 of the master clock MCK.
Assuming two clocks, "6" is set as mode setting information from an external microcomputer as the count cycle of the counter 33. Thereby, from the selector 34,
As shown in the timing chart of FIG. 4, a total of twelve correction data DATA1 to DATA6 are provided for each of port 1 and port 2.
DATA 12 is output periodically.

This correction data is input to the adders / subtractors 32-1 and 32-2 of the digital signal processing block 21.
These adders / subtracters 32-1 and 32-2 are provided for each of port 1 and port 2 that have undergone image adjustment such as user adjustment, white balance adjustment, OSD MIX, and gamma correction in the signal processing blocks 31-1 and 31-2. A process of adding correction data (waveform 2) selected by the selector 34 to the digital data (waveform 1) based on the count value of the counter 33 is performed.

Thus, the adders / subtracters 32-1 and 32-2
Outputs digital data (waveform 3) of ports 1 and 2 to which correction data of the opposite polarity has been added to the noise. The digital data of the port 1 and the port 2 on which the correction data is superimposed are supplied to a D / A converter (D / A converters 14R-1, 14R-2, and 14G in FIG.
-1, 14G-2, 14B-1, 14B-2) to perform D / A conversion to an analog video signal.

After the D / A conversion, if the noise generated at the timing when the horizontal display transfer pulse HCK changes appears on the analog signal line on the substrate, the level of the noise is almost constant, Since the polarity correction data is superimposed on the video signal in advance, the noise and the correction data cancel each other out. As a result, the analog video signals input to the LCD panels 16R, 16G, and 16B are noise-free. The waveform becomes smooth (waveform 4).

Here, the interpolation data superimposed on the video signal at the same level with respect to the noise of almost constant level is affected by the level of image quality adjustment in the signal processing blocks 31-1 and 31-2. The level must not change at For this reason, the adders / subtractors 32-1 and 32-2 provided for noise cancellation are provided at the last stage in the signal processing blocks 31-1 and 31-2, in this example, the signal processing blocks 31-1 and 31-2. It is important to provide it after.

[Second Embodiment] FIG. 6 is a block diagram showing a configuration example of a digital signal processing circuit (digital signal processing blocks 21R, 21G, 21B and a correction data setting block 24) according to a second embodiment of the present invention. It is. The digital signal processing block 2 corresponding to R, G, B
1R, 21G, and 21B have exactly the same configuration, and in the following description, they are commonly described as a digital signal processing block 21.

The digital signal processing block 21 has exactly the same configuration as that of the first embodiment. That is, the digital signal processing block 21 performs signal processing blocks 31-1 and 31-2 for performing image quality adjustment processing.
And adder / subtracters 32-1 and 32-2 arranged at a subsequent stage to perform addition / subtraction processing of correction data with respect to the video signal. The details of the signal processing blocks 31-1 and 31-2 and the adders / subtracters 32-1 and 32-2 are the same as those in the first embodiment, and thus description thereof is omitted here.

The correction data setting block 24 includes a counter (1) 35, a decoder 36, a counter (2) 37, and a selector 38. The correction data, mode setting information and reset value setting information used in the correction data setting block 24 are stored in a signal processing block 31.
Similarly, the serial data input from an external microcomputer, such as coefficients used in
/ F22 (see FIG. 1).

In the correction data setting block 24, the counter (1) 35 performs a counting operation in synchronization with the master clock MCK, and is reset at the edge of the horizontal synchronization signal HSYNC. The count value of this counter (1) 35 is
6 given. The decoder 36 has a counter (1) 35
Is decoded and applied to the counter (2) 37 as a reset pulse indicating the reset position. The output timing of the reset pulse, that is, the reset position can be arbitrarily set based on the reset value setting information.

The counter (2) 37 performs the same operation as the counter 33 in the first embodiment based on the reset pulse supplied from the decoder 36. The count cycle of the counter (2) 37 is set to a mode given from the outside so that the cycle of processing for adding correction data to the video signal matches the pulse width (Δt) of the horizontal display transfer pulse HCK. It can be set by setting information.

The selector 38 uses the output value (count value) of the counter (2) 37 as a select signal, and selects externally applied correction data by looking at the count value. As a result, as shown in the timing chart of FIG.
A1 to DATA12 are output and supplied to the adders / subtracters 32-1 and 32-2 of the digital signal processing block 21.

In the correction data setting block 24 according to the second embodiment, the reset timing of the counter (2) 37 for determining the output timing of the correction data to be added to the video signal, that is, the phase of the reset pulse is set from the microcomputer. The configuration can be freely set by the decoding process in the decoder 36 based on the reset value setting information to be performed.

Here, in contrast to the case of the first embodiment (FIG. 3), in the first embodiment, the counter 33 corresponding to the counter (2) 37 of the second embodiment sets the horizontal synchronizing signal HSYNCK to a reset pulse. , The phase relationship between the horizontal synchronization signal HSYNCK and the output value (count value) of the counter 33 is uniquely determined.

Therefore, when the output timing of the horizontal display transfer pulse HCK with respect to the horizontal synchronization signal HSYC changes depending on the format of the video signal to be displayed, it is necessary to reset the correction data accordingly. . In the resetting of the correction data at this time, the correction data DATA in the timing chart of FIG.
The output timing of 1 to DATA 12 is changed on the microcomputer side in accordance with the phase change amount of the horizontal display transfer pulse HCK.

In the timing chart of FIG. 4, the case where the count cycle of the counter 33 is set to "6" is taken as an example, so that a total of twelve correction data DATA1 to DATA12, Considering the case of three channels of G and B, the output timing must be reset for 36 pieces of correction data in total of three channels.

On the other hand, in the correction data setting block 24 according to the second embodiment, the reset timing of the counter (2) 37 for determining the output timing of the correction data to be added to the video signal can be freely set. When the phase of the horizontal display transfer pulse HCK changes due to the format of the video signal to be displayed or the like, the reset value setting information given from the microcomputer is changed to change the reset timing of the counter (2) 37.
It can respond to the phase change of the horizontal display transfer pulse HCK.

That is, considering the example of FIG. 4, when the output timing of the horizontal display transfer pulse HCK with respect to the horizontal synchronizing signal HSYC changes according to the format of the video signal to be displayed, etc. In the correction data setting block 24, R, G, and B total 36
The output timing of the correction data must be reset. On the other hand, in the correction data setting block 24 according to the second embodiment, only the reset value setting information set for the decoder 36 from the microcomputer is changed without resetting the output timing of the correction data. Can respond to the phase change of the horizontal display transfer pulse HCK.

[Modifications] In each of the above embodiments, the level of the noise on the analog signal line caused by the horizontal display transfer pulse HCK is quantitatively grasped in the correction data, and the correction is performed to cancel the level. It is assumed that data is set from the microcomputer to the selector 34 (FIG. 3) and the selector 38 (FIG. 6). In this system, however, the noise level is actually detected and fed back to the microcomputer, and the microcomputer outputs interpolation data corresponding to the detected level. Can also be set automatically.

That is, as shown in FIG. 7, the D / A converter 14 (D / A converters 14R-1 and 14R-1 in FIG. 1)
R-2, 14G-1, 14G-2, 14B-1, 14B
-2) and an LCD driver 15 (LCD drivers 15R-1, 15R-2, 15G-1, 15G-
2, 15B-1 and 15B-2), a level detector 39 is connected to the analog signal line L, and the level detector 39 detects the level of noise on the analog signal line L, and detects this level. The level is fed back to the microcomputer.

As shown in FIG. 7, the level detector 39 cuts a noise component included in an analog video signal output from the D / A converter 14 and extracts only a signal component. LPF) 391
And a subtractor 392 that extracts a noise component by subtracting an output signal of the low-pass filter 391, that is, a signal component from an analog video signal containing a noise component.

In each of the above embodiments, the case where the present invention is applied to a color liquid crystal display device is described as an example. However, the present invention is not limited to the application to a color liquid crystal display device, but is applied to a monochrome liquid crystal display device. Further, a clock pulse periodically generated even in an effective video period, for example, a horizontal display transfer pulse HCK, such as a display device using a CRT (cathode ray tube) or an organic EL element as a display device, is handled. The present invention is applicable to general display devices.

[Application Example] Further, the digital signal processing block 21 (21R, 21G, 21
B) can be used as a digital signal processing circuit of a liquid crystal projector. FIG. 8 shows a schematic configuration of a liquid crystal projector.

In FIG. 8, white light emitted from a light source 41 is converted into a specific color component by a first beam splitter 42.
For example, only the B (blue) light component having the shortest wavelength is transmitted,
Light components of the remaining colors are reflected. The light component of B transmitted through the first beam splitter 42 has its optical path changed by a mirror 43, and is irradiated on the LCD panel 11 B of B through a lens 44.

With respect to the light component reflected by the first beam splitter 42, for example, a G (green) light component is reflected by the second beam splitter 45, and an R (red) light component is transmitted. The G light component reflected by the second beam splitter 45 passes through the lens 46 to the G LCD panel 11G.
Is irradiated. The light component of R transmitted through the second beam splitter 45 has its optical path changed by mirrors 47 and 48 and is irradiated on the R LCD panel 11R through the lens 49.

The R, G, and B lights passing through the LCD panels 11R, 11G, and 11B are combined by the cross prism 50. The combined light emitted from the cross prism 50 is projected on a screen 52 by a projection prism 51.

In the liquid crystal projector having the above structure, L
To the CD panels 11R, 11G, and 11B, for example, two-system video signals processed in parallel for each of R, G, and B by the signal processing system shown in FIG. 1 are input.

Here, the above-described first or second embodiment is applied to the digital signal processing blocks 21R, 21G, and 21B of the digital signal driver 13, so that the digital signal processing blocks 21R, 21G, and 21B periodically occur even in the effective video period. Since the noise on the analog video signal due to the clock pulse, for example, the horizontal display transfer pulse HCK can be reliably removed, the LCD panels 11R, 11G, 11
An analog video signal without noise is input to B.
Thereby, when an image is displayed on the screen 52,
Since the occurrence of vertical streaks in the cycle of the number of signal lines due to the horizontal display transfer pulse HCK can be suppressed, a good image display can be realized.

Although the present invention has been described with reference to a case where the present invention is applied to a color liquid crystal projector, the present invention can be similarly applied to a monochrome liquid crystal projector. In this case, it is needless to say that the signal processing system needs only one channel.

[0066]

As described above, according to the present invention,
The periodic correction data is added to the digital data after the signal processing as an offset, so that the D / A
When periodic noise is added to the converted analog video signal, the periodic noise can be reliably removed by canceling the periodic noise with the correction data previously added to the digital data. It is possible to reliably suppress the occurrence of a vertical streak.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a system configuration of a liquid crystal display device according to the present invention.

FIG. 2 is a timing chart for explaining an operation of demultiplexing digital data of port 1 and port 2 by an A / D converter.

FIG. 3 is a block diagram illustrating a configuration example of a digital signal processing circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing a relationship between a counter operation and a selector output in the digital signal processing circuit according to the first embodiment.

FIG. 5 is a waveform chart for explaining an operation of noise cancellation.

FIG. 6 is a block diagram illustrating a configuration example of a digital signal processing circuit according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a modification of the present invention.

FIG. 8 is a schematic configuration diagram illustrating an example of a liquid crystal projector.

FIG. 9 is a waveform diagram showing how noise is added to an analog signal due to a horizontal display transfer pulse HCK.

FIG. 10 is a circuit diagram for explaining a problem of the related art.

[Explanation of symbols]

11R, 11G, 11B A / D converter, 13 Digital signal driver, 14R-1, 14R-2, 1
4G-1, 14G-2, 14B-1, 14B-2 ... D /
A converter, 15R-1, 15R-2, 15G-1,
15G-2, 15B-1, 15B-2 ... LCD driver, 16R, 16G, 16B ... LCD panel, 21, 22
1R, 21G, 21B ... digital signal processing block, 3
1-1, 31-2 ... signal processing block, 32-1, 32
-2: adder / subtracter, 33, 35, 37 ... counter, 34,
38 counter, 36 decoder, 39 level detector

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 642 G09G 3/20 642A 680 680C F-term (Reference) 2H088 EA12 HA06 MA20 2H093 NC23 NC24 NC25 NC27 ND40 NG02 5C006 AA16 AA22 AF46 AF51 AF81 AF83 BC16 BF15 BF21 BF22 BF24 BF26 BF28 EA01 EC11 FA18 FA22 FA31 5C080 AA10 BB05 CC03 DD05 DD12 JJ02 JJ04 JJ06

Claims (27)

[Claims] 1. A digital signal processing circuit arranged between an A / D converter for A / D converting an input analog video signal and a D / A converter for D / A converting digital data after signal processing. Correction data setting means for periodically outputting correction data for canceling noise on an analog video signal after D / A conversion by the D / A converter; and periodically output from the correction data setting means. A digital signal processing circuit comprising: adding means for adding correction data to the digital data after signal processing as an offset. 2. The correction data setting means selects a counter whose count cycle can be set arbitrarily and operates by using a horizontal synchronization signal as a reset input, and a preset correction data based on a count value of the counter. 2. The digital signal processing circuit according to claim 1, further comprising a selector for supplying the signal to said adding means. 3. The correction data setting means includes: a first counter that counts using a horizontal synchronization signal as a reset input; a counter that decodes a count value of the first counter to output a reset pulse; A decoder whose output timing can be arbitrarily set; a second counter that counts using the reset pulse as a reset input; and selecting preset correction data based on a count value of the second counter. 2. The digital signal processing circuit according to claim 1, further comprising a selector for supplying the signal to the adding unit. 4. The apparatus according to claim 1, wherein said adding means is an adder / subtracter for adding or subtracting correction data periodically output from said correction data setting means to digital data after signal processing. 2. The digital signal processing circuit according to 1. 5. The digital signal processing circuit according to claim 1, wherein the correction data is data with a sign bit. 6. Digital signal processing for performing signal processing between an A / D converter for A / D converting an input analog video signal and a D / A converter for D / A converting digital data after signal processing. A method of periodically generating correction data for canceling noise on an analog video signal after D / A conversion by the D / A converter, and offsetting the periodic correction data to digital data after signal processing. A digital signal processing method characterized by adding 7. A display for displaying an image, an A / D converter for A / D converting an input analog video signal,
A digital signal processing circuit for performing predetermined signal processing on digital data output from the A / D converter;
A D / A converter that D / A converts digital data output from the digital signal processing circuit and supplies the digital data to the display unit, wherein the digital signal processing circuit includes the D / A converter. A correction data setting means for periodically outputting correction data for canceling noise on the analog video signal after the D / A conversion, and a correction data periodically output from the correction data setting means for digital processing after signal processing. A display device comprising: an adding unit for adding an offset to data. 8. The display device according to claim 7, wherein a cycle at which the correction data is output is a cycle of a periodic pulse for driving the display unit in an effective video period. 9. The display device according to claim 8, wherein the periodic pulse is a horizontal display transfer pulse. 10. The correction data setting means selects a counter whose count cycle can be set arbitrarily and counts using a horizontal synchronization signal as a reset input, and selects preset correction data based on the count value of the counter. 8. The display device according to claim 7, further comprising: a selector that supplies the data to the adding unit. 11. The correction data setting means includes: a first counter that counts using a horizontal synchronization signal as a reset input; a counter that decodes a count value of the first counter to output a reset pulse; A decoder whose output timing can be set arbitrarily,
A second counter that counts using the reset pulse as a reset input; and a selector that selects preset correction data based on the count value of the second counter and supplies the selected correction data to the adding unit. The display device according to claim 7, wherein 12. The adder / subtracter for adding or subtracting correction data periodically output from the correction data setting means to digital data after signal processing. 7. The display device according to 7. 13. The display device according to claim 7, wherein the correction data is data with a sign bit. 14. A display unit in which liquid crystal cells are arranged in a matrix, and an analog video signal to be input to an A / D converter.
A / D converter for conversion, a digital signal processing circuit for performing predetermined signal processing on digital data output from the A / D converter, and D / A conversion of digital data output from the digital signal processing circuit And a D / A converter that supplies the digital video signal to the display unit. The digital signal processing circuit cancels noise on the analog video signal after the D / A conversion by the D / A converter. Correction data setting means for periodically outputting correction data to be processed, and addition means for adding correction data periodically output from the correction data setting means to digital data after signal processing as an offset. Liquid crystal display device. 15. A cycle in which the correction data is output,
The liquid crystal display device according to claim 14, wherein a period of a periodic pulse for driving the display unit during an effective video period is provided. 16. The liquid crystal display device according to claim 15, wherein the periodic pulse is a horizontal display transfer pulse. 17. The correction data setting means selects a counter whose count cycle can be set arbitrarily and counts using a horizontal synchronization signal as a reset input, and preset correction data based on a count value of the counter. 15. The liquid crystal display device according to claim 14, further comprising: a selector that supplies the data to the adding unit. 18. A correction data setting means, comprising: a first counter that counts using a horizontal synchronization signal as a reset input; a counter that decodes a count value of the first counter to output a reset pulse; A decoder whose output timing can be set arbitrarily,
A second counter that counts using the reset pulse as a reset input; and a selector that selects preset correction data based on the count value of the second counter and supplies the selected correction data to the adding unit. The liquid crystal display device according to claim 14, wherein 19. The adder / subtractor for adding or subtracting correction data periodically output from the correction data setting means to digital data after signal processing. 15. The liquid crystal display device according to 14. 20. The liquid crystal display device according to claim 14, wherein the correction data is data with a sign bit. 21. An LCD panel in which liquid crystal cells are arranged in a matrix, irradiation means for irradiating the LCD panel with light, and projection means for projecting light passing through the LCD panel onto a screen. An A / D converter for A / D converting an analog video signal, a digital signal processing circuit for performing predetermined signal processing on digital data output from the A / D converter, and an output from the digital signal processing circuit A liquid crystal projector comprising: a digital-to-analog (D / A) converter for converting digital data into digital data and supplying the digital data to the LCD panel; Correction data setting means for periodically outputting correction data for canceling noise on the signal; and LCD projector and having a adding means for adding a period to output the corrected offset data to digital data after signal processing. 22. A cycle at which the correction data is output,
22. The liquid crystal projector according to claim 21, wherein a period of a periodic pulse for driving the display unit during an effective video period is provided. 23. The liquid crystal projector according to claim 22, wherein the periodic pulse is a horizontal display transfer pulse. 24. The correction data setting means, wherein a counting cycle can be arbitrarily set, and a counter which counts using a horizontal synchronization signal as a reset input and a preset correction data are selected based on a count value of the counter. 22. The liquid crystal projector according to claim 21, further comprising: a selector that supplies the data to the adding unit. 25. The correction data setting means, comprising: a first counter that counts using a horizontal synchronization signal as a reset input; a counter that decodes a count value of the first counter to output a reset pulse; A decoder whose output timing can be set arbitrarily,
A second counter that counts using the reset pulse as a reset input; and a selector that selects preset correction data based on the count value of the second counter and supplies the selected correction data to the adding unit. The liquid crystal projector according to claim 21, wherein 26. The adder / subtractor for adding or subtracting correction data periodically output from the correction data setting means to digital data after signal processing. 24. The liquid crystal projector according to 21. 27. The liquid crystal projector according to claim 21, wherein the correction data is data with a sign bit.