JP2002101077A - Method for reducing jitter and device for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce jitters of a digital signal, such as a bi-phase digital voice signal which has been subjected to bi-phase mark modulation. SOLUTION: An input digital signal Da is delayed so that a signal DB for delay, a normal signal DN, and a signal DF for progress can be generated. Signal GB, GNd, and GFdd are generated from a jitter detection result, and the logical sum is generated as a signal Gor. In a period when jitter exceeding a prescribed ranged is absent, the logical product of the signal GNd and the signal DN is outputted as a signal DG, in a period when any jitter in a progressing direction is present, the logical sum of the signal GFdd and the signal DF is outputted as the signal DG, and in a period when any jitter for a delay direction is present, the logical product of the signal GB and the signal DB is outputted as the signal DG. The value of the signal DG at the rising edge of a clock CL, when the signal Gor is at high level is read, to generate an output digital signal Dc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method and an apparatus for reducing jitter of a digital signal such as a digital audio signal.

[0002]

2. Description of the Related Art For example, a CD (Compact Digest) between digital audio equipment for consumer and broadcast studio use.
sc) player, MD (Mini Disc) player, DVD (Digital Versatile D)
isc) player, DAT (Digital Audio)
o Taperecoder) A serial unidirectional interface for digital connection between a transmitting device such as a player and a receiving device that receives a digital audio signal transmitted from the device and converts it into an analog audio signal includes I
EC (International Electrot)
An interface conforming to the (TechnicalCommission) 958 standard is used.

[0003] The digital audio interface of the IEC958 standard is a self-synchronous system. On the receiving device side, a clock is reproduced from a received digital audio signal, and the reproduced clock is used to convert a digital audio signal into an analog audio signal.

In the format of the digital audio interface of the IEC958 standard, as shown in FIG. 9, one subframe for transmitting data of one sample of audio of channel 1 and channel 2 (for example, left channel and right channel) is used. A frame is formed, and one block is formed by 192 frames from frame 0 to frame 191.

The frame transmission rate is the same as the audio sampling rate, and the audio sampling frequency is fs.
Then, one frame is 1 / fs (second). For example, for a CD or the like, fs = 44.1 kHz,
One frame is about 22.7 microseconds.

[0006] At the beginning of each subframe, a synchronization preamble B, M or W is added. Synchronous preamble B
Indicates the beginning of a block, the synchronization preamble M indicates the beginning of a frame or subframe of channel 1,
The synchronization preamble W indicates the head of the subframe of channel 2.

[0007] As shown in FIG.
A maximum of 24 bits can be transmitted as audio data after the synchronization preamble of 4 bits, and 1 bit each of the validity flag V, user data U, channel Status C and parity bit P can be transmitted.

In practice, digital audio signals of the above format are bi-phase mark modulated to suppress the DC component, facilitate clock recovery, and allow data to be transmitted regardless of the polarity of the connection. Transmitted.

In the bi-phase mark modulation, as shown in FIG. 11, when data before modulation is source data and data after modulation is bi-phase mark signal, the bi-phase mark signal is generated at the boundary of each bit of the source data. When the source data is 1, the biphase mark signal is inverted even in the middle of the bit.
When the source data is 0, the source data is modulated so that the biphase mark signal is not inverted in the middle of the bit.

Therefore, the bi-phase mark modulation requires a clock having a frequency twice as high as that of the source data, as shown as a bi-phase clock. One frame is composed of 64 bits and the frequency of the source data is 6 bits.
4 fs, the frequency of the biphase clock is 1
28 fs.

FIG. 12 shows a conventional transmitting device for outputting a digital audio signal modulated in such a way as described above. In the transmitting device 10, in the digital audio output circuit 13, the digital audio signal of the format as shown in FIGS. 9 and 10 from the pre-stage circuit 12 is separated from the clock having the frequency fa = 256fs from the clock generation circuit 17. As shown in FIG. 11, bi-phase mark modulation is performed by a bi-phase clock having a frequency fb = 128 fs generated by frequency division by the frequency divider 14, and the modulated digital audio signal is output from the output terminal 19 to the receiving device. Sent.

From the general tendency of integration, the pre-stage circuit 1
2, the digital audio output circuit 13 and the frequency dividing circuit 14,
Other circuits use one LSI (Large Scal
e Integrated circuit) 11, and the clock generation circuit 17 is provided outside the LSI 11.

When the transmitting device 10 is an audio reproducing device such as a CD player or an MD player, the pre-stage circuit 12 decodes an encoded digital audio signal reproduced from a recording medium such as a CD or an MD. And so on.

FIG. 13 shows an example of a receiving device. In the receiving device 20, the digital audio signal after the biphase mark modulation transmitted from the transmitting device 10 as described above is:
Received as digital audio input, clock recovery PL
An L (Phase Locked Loop) 22 reproduces a clock from the bi-phase mark modulated digital audio signal.

The bi-phase decoder 23 demodulates the digital audio signal subjected to the bi-phase mark modulation by the reproduced clock, and generates a DAC (Digital) signal.
tal to Analog Converter) 2
4, the demodulated digital audio signal is transmitted to channel 1
And an analog audio signal of channel 2. The analog audio signal is amplified by audio amplifiers 25 and 26, respectively, and led to output terminals 27 and 28. Speakers, headphones, earphones, and the like are connected to the output terminals 27 and 28, from which audio of channel 1 and channel 2 is output.

[0016]

As shown in FIG. 12, in a transmitting apparatus 10, a pre-stage circuit 12, a digital audio output circuit 13, a frequency dividing circuit 14, and other circuits are integrated in one LSI 11. You. Therefore, the first-stage circuit 1
2 and other noises from the other circuits affect the output signal of the digital audio output circuit 13, causing jitter in the digital audio signal from the digital audio output circuit 13.

FIG. 14 shows this. When no jitter occurs, the rising edge and the falling edge of the signal are, for example, immediately after the rising edge of the biphase clock, as shown as a digital audio signal without jitter. In contrast, when jitter occurs, as shown as a digital audio signal with jitter,
The rising edge and the falling edge of the signal fluctuate in a time-advancing or lagging direction as indicated by leftward or rightward arrows.

When jitter is generated in the digital audio signal output from the transmitting device 10 and subjected to the biphase mark modulation, the clock reproduced by the clock reproducing PLL 22 of the receiving device 20 shown in FIG. And the analog audio signal output from the DAC 24 after DA conversion by the reproduced clock is distorted, and the audio output from a speaker or the like connected to the output terminals 27 and 28 is distorted. . for that reason,
It is necessary to reduce the jitter of the bi-phase mark modulated digital audio signal output from the transmitting device 10.

As a method of reducing the jitter of a digital signal such as a digital audio signal subjected to bi-phase mark modulation, a method of reading the digital signal in synchronization with a clock using a D flip-flop can be considered.

In the case of the transmission device 10 described above, FIG.
As shown in FIG. 2, a D flip-flop 18 is provided outside the LSI 11 so that the digital audio output circuit 1 in the LSI 11 is provided.
3 is input to the data terminal of the D flip-flop 18, and the jitter-free clock CL having the frequency fa = 2fb = 256fs from the clock generation circuit 17 is input to the clock terminal of the D flip-flop 18. Then, the digital audio signal Db output from the D flip-flop 18 is transmitted as a digital audio output.

According to this, the digital audio output circuit 13
Assuming that the digital audio signal Da is an input signal Da and the digital audio signal Db output from the D flip-flop 18 is an output signal Db, as shown in FIG. Immediately after clock C
L rises at the rising edge of L, and falls at the rising edge of the clock CL immediately after the fall of the input signal Da, so that the rising Cu and the falling Cd of the input signal Da are as shown by arrows Ju and Jd. Between the rising edge of the clock CL immediately before the original position and the rising edge of the clock CL immediately after the original position (for the rising Cu, the edge e4
Between edge e5 and falling edge Cd
8 and the edge e9), a jitter-free signal is obtained as the output signal Db.

However, as shown in FIG. 16B, the rising Cu and the falling Cd of the input signal Da correspond to the rising edge of the clock CL immediately before the original position, as shown by arrows J4 and J8. (The edge e4 for the rising Cu and the edge e8 for the falling Cd), the low-level periods NG1 and N
As shown by G2, rising Cu and falling C
A jittered signal is obtained in which the rising edge and the falling edge corresponding to d advance by one cycle of the clock CL with respect to the correct position.

As shown in FIG. 16C, the rising Cu and the falling Cd of the input signal Da are expressed by
As shown by arrows J5 and J9, the rising edge of the clock CL (rising C
If u is delayed in time beyond edge e5 and falling Cd is beyond edge e9), output signal Db corresponds to rising Cu and falling Cd as shown by low-level periods NG3 and NG4. A rising signal and a falling edge are delayed by one cycle of the clock CL with respect to a correct position, and a signal with jitter is obtained.

Therefore, the present invention is designed to reduce the jitter within a predetermined range when the digital signal has a jitter exceeding a predetermined range.

[0025]

According to the jitter reducing method of the present invention, a clock synchronized with an input digital signal is used to detect whether or not the input digital signal has a jitter exceeding a predetermined range. According to the result, the input digital signal is processed using the clock to generate an output digital signal.

A jitter reducing apparatus according to the present invention uses a clock synchronized with an input digital signal to detect whether or not the input digital signal has a jitter exceeding a predetermined range. And a digital signal processing means for processing the input digital signal using the clock to generate an output digital signal.

In the jitter reducing method or the jitter reducing apparatus of the present invention configured as described above, even if the input digital signal has a jitter exceeding a predetermined range, the jitter of the output digital signal is reduced to a predetermined range. Is obtained.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment of Jitter Reduction Method and Jitter Reduction Apparatus] FIG. 1 shows an IE equipped with a jitter reduction apparatus of the present invention according to the jitter reduction method of the present invention.
1 shows an example of a transmission device including a digital audio interface (serial one-way interface) conforming to the C958 standard.

In the transmitting device 10 of this example, like the transmitting device 10 shown in FIG. 12 or FIG.
The digital audio output circuit 13, the frequency dividing circuit 14, and other circuits are integrated in one LSI 11, the clock generation circuit 17 is provided outside the LSI 11, and the digital audio output circuit 13 FIG.
And a digital audio signal having a format as shown in FIG.
As shown in FIG. 11, bi-phase mark modulation is performed by a bi-phase clock having a frequency fb = 128 fs generated by dividing the frequency of the 256 fs clock by the frequency dividing circuit 14.

In this example, a jitter reducing circuit 16 having a configuration described later is provided outside the LSI 11, and a bi-phase mark modulated digital audio signal Da from the digital audio output circuit 13 and a clock generation circuit 17 are provided.
Is supplied to the jitter reduction circuit 16, and the digital audio signal Dc output from the jitter reduction circuit 16 is output from the output terminal 19 as an output of the transmission device 10 from the output terminal 19. It is transmitted to the receiving device 20 as shown in FIG.

The jitter reducing circuit 16 and the clock generating circuit 17 can be integrated in one LSI 15 separate from the LSI 11, or can be provided as separate LSIs.

When the transmitting device 10 is an audio reproducing device such as a CD player or an MD player, the pre-stage circuit 12 decodes an encoded digital audio signal reproduced from a recording medium such as a CD or an MD. And so on.

FIG. 2 shows a specific example of the jitter reduction circuit 16. The digital audio signal Da (hereinafter, referred to as an input signal Da) subjected to biphase mark modulation from the digital audio output circuit 13 is shown in FIG. 5 when there is a jitter in the leading direction exceeding a predetermined range as shown by the rising Cu and the falling Cd.
In this case, both the case where there is a jitter in the delay direction exceeding the predetermined range as shown by the falling Cd is dealt with.

FIGS. 3 to 5 show three cases in which the clock CL, the input signal Da, and the like are shown in an overlapping manner for the sake of convenience.
FIG. 8 is similar.

In the jitter reducing circuit 16 in the example of FIG. 2, the jitter detecting circuit 30 uses the jitterless clocks CL and CLi from the clock generating circuit 17 to determine whether the input signal Da has a jitter exceeding a predetermined range. No, and if present, whether the direction is a leading direction or a lagging direction is detected. The clock CL is a clock having a frequency fa = 2fb = 256 fs as shown in FIG. 1, and the clock CLi is a clock inverted from the clock CL.

Specifically, in the jitter detection circuit 30, the input signal Da is supplied to the edge detection circuits 31 and 32,
The clock CL is supplied to the edge detection circuit 31, the clock CLi is supplied to the edge detection circuit 32, and the edge detection circuit 31 outputs the edge detection signal Ea as shown in FIG. 3 and FIG. 4 or FIG. 6 and FIG. Input signal Da
From the rising edge of the clock CL immediately after the rising edge and the falling edge of the clock CL for one cycle of the clock CL, and the edge detection signal Eb from the edge detection circuit 32 as shown in FIG.
Alternatively, as shown in FIG. 6, the falling edge of the clock CL immediately after the rising edge and the falling edge of the input signal Da (the rising edge of the clock CLi).
, A signal which is at a high level over one cycle of the clock CL is obtained.

Further, in the jitter detection circuit 30, the edge detection signal Ea from the edge detection circuit 31 is input to the enable terminal of the D flip-flop 33, and the edge detection signal Eb from the edge detection circuit 32 is converted to the D flip-flop 33. Of the clock generation circuit 1
7 is input to the clock terminal of the D flip-flop 33, and the D flip-flop 33 reads the value of the edge detection signal Eb at the rising edge of the clock CL when the edge detection signal Ea is at a high level. Can be

In the case shown in FIG. 3, when the rising edge and the falling edge of the input signal Da do not have a jitter exceeding a predetermined range as shown in the portion excluding the rising Cu and the falling Cd, these portions are not changed. , The edge detection signal Eb leads the edge detection signal Ea by a half cycle of the clock CL, and when the edge detection signal Ea is at a high level, the edge detection is performed at the rising edge of the clock CL. As a result of reading the low level of the signal Eb, the output signal FOB of the D flip-flop 33 becomes low.

On the other hand, the rising Cu and the falling Cd of the input signal Da are at their original positions (for the rising Cu, the rising edge e of the clock CL).
4, immediately after the falling Cd, immediately after the rising edge e8 of the clock CL, and beyond the rising edge of the immediately preceding clock CL (rising edge e4 for rising Cu, rising edge e8 for falling Cd). When advancing in time, as for the rising Cu and falling Cd portions, the edge detection signal Ea leads the edge detection signal Eb by a half cycle of the clock CL as shown by the portions Fu and Fd, and the edge detection signal When Ea is at a high level, the high level of the edge detection signal Eb is read at the rising edge of the clock CL. As a result, the output signal FOB of the D flip-flop 33 is at a high level. Becomes

On the other hand, in the case of FIG.
As shown in the portion excluding the rising Cu and the falling Cd at the rising edge and the falling edge of a, when there is no jitter exceeding a predetermined range, as shown in the portion excluding the portions Bu and Bd, , The edge detection signal Ea is the edge detection signal Eb
A half cycle of the clock CL leads to the edge detection signal E
When a is at a high level, the high level of the edge detection signal Eb is read at the rising edge of the clock CL,
The output signal FOB of the D flip-flop 33 goes high.

On the other hand, the rising Cu and the falling Cd of the input signal Da are at their original positions (for the rising Cu, the rising edge e of the clock CL corresponds to the rising edge e).
5, before the falling Cd, just before the rising edge e9 of the clock CL, and beyond the rising edge of the immediately following clock CL (rising edge e5 for rising Cu, rising edge e9 for falling Cd). When the time is delayed, the edge detection signal Eb leads the edge detection signal Ea by a half cycle of the clock CL, as shown by the portions Bu and Bd, with respect to the rising Cu and the falling Cd. When Ea is at a high level, the low level of the edge detection signal Eb is read at the rising edge of the clock CL. As a result, the output signal FOB of the D flip-flop 33 is at a low level, contrary to when no jitter exceeding a predetermined range exists. Becomes

Further, in the jitter detection circuit 30, the edge detection signal Ea from the edge detection circuit 31 is supplied to the delay circuit 3
4, the signal is delayed by one cycle of the clock CL,
From the edge detection signal Ea as shown in FIG. 3 or FIG.
d is obtained, and the clock CL from the clock generation circuit 17 is frequency-divided by the flip-flop 35, and the flip-flop 35 outputs a signal C which is inverted every rising edge of the clock CL as shown in FIG.
T is obtained. The frequency of the signal CT is the same as the above-described frequency of the biphase clock, that is, fb = 128 fs.

Further, in the jitter detection circuit 30, the delayed edge detection signal Ead from the delay circuit 34 is input to the enable terminal of the D flip-flop 36, and the signal CT from the flip-flop 35 is Input to the data terminal, the clock generation circuit 17
Is input to the clock terminal of the D flip-flop 36, and the value of the signal CT at the rising edge of the clock CL when the delayed edge detection signal Ead is at a high level is read by the D flip-flop 36. Can be

As a result, as shown in FIG. 3 or FIG. 6, the output signal DT of the D flip-flop 36 is
A signal holding the value of the signal CT when the immediately preceding delayed edge detection signal Ead is at a high level is obtained.

In the jitter detection circuit 30, the delayed edge detection signal Ead from the delay circuit 34, the output signal FOB of the D flip-flop 33, the output signal CT of the flip-flop 35, the output signal DT of the D flip-flop 36, And clock C from clock generation circuit 17
L is supplied to a decision circuit 37, which outputs a signal CT when the edge detection signal Ead is at a high level.
Is compared with the value of the signal DT to determine whether or not the input signal Da has a jitter exceeding a predetermined range. When it is determined that the jitter is present, whether or not the signal FOB is at a high level at that time is determined. Depending on whether it ’s low level,
It is determined whether the direction of the jitter is a leading direction or a lagging direction.

That is, when the value of the signal CT and the value of the signal DT are the same when the edge detection signal Ead is at the high level, the signal Ead when the previous signal Ead is at the high level and the signal E
The time interval from when ad is at a high level is an integer multiple of two cycles of the clock CL, and there is no jitter exceeding a predetermined range in the input signal Da. Conversely, if the value of the signal CT is different from the value of the signal DT when the edge detection signal Ead is at a high level, it means that the input signal Da has a jitter exceeding a predetermined range.
If OB is at a high level, the direction of the jitter is a leading direction, and if the signal FOB is at a low level, the direction of the jitter is a lagging direction.

In the case of FIG. 3, rising edges e3 and e of the clock CL when the signal Ead is at a high level.
5, e10, and e17 indicate that the value of the signal CT and the value of the signal DT are the same, and that no jitter is caused when the signal Ead before that is at a high level. On the other hand, rising edges e6 and e1 of clock CL
5, the value of the signal CT and the value of the signal DT are different,
This indicates that the signal Ead before that has a high level causes jitter. At this time, at the rising edge e6, the signal FOB is at a high level, indicating that the direction of the jitter is in the leading direction. At the rising edge e15, the signal FOB is at a low level, and the direction of the jitter is in the lagging direction. However, at the rising edge e15, since it is delayed by one cycle from the state advanced by one cycle of the clock CL, it returns to normal as a result.

On the other hand, in the case of FIG.
Rising edge e of clock CL when is high
3, e5, e12 and e17, the value of the signal CT and the signal D
This indicates that the value of T is the same, and no jitter is caused when the previous signal Ead is at a high level. On the other hand, the rising edge e of the clock CL
8, e15 indicate that the value of the signal CT and the value of the signal DT are different, and that the signal Ead before the signal has a higher level than when the signal Ead has a high level. At this time, at the rising edge e8, the signal FOB is at the low level, indicating that the direction of the jitter is in the lagging direction. At the rising edge e15, the signal FOB is at the high level, and the direction of the jitter is in the leading direction. However, at the rising edge e15, the state has been advanced by one cycle from the state delayed by one cycle of the clock CL, and as a result, the state has returned to normal.

As described above, in the jitter detection circuit 30,
Whether or not the input signal Da has a jitter exceeding a predetermined range, and if so, whether the direction is a leading direction or a lagging direction, is detected. The detection result as shown in the lower part is obtained.

That is, in the case of FIG.
Between the rising edge e6 and the rising edge e15 are detected as a period in which the jitter in the leading direction exceeds the predetermined range, and before the rising edge e6 and after the rising edge e15, as a period in which the jitter does not exceed the predetermined range. Is detected. In the case of FIG. 6, the rising edge e8 of the clock CL and the rising edge e1
5 is detected as a period in which the jitter in the delay direction exceeds the predetermined range, and before the rising edge e8 and after the rising edge e15, it is detected as a period in which the jitter does not exceed the predetermined range.

The jitter reducing circuit 16 in the example of FIG. 2 further detects the signal G for processing the input signal Da from the detection result.
B, GNd, GFdd, and Gor are generated.

More specifically, the edge detection signal Ead from the delay circuit 34 of the jitter detection circuit 30
1 delays one cycle of the clock CL,
From the edge detection circuit 3 as shown in FIG. 4 or FIG.
1 of the clock CL with respect to the edge detection signal Ea from
An edge detection signal Eadd delayed by the period is obtained, and the edge detection signal Eadd is supplied to the mask gate circuit 42,
The detection results from the determination circuit 37 of the jitter detection circuit 30 are supplied to the mask gate circuits 42, 43, and 44, respectively.

The mask gate circuit 44 is for a case where there is a jitter in the leading direction exceeding a predetermined range. As shown in FIGS. 3 and 4, the period during which the jitter detection result is “there is jitter in the leading direction”. Only in step (1), the input edge detection signal Eadd is passed as the output signal GF, and in other periods, the edge detection signal Eadd is masked.

The mask gate circuit 42 is for a case where there is jitter in the delay direction exceeding a predetermined range, and as shown in FIGS. 6 and 7, the period during which the jitter detection result is “there is jitter in the delay direction”. Only in step (1), the input edge detection signal Eadd is passed as the output signal GB, and in other periods, the edge detection signal Eadd is masked.

The mask gate circuit 43 is provided for the case where there is no jitter exceeding a predetermined range. As shown in FIG. 4 or FIG. 7, the edge detection of the input is performed only during the period when the jitter detection result is “normal”. The signal Eadd is passed as the output signal GN, and in other periods, that is, in a period in which the jitter detection result is “with jitter in the leading direction” or “with jitter in the lagging direction”, the edge detection signal Ead
This is to mask d.

The output signal GN of the mask gate circuit 43 is
4 and 5 or FIGS. 7 and 8
A signal GNd as shown in FIG. The output signal GF of the mask gate circuit 44 is delayed by two cycles of the clock CL by the delay circuits 46 and 47, and
A signal GFdd as shown in FIGS. 4 and 5 or FIGS. 7 and 8 is obtained.

Further, the output signal GFd of the delay circuit 47
d, the output signal GNd of the delay circuit 45, and the output signal GB of the mask gate circuit 42 are supplied to the OR gate 48, and are output from the OR gate 48 to FIG.
And a signal Gor as shown in FIG.

On the other hand, the input signal Da is delayed by the phase matching delay circuit 50 for a time corresponding to the time delay of the jitter detection described above. Specifically, the delay circuit 50 is constituted by three stages of delay circuits 51, 52, and 53 for respectively delaying the input signal by one cycle of the clock CL. The delay circuit 53 outputs a signal as shown in FIG. (Digital audio signal) DB is obtained.

The signal DB is to be selected when there is a jitter in the delay direction exceeding a predetermined range.
B is delayed by the delay circuit 61 by one cycle of the clock CL, and a signal DN as shown in FIG. 5 or FIG. The signal DN should be selected when there is no jitter exceeding a predetermined range.
Is delayed by one cycle of the clock CL in the delay circuit 62, and a signal DF as shown in FIG. 5 or FIG. 8 is obtained from the delay circuit 62. The signal DF is to be selected when there is a leading jitter exceeding a predetermined range.

Then, the signals DF, DN and DB are supplied to the selector 71, and the signals GFdd, GNd
And GB are supplied to the selector 71 as a selection signal.

In the selector 71, the signal DF is selected while the signal GFdd is at a high level, the signal DN is selected while the signal GNd is at a high level, and the signal DB is selected while the signal GB is at a high level. Therefore, signal DG as shown in FIG. 5 or FIG. 8 is obtained from selector 71.

The output signal Gor of the OR gate 48 is
Is input to the enable terminal of the D flip-flop 72, the output signal DG of the selector 71 is input to the data terminal of the D flip-flop 72, and the clock generation circuit 17
Is input to the clock terminal of the D flip-flop 72, and the D flip-flop 72 causes the signal at the rising edge of the clock CL when the signal Gor is at a high level as shown in FIG. D
The value of G is read.

Therefore, as the digital audio signal Dc output from the D flip-flop 72, a signal having no jitter as shown at the bottom of FIG. 5 or 8 is obtained.

That is, the digital audio output circuit 1 shown in FIG.
In the case where the digital audio signal Da from No. 3 has a jitter in the leading direction exceeding a predetermined range as shown by the rising Cu and the falling Cd in FIGS. Low level period is OK at the bottom
As shown by 1 and OK2, the jitter-free input digital audio signal in which the rising edge and the falling edge corresponding to the rising Cu and the falling Cd have been corrected to the correct positions is delayed by five periods of the clock CL. A signal is obtained.

Even when the digital audio signal Da from the digital audio output circuit 13 has a jitter in the delay direction exceeding a predetermined range as shown by rising Cu and falling Cd in FIGS. As the signal Dc, the low level periods OK1 and OK
As shown by 2, the rising Cu and the falling Cd
Is obtained, the rising edge and the falling edge corresponding to are corrected to the correct positions, and the input digital audio signal without jitter is delayed by five periods of the clock CL.

As described above, a jitter-free signal is obtained as the digital audio signal Dc output from the transmitting device 10 in FIG. Therefore, no jitter occurs in the clock reproduced by the clock reproducing PLL 22 of the receiving device 20 shown in FIG.
The analog audio signal output from the DAC 24 after the A conversion is not distorted, and the audio output from a speaker or the like connected to the output terminals 27 and 28 is not distorted.

[Other Embodiments] In the example of FIG. 2, the input digital audio signal Da has both a jitter in a leading direction exceeding a predetermined range and a jitter in a lagging direction exceeding a predetermined range. As a countermeasure, if there is only a known jitter in one of the directions, it is not necessary to detect the direction of the jitter and to cope with the jitter in the other direction.

The above-described example is based on the format shown in FIG. 9 and FIG. 10 of the IEC958 standard.
As shown in FIG. 1, the case where the jitter of the digital audio signal subjected to the bi-phase mark modulation is reduced, the present invention is not limited to the signal of such a format, and is not limited to the signal of the bi-phase mark modulation. The present invention is not limited to audio signals, and can be applied to a case where jitter of a digital signal is reduced to reproduce a clock from the digital signal.

[0069]

As described above, according to the present invention, when a digital signal has a jitter exceeding a predetermined range,
The jitter can be reduced to a predetermined range, and when the digital signal is a self-synchronous digital audio signal output from the transmitting device, the transmitting device outputs the digital audio signal with the jitter reduced. By
A clock with less jitter can be reproduced in the receiving device, and audio with less distortion can be output.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a transmission device equipped with a jitter reduction device of the present invention.

FIG. 2 is a diagram illustrating a specific example of a jitter reduction circuit.

FIG. 3 is a diagram illustrating an example of a signal obtained in each unit of the jitter reduction circuit in FIG. 2;

FIG. 4 is a diagram illustrating an example of a signal obtained in each unit of the jitter reduction circuit in FIG. 2;

FIG. 5 is a diagram illustrating an example of a signal obtained in each unit of the jitter reduction circuit in FIG. 2;

FIG. 6 is a diagram illustrating an example of a signal obtained in each unit of the jitter reduction circuit in FIG. 2;

FIG. 7 is a diagram illustrating an example of a signal obtained in each unit of the jitter reduction circuit in FIG. 2;

FIG. 8 is a diagram illustrating an example of a signal obtained in each unit of the jitter reduction circuit in FIG. 2;

FIG. 9 is a diagram showing a format of a digital audio interface.

FIG. 10 is a diagram showing a subframe configuration of the format of FIG. 9;

FIG. 11 is a diagram illustrating biphase mark modulation.

FIG. 12 is a diagram illustrating an example of a conventional transmission device.

FIG. 13 is a diagram illustrating an example of a receiving device.

14 is a diagram showing that jitter occurs in the output of the transmission device of FIG. 12;

FIG. 15 illustrates a possible example of a transmitting device.

16 is a diagram illustrating that jitter cannot be reduced by the transmission device of FIG. 15;

[Explanation of symbols]

Since the main parts are all described in the figure, they are omitted here.

Claims (10)

[Claims] And detecting whether or not the input digital signal has a jitter exceeding a predetermined range by using a clock synchronized with the input digital signal. Processing digital signals,
A jitter reduction method for generating an output digital signal. 2. The jitter reduction method according to claim 1, wherein the jitter detection is performed to detect whether or not the input digital signal has a jitter in a predetermined direction exceeding a predetermined range. According to the detection result, the signal is generated by converting one of a digital signal having a time relationship defined with respect to the input digital signal and a digital signal delayed or advanced with respect to the input digital signal. The jitter reduction method to be selected. 3. The jitter reduction method according to claim 1, wherein the jitter detection is performed to determine whether or not the input digital signal has a jitter exceeding a predetermined range, and if so, the direction of the jitter is advanced or delayed. The output digital signal is generated in accordance with a detection result of the first digital signal having a time relationship defined with respect to the input digital signal. And a third digital signal that is temporally advanced with respect to the first digital signal and a second digital signal that is temporally delayed with respect to the first digital signal. 4. The jitter reduction method according to claim 3, wherein a rising edge or a falling edge of the input digital signal is detected by a rising edge and a falling edge of the clock, respectively, and a phase relationship between the two edge detection signals is detected. Jitter reduction method for determining the direction of jitter from 5. A jitter detecting means for detecting whether or not a jitter exceeding a predetermined range exists in the input digital signal using a clock synchronized with the input digital signal, and detecting the clock in accordance with a result of the detection. And a digital signal processing means for processing the input digital signal to generate an output digital signal. 6. The jitter reducing apparatus according to claim 5, wherein the jitter detecting means detects whether or not the input digital signal has a jitter in a predetermined direction exceeding a predetermined range. The signal processing means, according to the detection result of the jitter detection means, a digital signal having a time relationship determined with respect to the input digital signal, and a digital signal delayed or advanced with respect to the digital signal. , A jitter reducing apparatus for selecting one of the above. 7. The jitter reducing apparatus according to claim 5, wherein the jitter detecting means determines whether or not the input digital signal has a jitter exceeding a predetermined range, and if so, determines whether the direction is a forward direction. The digital signal processing means detects a first digital signal having a time relationship with respect to the input digital signal in accordance with a detection result of the jitter detection means; A jitter reducing apparatus for selecting one of a second digital signal temporally delayed with respect to one digital signal and a third digital signal temporally advanced with respect to the first digital signal . 8. The jitter reducing apparatus according to claim 7, wherein the jitter detecting means detects a rising edge or a falling edge of the input digital signal based on a rising edge of the clock, and detects a rising edge or a falling edge of the input digital signal based on a falling edge of the clock. A jitter reducing apparatus comprising: means for detecting a rising edge or a falling edge of the input digital signal; and means for judging the direction of jitter based on the detection results of both the detecting means. 9. A transmission device which is equipped with the jitter reduction device according to claim 5 and outputs said output digital signal. 10. An audio reproducing apparatus comprising the jitter reducing apparatus according to claim 5, wherein said input digital signal is a digital audio signal reproduced from a recording medium.