JP2002100971A - Drive method for double-gate igbt - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive method for a double-gate IGBT, which can be always driven by an optimum turn-off characteristic by a method, where the discharge state of carriers stored inside an element is indirectly observed by the drain-to-source voltage of the element, and a main gate G1 is turned off immediately after the carriers stored inside the element have been discharged. SOLUTION: A zero is input to an input terminal IN. A pulse width from a second delayed-pulse generation circuit 600 is set at several μsec so as to be input to the gate of a level shifter MOS 300. A positive voltage is applied to the auxiliary gate G2 of the double-gate IGBT 100, and the drain-to-source voltage of the IGBT 100 rises. When the voltage exceeds the set value of a voltage decision circuit 900, pulses are output to be input to the reset terminal of a first latching circuit 700. Thereby, the main gate G1 is turned off, and the IGBT 100 is turned off. The timing, at which the main gate G1 is turned off is decided by the voltage of the element, the discharge state of the carriers inside the element is observed indirectly, and the main gate G1 is turned off always immediately after the carriers stored inside the element have been discharged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a double gate IG.
The present invention relates to a method for driving a BT.

[0002]

2. Description of the Related Art FIG. 3 shows a general structure of a conventional IGBT. Here, an example of a horizontal IGBT formed on a dielectric isolation substrate in which an oxide film SIO ₂ is embedded in a semiconductor substrate is shown. 8 is a p-type drain diffusion layer, 7 is an n-type buffer layer, 1
Is a high-resistance n-type base diffusion layer. A p-type base diffusion layer 2 is selectively formed on the surface of the n-type base diffusion layer 1 by diffusion. The layer 3 is formed by diffusion. n of the p-type base diffusion layer 2
The surface of the region sandwiched between the type source diffusion layer 3 and the n-type base diffusion layer 1 is defined as a channel region CH1, where a gate electrode 6 is formed via a gate insulating film 5. A source electrode 4 is formed so as to make ohmic contact with the n-type source diffusion layer 3 and the p-type base diffusion layer 2 at the same time, and a drain electrode 10 is formed on the p-type drain diffusion layer 8.

In this IGBT, when the gate electrode 6 is positively biased with respect to the source electrode 4, the channel region CH
1 is inverted and electrons are injected from the n-type source diffusion layer 3 into the n-type base diffusion layer 1. When this electron current enters the p-type drain diffusion layer 8 via the n-type buffer layer 7, the pn junction is forward-biased and holes are generated from the p-type drain diffusion layer 8 through the n-type buffer layer 7. Is injected into the mold base diffusion layer 1. In this way, both electrons and holes are accumulated in the n-type base diffusion layer 1, and conductivity modulation occurs. Therefore, in order to obtain a high breakdown voltage, even when the n-type base diffusion layer 1 has a high resistance,
At the time of ON, the resistance of the n-type base diffusion layer 1 becomes substantially small, so that a small ON voltage is obtained. This IGBT
Is turned off by biasing the gate electrode 6 to zero or negative with respect to the source electrode 4 to eliminate the inversion layer in the channel region CH1.

In such a conventional IGBT, in order to increase the turn-off switching speed, it is necessary to quickly eliminate carriers accumulated in the n-type base diffusion layer 1. If carriers accumulated in the n-type base diffusion layer 1 do not escape quickly, a pnp transistor composed of the p-type drain diffusion layer 8, the n-type buffer layer 7, the n-type base diffusion layer 1, and the p-type base diffusion layer 2 operates. Large tail current flows. Therefore, in order to increase the turn-off switching speed, the p-type drain diffusion layer 8 needs to
It is necessary to limit the amount of holes to be injected into the mold base diffusion layer 1, and it is necessary to set the impurity dose when forming the p-type drain diffusion layer 8 separately from other diffusion layers. However, if the impurity dose is set separately, there is a problem that the number of manufacturing steps of the element increases and the cost increases.

[0005] For this reason, a double-gate IGBT shown in FIG. 4 has been proposed. The same reference numerals are used for the same portions of the double gate IGBT shown here and the IGBT shown in FIG.

This double gate IGBT has a high resistance n
A p-type base diffusion layer 2 selectively formed on the surface of the p-type base diffusion layer 1, a first n-type source diffusion layer 3 selectively formed on the surface of the p-type base diffusion layer 2, An n-type buffer layer 7 selectively formed on the surface of the n-type base diffusion layer 1 on the same side as the p-type base diffusion layer 2, and a p-type buffer layer selectively formed on the surface of the n-type buffer layer 7. A drain diffusion layer 8, a second n-type source diffusion layer 9 selectively formed on the surface of the p-type drain diffusion layer 8, the p-type base diffusion layer 2, and the first n-type source diffusion layer 3, a drain electrode 10 that contacts the p-type drain diffusion layer 8 and the second n-type source diffusion layer 9, and a first n-type source diffusion layer 3. In the region between the n-type base diffusion layer 1 and the p A main gate electrode 6 formed on a surface of a base diffusion layer 2 via a gate insulating film 5; and a p-type region in a region sandwiched between the n-type buffer layer 7 and the second n-type source diffusion layer 9. An auxiliary gate electrode 12 is formed on the surface of the drain diffusion layer 8 via a gate insulating film 11.

FIG. 5 is an equivalent circuit diagram of the double gate IGBT of FIG. 4, and FIG. 6 is a symbolized version. When this element is turned off, the main gate G1
Is set to zero or a negative bias with respect to the source S to turn off the first channel region CH1. At the same time, the auxiliary gate G
2 is biased positively with respect to the drain D to turn on the second channel region CH2.

With such a bias, electron injection from the first n-type source diffusion layer 3 to the n-type base diffusion layer 1 is eliminated. Then, on the drain D side, the second n-type source diffusion layer 9 conducts with the n-type buffer layer 7 via the second channel region CH2, so that the drain electrode 10 and the n-type buffer layer 7 are short-circuited. In other words, at turn-off,
The pnp transistor has a current gain of zero. In this state, the electrons accumulated in the device pass through the n-type buffer layer 7 -the second channel region CH2 -the second n-type source diffusion layer 9 to the drain electrode 10, and the holes are the p-type base diffusion layer 2 Through to the source electrode 4. This state is equivalent to the fact that the p-type base diffusion layer 2 and the n-type base diffusion layer 1 are effectively reverse-biased.

As described above, in this device, the tail current can be reduced and the turn-off speed can be increased by short-circuiting the n-type buffer layer 7 and the drain electrode 10 only at the time of turn-off. Further, the p-type drain diffusion layer 8 can be formed with a high impurity dose, and the same steps as those for the other diffusion layers can be used, so that an inexpensive element can be provided.

As described above, the turn-off time when the main gate G1 is turned off and the auxiliary gate G2 is turned on at the same time is almost the same as the time for discharging the carriers accumulated in the n-type base diffusion layer 1. However, when the auxiliary gate G2 is turned on before the main gate G1 is turned off, a faster turn-off operation is realized. Ideally, n-type base diffusion layer 1
It is desirable to turn off the main gate G1 immediately after the carriers accumulated in the main gate are discharged.

[0011]

As described above, in the double-gate IGBT, the point at which the main gate G1 is turned off is important for obtaining an optimum turn-off characteristic, but the carrier accumulated in the n-type base diffusion layer 1 is important. The amount depends on the value of the current flowing through the element, and the time from turning on the auxiliary gate G2 to the discharge of carriers differs depending on the value of the flowing current. If the time when the main gate G1 is turned off is too late, the turn-off loss increases. Conventionally, the main gate G1
In the method of setting the time to turn off by the time from the time when the auxiliary gate G2 is turned on, it is not possible to obtain an optimum turn-off characteristic.

An object of the present invention is to provide a method of driving a double gate IGBT which has solved the above-mentioned problem.

[0013]

A method of driving a double gate IGBT according to the present invention comprises a low-concentration semiconductor layer, a first conductivity type base diffusion layer selectively formed on a surface of the semiconductor layer, A second conductivity type source diffusion layer selectively formed on the surface of the one conductivity type base diffusion layer, and a second conductivity type source diffusion layer selectively formed on the surface of the semiconductor layer on the same side as the first conductivity type base diffusion layer. A conductivity type buffer layer; a first conductivity type drain diffusion layer selectively formed on the surface of the second conductivity type buffer layer; and a first conductivity type drain diffusion layer selectively formed on the surface of the first conductivity type drain diffusion layer. And a low-concentration second conductive layer formed on the surface of the semiconductor layer in a region between the first conductive type base diffusion layer and the second conductive type buffer layer. Diffusion layer, the first conductivity type base diffusion layer and the first A source electrode that contacts over the conductive type source diffusion layer, a drain electrode that contacts over the first conductive type drain diffusion layer and the first second conductive type diffusion layer, and the second conductive type source diffusion layer A main gate electrode formed on the surface of the first conductivity type base diffusion layer via a gate insulating film in a region sandwiched between the second conductivity type diffusion layer and the second conductivity type buffer layer; Driving of a double gate IGBT comprising: an auxiliary gate electrode formed on a surface of the drain diffusion layer of the first conductivity type via a gate insulating film in a region interposed between the diffusion layer of the first conductivity type and a first diffusion layer of the second conductivity type In the circuit, the double gate I
The drive circuit of the GBT includes a circuit for observing a voltage between the drain and the source of the double gate IGBT, a circuit for providing an ON / OFF signal to the main gate electrode, and an ON / OFF signal to the auxiliary gate electrode. When turning off the double gate IGBT, the auxiliary gate electrode is turned off first, and then the drain-source voltage of the IGBT is observed by a circuit for observing the drain-source voltage. The main gate electrode is turned off when this voltage exceeds a predetermined voltage.

Further, the power supply of the auxiliary gate circuit of the drive circuit is characterized by using the charge of a capacitor charged through the double gate IGBT when the double gate IGBT is turned on.

According to the present invention, the discharge state of the carriers accumulated in the n-type base diffusion layer can be indirectly observed by the drain voltage of the element, and the main gate is always kept immediately after the carriers accumulated in the n-type base diffusion layer are exhausted. G1 can be turned off, and driving can be performed with optimal turn-off characteristics.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a driving circuit according to an embodiment of the present invention. A double gate IGBT 100 has a source terminal S grounded and a drain terminal D connected to a main power supply E _M via a load L.
It is used under the condition of receiving the voltage. This double gate I
A control signal is applied to the main gate G1 and the auxiliary gate G2 of the GBT 100 using the source terminal S and the drain terminal D as reference potential points, respectively. For this purpose, the power supply Eg1 of the main gate G1 is provided on the ground side, and the power supply of the auxiliary gate G2 is provided on the high voltage side. The power supply circuit of the auxiliary gate G2 includes a diode Db connected to the high potential side of the power supply Eg1 of the main gate G1, and a capacitor Cb connected between the cathode of the diode Db and the drain of the double gate IGBT100. Double gate IGBT100
Is turned on, the diode Db, the capacitor Cb, the double gate IGBT 100
, A charging current of the capacitor Cb flows, and the capacitor Cb is charged with a charge having substantially the same voltage as the power supply Eg1 of the main gate G1. In addition, to the double-gate IGBT 100, an element 200 constituting a circuit for observing a drain-source voltage of the double-gate IGBT 100 and a resistor R are connected in parallel. Specifically, Japanese Patent Laid-Open No. 9-148
Means shown at 579 are used. Further, the driving circuit includes a level shifter MOS 300, a first delay pulse generation circuit (DP1) 500, a second delay pulse generation circuit (DP2) 600, and a first latch circuit (LC1).
700, a second latch circuit (LC2) 800, a voltage determination circuit (CMP) 900, and an auxiliary gate circuit 400.

Next, the operation of the driving circuit will be described with reference to a timing chart shown in FIG. First, as shown in FIG. 2A, a control signal is supplied to an input terminal IN of the drive circuit.
To enter. Then, the first delay pulse generation circuit 500
2 outputs a pulse having a width W1 as shown in FIG. Here, the width W1 of this pulse is
It is set slightly longer than the turn-on time of the GBT 100. Further, the pulse of the first delay pulse generation circuit 500 is supplied to the first latch circuit 700 and the second latch circuit 80.
0 to the first latch circuit 70
At 0, the output is set at the rising edge of the pulse, and in the second latch circuit 800, the output is set at the falling edge of the pulse. Therefore, when a signal enters the input terminal IN of the drive circuit, the double gate IGBT 10
A positive voltage is applied to the 0 main gate G1, and the double gate IGBT 100 is turned on. Here, the above W1
During the period, no voltage is applied to the gate of the element 200 of the voltage observation circuit, and the voltage of the double gate IGBT 100 is not observed. This is because the voltage in the turn-on transient state is not detected.

Next, when the signal input to the input terminal IN of the drive circuit is set to zero, a pulse having a width W2 as shown in FIG. 2C is output from the second delay pulse generation circuit 600. The width W2 of this pulse is set to several μsec, and the gate of the level shifter MOS 300 and the second latch circuit 8
00 is input to the reset terminal. As a result, the level shift MOS 300 operates and the auxiliary gate circuit 400
, A positive voltage is applied to the auxiliary gate G2 of the double-gate IGBT 100, and the second n-type source diffusion layer 9 conducts with the n-type buffer layer 7 via the second channel region CH2. The electrons that are short-circuited with the buffer layer 7 and accumulated in the device are transferred to the n-type buffer layer 7-
The channel region CH2 passes through the second n-type source diffusion layer 9 to the drain electrode 10, and holes are removed from the p-type base diffusion layer 2.
Through to the source electrode 4. Then, the voltage between the drain and the source of double-gate IGBT 100 rises, and when this voltage exceeds the set value of voltage determination circuit 900, FIG.
As shown in (g), a pulse is output from the voltage determination circuit 900 and input to the reset terminal of the first latch circuit 700. As a result, as shown in FIG. 2D, the signal of the main gate G1 of the double-gate IGBT 100 is turned off, the first channel region CH1 is turned off, and the first n-type source diffusion layer 3 to the n-type base diffusion layer The injection of electrons into 1 stops, and the double-gate IGBT 100 turns off.

As described above, in the driving method according to the present invention, the timing for turning off the main gate G1 is determined by the voltage of the element, and the state of discharging carriers inside the element is indirectly observed.
The main gate G1 is always turned off immediately after the carriers accumulated inside the element are discharged.

In the above embodiment, one double gate I
Although the driving method in the GBT has been described, the present invention is not limited to the above embodiment. For example, the present invention can be applied to an inverter device using a plurality of double-gate IGBTs. In addition, a double gate IGBT is replaced with a double gate GT.
O, double gate EST, and double gate SIT can be used. Further, the structure of the present invention can be integrated on the same substrate.

[0022]

As described above, according to the present invention, the discharge state of the carriers accumulated inside the device is determined by the drain and drain of the device.
The main gate G1 is turned off immediately after the carriers accumulated inside the element are discharged, as observed indirectly with the source-to-source voltage, so that the drive can always be performed with the optimal turn-off characteristics. As a result, a high-speed and low-loss device can be provided.

[Brief description of the drawings]

FIG. 1 shows a driving circuit of the present invention.

FIG. 2 is a timing chart of a driving circuit of the present invention.

FIG. 3 is a cross-sectional view of a conventional IGBT.

FIG. 4 is a sectional view of a conventional double gate IGBT.

FIG. 5 is an equivalent circuit of a double gate IGBT.

FIG. 6 is a symbol diagram of a double gate IGBT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... n-type base diffusion layer 2 ... p-type base diffusion layer 3 ... 1st n-type source diffusion layer 4 ... source electrode 5 ... gate insulating film 6 ... main gate electrode 7 ... n-type buffer layer 8 ... p-type drain diffusion Layer 9 Second n-type source diffusion layer 10 Drain electrode 11 Gate insulating film 12 Auxiliary gate electrode 100 Double gate IGBT 200 Voltage detection element 300 Level shifter MOS 400 Auxiliary gate circuit 500 First delay Pulse generating circuit 600: second delayed pulse generating circuit 700: first latch circuit 800: second latch circuit 900: voltage determining circuit

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H03K 17/56 Z

Claims (2)

[Claims] 1. A low-concentration semiconductor layer, a first conductivity type base diffusion layer selectively formed on a surface of the semiconductor layer, and a first conductivity type base diffusion layer selectively formed on a surface of the first conductivity type base diffusion layer. A second conductivity type source diffusion layer, a second conductivity type buffer layer selectively formed on the surface of the semiconductor layer on the same side as the first conductivity type base diffusion layer, and a surface of the second conductivity type buffer layer A first conductivity type drain diffusion layer selectively formed on the first conductivity type drain diffusion layer; a first second conductivity type diffusion layer selectively formed on the surface of the first conductivity type drain diffusion layer; A low-concentration second second-conductivity-type diffusion layer formed on a surface of the semiconductor layer in a region sandwiched between the diffusion layer and the second-conductivity-type buffer layer; A source electrode contacting over the second conductivity type source diffusion layer; A drain electrode in contact with the first conductivity type drain diffusion layer and the first second conductivity type diffusion layer, and sandwiched between the second conductivity type source diffusion layer and the second second conductivity type diffusion layer; A main gate electrode formed on the surface of the base diffusion layer of the first conductivity type in the separated region via a gate insulating film; and the buffer layer of the second conductivity type and the first diffusion layer of the second conductivity type. A driving circuit for a double-gate IGBT, comprising: an auxiliary gate electrode formed on a surface of the first-conductivity-type drain diffusion layer in a separated region via a gate insulating film; A circuit for observing a voltage between the drain and the source of the double gate IGBT, a circuit for providing an on / off signal to the main gate electrode, and a circuit for providing an on / off signal to the auxiliary gate electrode. When the double-gate IGBT is turned off, the auxiliary gate electrode is first turned off, and then the voltage between the drain and source of the IGBT is observed by a circuit for observing the voltage between the drain and source. And turning off the main gate electrode when the voltage exceeds a predetermined voltage. 2. A power supply for an auxiliary gate circuit of the driving circuit,
2. The double gate I according to claim 1, wherein when the double gate IGBT is turned on, a charge of a capacitor charged through the double gate IGBT is used.
GBT driving method.