JP2002100966A - Adjusting device and testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an adjusting device, in which the delay time for the rise time of an input signal and the delay time for the fall time of the input signal are adjusted. SOLUTION: The adjusting device 152 is provided with a first delay circuit 166, in which the rise time of the input signal is delayed more than the fall time of the input signal, a second delay circuit 168 in which the fall time of the input signal is delayed more than the rise time of the input signal and a selection part 176 which selects the first delay circuit or the second delay circuit and in which the input signal adjusted by the selected delay circuit is output as an adjusting signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an adjusting device and a test device. In particular, the present invention relates to an adjustment device and a test device that adjust a delay time of a rise time and a delay time of a fall time of an input signal.

[0002]

2. Description of the Related Art As a test apparatus for testing electrical characteristics of an electronic device, a comparator for inputting an input pattern signal to the electronic device, receiving an output pattern signal output from the electronic device based on the input pattern signal, and comparing timings. Are used. The electronic device has a plurality of input pins and output pins, an input pattern signal is input to each input pin, and each output pattern signal is output from each output pin. The comparator has a plurality of comparison circuits, and the output pattern signal output from each output pin is input to each comparison circuit.

[0003]

However, since each comparison circuit has its own characteristic, the delay time generated between the rise time and the fall time of the input output pattern signal varies with the speed of the electronic device. However, there is a problem that skew occurs. Therefore, such a skew has been required to be improved in a test device such as a comparator.

Accordingly, an object of the present invention is to provide an adjusting device and a test device which can solve the above-mentioned problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.

[0005]

According to a first aspect of the present invention, a first delay circuit for delaying the rise time of an input signal longer than the fall time of an input signal, and the fall time of an input signal Delay circuit that delays the input signal more than the rise time of the input signal, and one of the first delay circuit and the second delay circuit, and the input signal adjusted by the selected delay circuit is output as an adjustment signal. And a selecting unit that performs the adjustment.

[0006] The input signal may be adjusted by passing through a delay circuit selected by the selection unit. The adjustment device furthermore
A buffer for shaping the waveform of a predetermined signal and outputting an input signal may be provided.

[0007] The selector may select either the first delay circuit or the second delay circuit so that the pulse width of the adjustment signal is equal to the pulse width of the predetermined signal. The adjustment device may further include a storage unit that stores which of the delay circuits is selected by the selection unit.

The adjustment device further includes a detection timing signal output unit for outputting a detection timing signal for detecting a timing at which the adjustment signal changes, and detects and detects the adjustment signal based on the timing at which the detection timing signal changes. A detection signal output unit that outputs the signal as a signal.

The adjusting device further includes a first delay circuit and a second delay circuit.
A delay circuit, a selection unit, a detection timing signal output unit,
A plurality of adjustment units each including a detection signal output unit, and a detection timing generation unit that instructs a detection timing may be provided, and an input signal is input to each of the plurality of adjustment units, and the detection timing signal output unit Alternatively, when the detection timing generator gives the same timing to each adjustment unit, each detection signal output unit may output a detection timing signal so that the adjustment signal is detected at the same timing.

According to a second aspect of the present invention, there is provided a test apparatus for testing an electronic device, a pattern generator for generating an input pattern signal to be input to the electronic device, and a waveform of the input pattern signal. A waveform shaping unit;
A signal input / output unit that electrically contacts the electronic device and supplies an input pattern signal shaped by the waveform shaping unit to the electronic device and receives an output pattern signal output by the electronic device based on the input pattern signal; and a reference clock signal. A timing generator for delaying a desired time to generate a timing signal of a desired frequency, and a detector for inputting and detecting an output pattern signal output by the electronic device,
A first delay circuit that delays the rise time of the input signal longer than the fall time of the input signal; a second delay circuit that delays the fall time of the input signal more than the rise time of the input signal; First delay circuit and second delay circuit
A selector for selecting one of the delay circuits and outputting an input signal adjusted by the selected delay circuit as an adjustment signal.

The above summary of the invention does not enumerate all of the necessary features of the present invention, and a sub-combination of these features can also be an invention.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the claimed invention and have the features described in the embodiments. Not all combinations are essential to the solution of the invention.

FIG. 1 is a block diagram showing the entire configuration of the test apparatus 100. The test apparatus 100 includes a pattern generator 110, a timing generator 120, and a waveform shaping unit 13.
0, a signal input / output unit 140, and a detection unit 150. The test apparatus 100 tests the electrical characteristics of the electronic device 200.

Here, "electronic device" refers to a component that performs a predetermined action according to current or voltage.
C (Integrated Circuit) and LSI (Large-Scale Int)
eg, a semiconductor component comprising an active element such as an rated circuit. Further, it includes a component in which these components are combined and stored in one package, and a component such as a breadboard in which these components are mounted on a printed circuit board to realize a predetermined function.

The pattern generator 110 includes an input pattern signal 112 to be input to the electronic device 200 to be tested, an expected value pattern signal 114 to be output from the electronic device 200 when the input pattern signal 112 is input, and Is generated according to a predetermined control sequence.

The timing generator 120 generates a timing signal of a desired frequency by delaying a reference clock signal received from a reference clock generator (not shown) by a desired time. The timing generation unit 120 includes the electronic device 200
A timing signal 122 for controlling the input timing of the input pattern signal 112 to the input terminal is generated at various timings based on the reference clock signal.

The waveform shaping section 130 receives the input pattern signal 1
Twelve waveforms are shaped based on the timing signal 122 so as to conform to the characteristics of the electronic device 200, and the input of the input pattern signal 112 to the electronic device 200 is controlled based on the timing signal 122.

The signal input / output unit 140 includes the electronic device 20
0 is electrically contacted, and receives the input pattern signal shaped by the waveform shaping unit 120 and supplies it to the input pin of the electronic device 200. The signal input / output unit 140 receives and outputs the output pattern signal 142 output from the output pin by the electronic device 200 based on the input pattern signal.

The detection unit 150 outputs the output pattern signal 142
And the expected value pattern signal 114. Detector 15
0 is the output pattern signal 142 and the expected value pattern signal 1
14 is logically compared based on the timing signal 124 output from the timing generation unit 120, and it is detected whether or not they match. The detection unit 150 has an adjustment device 152. The adjusting device 152 includes a first delay circuit that delays the rise time of the input signal longer than the fall time of the input signal, and a second delay circuit that delays the fall time of the input signal more than the rise time of the input signal. And a selector for selecting one of the first delay circuit and the second delay circuit and outputting an input signal adjusted by the selected delay circuit as an adjustment signal. Each unit of the test apparatus 100 is controlled by the control device 210.

FIG. 2 shows a detecting unit 150 according to this embodiment.
FIG. 3 is a block diagram illustrating a configuration of an adjustment device 152 included in the first embodiment. The adjustment device 152 includes a plurality of comparison circuit units (152-102) corresponding to a plurality of output pins of the electronic device 200, respectively.
1 to 152-n) and a detection timing generator 190. Each of the comparison circuit units (152-1 to 152-n)
Each has a level comparison circuit 154 and a timing comparison circuit 156. Each comparison circuit section (152-1 to 152)
−n) has the same configuration, and therefore, the configuration of the comparison circuit unit 152-1 will be described below.

The timing comparison circuit 156 includes a buffer 1
58 and an adjusting unit 160. The buffer 158 shapes the waveform of a predetermined signal and outputs the input signal SIG11. The predetermined signal in this embodiment is an output pattern signal 1 output from each output pin of the electronic device 200.
42-1.

The adjusting unit 160 includes a pulse width adjusting unit 162
And a detection signal output unit 180 and a detection timing signal output unit 182. The pulse width adjustment unit 162 has a circuit unit 164 and a selection unit 176. The circuit unit 164 includes
A first delay circuit 166 that delays the rise time of the input signal longer than the fall time of the input signal, and a second delay circuit 168 that delays the fall time of the input signal more than the rise time of the input signal. Have.
The pulse width adjustment unit 162 further includes a through path 170 for passing the input signal output from the buffer 158 as the adjustment signal SIG21, a first path 172 for passing the adjustment signal SIG22 that has passed through the first delay circuit 166, and a second path 172. A second path 174 for passing the adjustment signal SIG23 that has passed through the delay circuit 168.

The selection unit 176 selects one of the through path 170, the first path 172, and the second path 174, and adjusts the input by passing through the selected path (170, 172, 174). Adjustment signal SI that is signal SIG11
G21, SIG22 or SIG23 is output. The selection unit 176 receives the adjustment signal SIG21, SIG22 or SIG
23 and the first path 172 so that the pulse width of the output pattern signal 142-1 which is a predetermined signal input to the buffer 158 is equal to the pulse width of the output pattern signal 142-1.
And the second path 174 are selected.

The selecting section 176 preferably has a storage section 178 for storing which route is selected. It is preferable that the storage unit 178 stores the path selected when the pulse width adjustment unit 162 is calibrated. In the present embodiment, the storage unit 178 is a register,
0, the selected route (170,
172, 174) are stored. Then, the selection unit 176
The stored path (170, 172, 174) is selected, and the adjustment signals SIG21, SI passing through the selected path are selected.
G22 or SIG23 is output as the adjustment signal SIG31. The selection unit 176 includes the storage unit 178, and selects the path based on the information stored in the storage unit 178.
Does not need to be calibrated to detect the path to be selected by the selection unit 176.

In another embodiment, circuit portion 164 includes
A plurality of paths each having a delay circuit having a different delay amount may be provided, and the selection unit 176 may select any one of the plurality of paths and adjust the waveform of the input signal SIG11. The delay circuit having the different delay amount delays one of the rise time and the fall time of the waveform of the input signal more than the other and has a different pulse width from the output waveform. Is preferred. Specifically, for example, paths having different delay amounts may be provided by combining a plurality of delay circuits that delay the rise time of the waveform of the input signal SIG11 by a predetermined time. In addition, for example, paths having different delay amounts may be provided by combining a plurality of delay circuits that delay the fall time of the waveform of the input signal SIG11 by a predetermined time. Thus, by combining various delay amounts that delay the rise time or fall time of the waveform of the input signal, the pulse width of the output signal can be adjusted.

The detection timing generation section 190 generates a detection timing signal, and outputs a signal to each of the comparison circuit sections (152-1 to 152).
The timing at which the detection signal output section 180 outputs the detection signal SIG41 is given to the detection timing signal output section 182 of -n). Further, the timing generator 120 included in the test apparatus 100 may generate the detection timing signal.

The detection timing signal output section 182 outputs a detection timing signal STRB for detecting a timing at which the adjustment signal SIG31 changes. The detection timing signal output unit 182 in the present embodiment is a variable delay circuit. The detection timing signal output unit 182 is configured such that the detection timing generation unit 190 makes each of the comparison circuit units (152-1 to 152-1).
52-n), when the same timing is given to the detection timing signal output unit 182, each detection signal output unit 180 outputs the detection timing signal STRB so that the adjustment signal SIG31 is detected at the same timing.

The detection signal output section 180 receives the adjustment signal SIG31 and the detection timing signal STRB output from the selection section 176. The detection signal output unit 180 according to the present embodiment is a latch circuit. Detection signal output section 180
Detects the adjustment signal SIG31 based on the timing at which the detection timing signal STRB changes, and
Output as IG41.

FIG. 3 shows a comparison circuit section 1 according to this embodiment.
It is a timing chart which shows the waveform of the signal adjusted in 52-1. FIG. 3A shows an electronic device 200.
5 shows a waveform of an output pattern signal 142-1 output from the LM. FIG. 3B shows the output pattern signal 14 shown in FIG.
2 shows a waveform of a pulse wave schematically showing 2-1.

FIGS. 3C to 3E are pulse waves showing the input signal SIG11 after the output pattern signal 142-1 has passed through the level comparison circuit 154 and the buffer 158. FIG. 3C shows the input signal SIG11- (1) when the delay time t1 of the rise time and the delay time t2 of the fall time generated through the level comparison circuit 154 and the buffer 158 are equal. Since the output pattern signal 142-1 passes through the level comparison circuit 154 and the buffer 158, the output pattern signal 142-1
Is delayed by the time required to pass through the level comparison circuit 154 and the buffer 158.

Here, the delay time t1 of the rise time is the time between the timing when the input signal changes from L logic to H logic and the timing when the output signal changes from L logic to H logic. Say. The timing is
The timing may be a timing at which the signal is recognized as H logic. Further, the delay time t2 of the fall time refers to the time between the timing when the input signal changes from H logic to L logic and the timing when the output signal changes from H logic to L logic. The timing may be a timing at which the signal is recognized as having L logic.

FIG. 3D shows the input signal SIG11- (2) when the delay time t1 of the rise time generated by passing through the level comparison circuit 154 and the buffer 158 is smaller than the delay time t2 of the fall time. Is shown. FIG.
(E) shows the input signal SIG11- (3) when the delay time t1 of the rise time generated by passing through the level comparison circuit 154 and the buffer 158 is longer than the delay time t2 of the fall time.

Referring to FIG. 2 and FIG. 3, the function of the adjusting device 160 in the present embodiment will be described. First, the difference between the delay time t1 of the rise time and the delay time t2 of the fall time of the input signal SIG11 is determined. The selection unit 176 selects the through path 170, and the pulse width adjustment unit 162
The output pattern signal 142-1 that has passed through the level comparison circuit 154 and the buffer 158 is received as an input signal SIG11. The selector 176 receives the input signal SIG11 that has passed through the through path 170. Here, as the input signal SIG11 passes through the through path 170, the rise time and the fall time of the SIG11 are delayed by the same time. Therefore, the signal output from the selection unit 176 may be any one of the input signals SIG11- (1) to (3) shown in FIGS. 3C to 3E according to the rise time and the fall time of the SIG11. It has a waveform showing the same tendency. Control device 210 receives input signal SI
From the difference between the pulse width of G11- (1) to (3) and the pulse width of the output pattern signal 142-1, the input signal SIG1
The difference between the rise time delay time t1 and the fall time delay time t2 is calculated.

Next, the selector 176 receives the input signal SIG1.
The path is selected so as to correct the difference between the delay time t1 of the rise time and the delay time t2 of the fall time.
For example, as shown in FIG.
When the pulse width of-(1) is equal to the pulse width of the output pattern signal 142-1, the delay time t1 of the rise time and the delay time t2 of the fall time of the input signal SIG11.
Δt = | t1−t2 | = 0 (zero). At this time, the selection unit 176 selects the through path 170 and receives the adjustment signal SIG21. FIG. 3F shows a waveform of the adjustment signal SIG31- (1) that has passed through the through path 170. The input signal SIG11- (1) is
By passing through 0, the rise time is delayed by t3 and the fall time is delayed by t4, which is a time equal to t3. Then, the selection unit 176 sets the SIG31- (1)
Is supplied to the detection signal output unit 180.

For example, as shown in FIG. 3D, the pulse width of the input signal SIG11- (2) is
When the pulse width is larger than the pulse width of the input signal SIG,
The difference between the delay time t1 of the rising time and the delay time t2 of the falling time is Δt = | t1−t2 |.
At this time, the selection unit 176 selects the first route 172,
An adjustment signal SIG22 is received. First delay circuit 166
Is the difference Δt between the delay time t1 of the rise time and the delay time t2 of the fall time of the input signal SIG11- (2).
= | T1−t2 |. That is, the first delay circuit 166 receives the input signal SIG11−
The rise time of (2) is delayed by Δt longer than the fall time. FIG. 3G illustrates a waveform of the adjustment signal SIG31- (2) that has passed through the first path 172. At this time, the delay time t3 of the rise time of the input signal SIG11- (2) is longer than the delay time t4 of the fall time by Δ.
Delayed by t. Therefore, the adjustment signal SIG31- passed through the first path 172 having the first delay circuit 166
The pulse width of (2) is equal to the pulse width of the output pattern signal 142-1. Then, the selection unit 176 sets the SI
G31- (2) is supplied to the detection signal output unit 180.

For example, as shown in FIG. 3E, the pulse width of the input signal SIG11- (3) is
When the pulse width is smaller than the pulse width of the input signal SIG,
The difference between the delay time t1 of the rising time and the delay time t2 of the falling time is Δt = | t1−t2 |.
At this time, the selector 176 selects the second path 174 and receives the adjustment signal SIG23. The second delay circuit 168 is
Difference Δt = | between delay time t1 of rise time and delay time t2 of fall time of input signal SIG11- (3)
It is configured to correct t1-t2 |. That is, the second delay circuit 168 delays the fall time of the input signal SIG11- (3) by Δt more than the rise time. FIG. 3H shows the adjustment signal SIG31- (3) passed through the second path 174. At this time, the input signal SI
The delay time t4 of the fall time of G11- (3) is delayed by Δt more than the delay time t3 of the rise time. Therefore, the second path 1 having the second delay circuit 168
The pulse width of the adjustment signal SIG31- (3) that has passed through 74 becomes equal to the pulse width of the output pattern signal 142-1. Then, the selection unit 176 supplies SIG31- (3) to the detection signal output unit 180.

Similarly, the other comparison circuit units (152-2 to 2-1)
52-n), each of the comparison circuit units (152-2 to 15-2)
The pulse width adjustment unit 162 included in 52-n) adjusts the pulse width of the input output pattern signal (142-2 to 142-n). Each comparison circuit (152-2
The selection unit 176 included in 152-n) supplies the signal to the SIG31 detection signal output unit 180.

The detection timing signal generation section 190 indicates the timing of the detection timing signal STRB output from the detection timing signal output section 182 included in each of the comparison circuit sections (152-2 to 152-n). For example, FIG.
As shown in (c) to (h), the rise time t1 of the input signal SIG11 and the rise time t3 of the adjustment signal SIG31 are determined by the respective comparison circuit units (152-2 to 152-).
Different for each signal adjusted in n). The detection timing signal output unit 182 adjusts the timing at which the detection timing signal STRB changes based on the timing instructed by the detection timing generation unit 190 to the rising time t1 of the input signal SIG11 and the rising time t3 of the adjustment signal SIG31. Delay by a predetermined amount. Therefore, for example, when the detection timing signal generation section 190 gives the same timing to the detection timing signal output sections 182 of the respective comparison circuit sections (152-1 to 152-n), the respective detection signal output sections 180 Adjustment signal SIG
31 can be detected at the same timing.

As described above, the selection section 176 selects one of the paths so that the pulse width of the output pattern signal 142 and the pulse width of the adjustment signal SIG31 are equal, so that the level comparison circuit 154 and the buffer 158 Thus, even if a difference occurs between the rise time and the fall time delay of the output pattern signal 142, the difference can be corrected.

Further, each of the comparator circuits (152-1 to 15-15)
When the same timing is given to the detection timing signal output unit 182 of 2-n), each detection signal output unit 180 can detect the adjustment signal SIG31 at the same timing.

FIG. 4 is a diagram showing another embodiment of the pulse width adjusting unit 262. The pulse width adjustment unit 262 includes a first delay circuit 266, a second delay circuit 268, and a selection unit 267a.
267b and a path 270. Selector 276
a is provided so as to connect the first delay circuit 266 to the path 270, and the selector 276b is provided so as to connect the second delay circuit 268 to the path 270. The first delay circuit 266 is, for example, an installed capacitor and has a function of delaying a rise time of an input signal. Therefore, when the selection unit 267a is short-circuited and the first delay circuit is connected to the path 270, the rise time of the waveform of the input signal SIG11 passing through the path 270 is:
It is delayed more than the fall time. On the other hand, the second delay circuit 268 is, for example, a grounded resistor and has a function of delaying the fall time of an input signal. Therefore, when the selection unit 276b is short-circuited and the second delay circuit 268 is connected to the path 270, the fall time of the waveform of the input signal SIG11 passing through the path 270 is delayed more than the rise time.

As described above, the present invention has been described using the embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be added to the above embodiment. It should be noted that such modified or improved embodiments may be included in the technical scope of the present invention.
It is clear from the description of the claims.

[0043]

As is apparent from the above description, according to the present invention, the delay time of the rise time and the delay time of the fall time of the input signal can be adjusted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a test apparatus.

FIG. 2 is a block diagram illustrating a configuration of a detection unit according to the present embodiment.

FIG. 3 is a timing chart showing a waveform of a signal flowing through a comparator according to the embodiment.

FIG. 4 is a diagram showing another embodiment of the pulse width adjusting unit.

[Explanation of symbols]

100 test equipment, 110 pattern generator, 12
0 timing generator, 130 waveform shaping unit, 14
0 ... signal input / output unit, 150 detection unit, 152 adjustment unit, 152-1 to 152-n comparison circuit unit, 15
4 ··· level comparison circuit, 156 ··· timing comparison circuit, 158 · · buffer, 160 · · · adjustment unit, 162 · · ·
.Pulse width adjustment unit, 164, circuit unit, 166, first
Delay circuit, 168 second delay circuit, 170 through-path, 172 first path, 174 second path, 17
6 selection section, 178 storage section, 180 detection signal output section, 182 detection timing signal output section, 200
..Electronic device, 210..control device, 266..first delay circuit, 268..second delay circuit, 270..path, 276a, 276b..selection unit

Claims (8)

[Claims] 1. A first delay circuit for delaying a rise time of an input signal longer than a fall time of the input signal, and a second delay circuit for delaying a fall time of the input signal longer than a rise time of the input signal. A delay circuit; and a selector that selects one of the first delay circuit and the second delay circuit and outputs the input signal adjusted by the selected delay circuit as an adjustment signal. And adjusting device. 2. The adjustment device according to claim 1, wherein the input signal is adjusted by passing through the delay circuit selected by the selection unit. 3. The adjusting device according to claim 1, further comprising a buffer for shaping a waveform of a predetermined signal and outputting the input signal. 4. The selection section selects one of the first delay circuit and the second delay circuit such that a pulse width of the adjustment signal is equal to a pulse width of the predetermined signal. The adjusting device according to claim 3, wherein: 5. The adjustment device according to claim 1, further comprising a storage unit that stores which of the delay circuits is selected by the selection unit. 6. A detection timing signal output unit for outputting a detection timing signal for detecting a timing at which the adjustment signal changes, and detecting and detecting the adjustment signal based on a timing at which the detection timing signal changes. The adjustment device according to claim 1, further comprising a detection signal output unit that outputs the signal as a signal. 7. The first delay circuit, the second delay circuit, the selection unit, the detection timing signal output unit,
A plurality of adjustment units each including the detection signal output unit; and a detection timing generation unit that instructs the timing to be detected. An input signal is input to each of the plurality of adjustment units, and the detection timing signal output is output. The unit outputs the detection timing signal so that each of the detection signal output units detects the adjustment signal at the same timing when the detection timing generation unit gives the same timing to each of the adjustment units. The adjustment circuit according to claim 6, wherein 8. A test apparatus for testing an electronic device, comprising: a pattern generation unit that generates an input pattern signal to be input to the electronic device; a waveform shaping unit that shapes a waveform of the input pattern signal; A signal input / output unit that electrically contacts an electronic device, supplies the input pattern signal shaped by the waveform shaping unit to the electronic device, and receives an output pattern signal output by the electronic device based on the input pattern signal A timing generation unit that delays a reference clock signal by a desired time to generate a timing signal of a desired frequency; and a detection unit that inputs and detects the output pattern signal output by the electronic device. A first delay circuit for delaying a rise time of the input signal longer than a fall time of the input signal; A second delay circuit for delaying a fall time of the input signal longer than a rise time of the input signal; and selecting one of the first delay circuit and the second delay circuit, and selecting the selected delay. A selector for outputting the input signal adjusted by the circuit as an adjustment signal.