JP2002100961A - Integrating circuit for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrating circuit, for a semiconductor integrated circuit, in which the capacitance of a capacitor can be reduced and in which the formation area of the capacitor in a semiconductor chip can be reduced. SOLUTION: In the integrating circuit, the capacitor (C10) is connected across the inverting input terminal and the output terminal of operational amplifiers (M7 to M10), and a signal is input to the inverting input terminal via a first resistance (R1). The integrated circuit is provided with current-limiting means (26, 28, M1 to M6), which limit the current for raising and lowering the input signal. The charging current and the discharge current of the capacitor (C10) are delayed, and the capacitance of the capacitor (C10) can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integration circuit for a semiconductor integrated device, and more particularly to an integration circuit formed in a semiconductor integrated device.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated device,
2. Description of the Related Art An integrating circuit that integrates a signal is used for various purposes, such as generating a gradient waveform from a rectangular wave signal and further delaying the rectangular wave signal by comparing the gradient waveform with a reference value.

FIG. 4 shows an equivalent circuit diagram of an example of an integrating circuit of a conventional semiconductor integrated device. In the figure, an input signal is supplied to a terminal 10. One end of a resistor R2 is connected to the terminal 10, the other end of the resistor R2 is grounded via a resistor R3, and connected to the inverting input terminal of the operational amplifier 12 via a resistor R1. The output terminal of the operational amplifier 12 is connected to the terminal 14, and the non-inverting input terminal is grounded. Further, a capacitor C1 is connected between the output terminal and the inverting input terminal of the operational amplifier 12, thereby forming a Miller integrating circuit.

[0004]

The time constant τ of the integrating circuit shown in FIG. 4 is represented by τ = C1 · R1. This time constant τ
Is set to a large value on the order of several tens of msec,
Each of the resistance value of the resistor R1 and the capacitance value of the capacitor C1 increases.

[0005] In particular, when the capacitance value of the capacitor C1 increases, the formation area of the capacitor C1 in the semiconductor chip increases, which leads to a problem that the size and cost of the semiconductor integrated device increase.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides an integration circuit of a semiconductor integrated device that can reduce the capacitance of a capacitor and reduce the area of the capacitor formed on a semiconductor chip. With the goal.

[0007]

According to the first aspect of the present invention, a capacitor (C10) is connected between an inverting input terminal and an output terminal of an operational amplifier (M7 to M10), and a capacitor (C10) is connected to the inverting input terminal. Current limiting means (26, 28, M1 to M1) for limiting a current that causes the input signal to rise and fall in an integration circuit that inputs a signal via one resistor (R1).
By having 6), the charge current and the discharge current of the capacitor (C10) can be limited to delay the charge time and the discharge time of the capacitor (C10), thereby reducing the capacitance of the capacitor (C10).

According to a second aspect of the present invention, in the integration circuit of the first aspect, the current limiting means (26, 28, M
1 to M6) are signal inverting means (M4, M5) for inverting a supplied signal and outputting the inverted signal as the input signal, and a first current source (2) for limiting a rising current of the input signal.
6, M1, M3) and the second current source (28, M2, M6) for limiting the falling current of the input signal, so that the current for rising and falling the input signal can be limited. it can.

According to a third aspect of the present invention, in the integration circuit according to the first or second aspect, the signal inverting means (M4,
M5) and the first resistor (R1), by having a voltage dividing circuit (R2, R3) for dividing the voltage of the input signal, the input signal rises and rises by reducing the input voltage. The lowering current can be limited.

The reference numerals in the parentheses are provided for easy understanding, are merely examples, and are not limited to the illustrated embodiment.

[0011]

FIG. 1 is a circuit diagram showing an embodiment of an integrating circuit of a semiconductor integrated device according to the present invention. In the figure, terminal 2
0 is supplied with an input signal, and the power supply terminal 22 is connected to the power supply VDD.
Is supplied, and the power supply terminal 24 is grounded. The P-channel MOS transistor M1 has a source and a back gate connected to the power supply VDD, a drain and a gate connected to one end of the constant current source 26, and the other end of the constant current source 26 is grounded. The constant current source 26 supplies the current I2.

An N-channel MOS transistor M2
Has a source and a back gate grounded, a drain and a gate connected to one end of a constant current source 28, and the other end of the constant current source 28 connected to a power supply VDD. The constant current source 28 allows a current I1 (I1 = I2) to flow. MOS transistor M1
Is commonly connected to the gate of P-channel MOS transistor M3, and MOS transistors M1 and M3 form a current mirror circuit.
The gate of 2 is commonly connected to the gate of N-channel MOS transistor M6, and MOS transistors M2 and M6 constitute a current mirror circuit.

The terminal 20 is connected to the gate of the P-channel MOS transistor M4 and the gate of the N-channel MOS transistor. The MOS transistor M4 has a source connected to the drain of the MOS transistor M3, a back gate connected to the power supply VDD, and a drain commonly connected to the drain of the MOS transistor M5. The source and the back gate of the MOS transistor M3 are connected to the power supply VDD.

The source of the MOS transistor M5 is MOS.
The drain is connected to the drain of the transistor M6, the back gate is grounded, and the drain is commonly connected to the drain of the MOS transistor M4. The source and the back gate of the MOS transistor M6 are grounded. MO
S transistors M4 and M5 constitute an inverter, and
The S transistor M3 functions as a current source that sets the drain current of the MOS transistor M4 to a current I2.
The MOS transistor M6 functions as a current source that sets the drain current of the MOS transistor M5 to the current I1.

One end of a resistor R2 is connected to a point A, which is a commonly connected drain of the MOS transistors M4 and M5, and the other end of the resistor R2 is grounded via a resistor R3 and operated via a resistor R1. It is connected to a point B which is a gate of a P-channel MOS transistor M7 which is an inverting input terminal of the amplifier 12.

The source and back gate of the MOS transistor M7 are commonly connected to the source and back gate of the P-channel MOS transistor M8, and are connected to one end of the constant current source 30 to form a differential circuit. The end is connected to the power supply VDD. MOS transistor M7
Is connected to the drain of an N-channel MOS transistor M9, and the drain of the MOS transistor M8 is connected to the drain and gate of an N-channel MOS transistor M10. MOS transistors M9, M1
The gates of the MOS transistors M9, M9,
The source of each of M10 is grounded. The reference voltage Vre is supplied from the terminal 32 to the gate of the MOS transistor M8.
f is supplied.

As a result, the MOS transistors M9, M
Reference numeral 10 forms a current mirror circuit and operates as a current source for each of the MOS transistors M7 and M8. The MOS transistors M7 to M10 constitute an operational amplifier. The gates of the MOS transistors M7 and M8 correspond to the inverting input terminal and the non-inverting input terminal, respectively. The drain of the MOS transistor M7, which is the output terminal of the operational amplifier, is connected to the terminal 34. A capacitor C10 is connected to the MOS transistor M7 to M10, the resistor R1, and the capacitor C10 to form a Miller integrating circuit.

Here, when a low level signal is supplied to the terminal 20, the MOS transistor M4 is turned on and the MOS transistor M4 is turned on.
The transistor M5 is turned off, and the MOS transistor M3
, The current I2 flows to the drain of the MOS transistor M4, so that the point A becomes high level. When a high-level signal is supplied to the terminal 20, the MOS transistor M4 is turned off, the MOS transistor M5 is turned on, and M
Since the current I1 flows through the drain of the MOS transistor M5 by the OS transistor M6, the point A becomes low level.

Now, when the signal supplied to the terminal 20 changes from low level to high level, the voltage at the point A rapidly changes from high level to low level, and the voltage divided by the resistors R2 and R3 is It is supplied to the integration circuit through R1. Assuming that the input impedance of the operational amplifier is infinite, since the gates of the MOS transistors M7 and M8 are a virtual short, the current I4 flowing through the resistor R1
Between the current I5 flowing through the capacitor C10 and I4 = −
The relationship of I5 is established.

The waveform integrated by the integration circuit is represented by a capacitor C
10 and its charging current I5,
The integral waveform can be controlled by controlling the current I5 input to the integration circuit. At the rising edge of the signal at the point C, which is the input terminal of the integrating circuit, the input current I4 of the integrating circuit is limited by the current I1 to delay the charging time of the capacitor C10. This limits the charging time of the capacitor C10.

Although the input current I4 can be limited by reducing the input voltage of the integrating circuit by the voltage dividing ratio of the resistors R2 and R3, the resistance ratio of the resistors R2 and R3 formed in the same process is set to 1000: 1 or more. If an attempt is made to increase the ratio, the area required for forming the resistors R2 and R3 becomes large. Therefore, in this embodiment, the resistance ratio of the resistors R2 and R3 is set to 50:
By setting the value to about 1, the input current I4 is limited as described above to control the integral waveform, thereby reducing the capacitance of the capacitor C10.

Here, the current I1 = I2 = 2 μA and R1 =
1000KΩ, R2 = 325KΩ, R = 5KΩ, C10
2A, the solid line shows the input signal waveform of the terminal 20, the broken line shows the inverted waveform of the point A, and the solid line shows the output signal waveform of the terminal 34. Also, current I1 = I2 = 1 μA, R1 = 1000 KΩ, R1
When 2 = 500 KΩ, R = 5 KΩ, and C10 = 20 pF, FIG. 3 (A) shows the input signal waveform of the terminal 20 with a solid line, the broken line shows the inverted waveform of the point A, and FIG. 3 shows an output signal waveform of a terminal 34. In this case, the capacitance of the capacitor can be reduced to about 1/10 as compared with the conventional circuit. That is, the formation area of the capacitor in the semiconductor chip can be reduced to about 1/10.

[0023]

As described above, the first aspect of the present invention provides
By having the current limiting means for limiting the rising and falling currents of the input signal, it is possible to limit the charging current and discharging current of the capacitor, delay the charging time and discharging time of the capacitor, and reduce the capacitance of the capacitor. In addition, the formation area of the capacitor can be reduced.

According to a second aspect of the present invention, the current limiting means includes a signal inverting means for inverting a supplied signal and outputting the inverted signal as the input signal, and a first current source for limiting a rising current of the input signal. By using the second current source for limiting the falling current of the input signal, it is possible to limit the rising and falling currents of the input signal.

According to a third aspect of the present invention, the input signal is reduced by providing a voltage dividing circuit between the signal inverting means and the first resistor for dividing the voltage of the input signal. The rise and fall current can be limited.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of an integration circuit of a semiconductor integrated device of the present invention.

FIG. 2 is a signal waveform diagram of each part of an integration circuit of the semiconductor integrated device of the present invention.

FIG. 3 is a signal waveform diagram of each part of the integration circuit of the semiconductor integrated device of the present invention.

FIG. 4 is a circuit diagram of an example of an integration circuit of a conventional semiconductor integrated device.

[Explanation of symbols]

 20, 32 terminal 22, 24 power supply terminal 26, 28, 30 constant current source C10 capacitor R1 to R3 resistance M1 to M10 MOS transistor

Claims (3)

[Claims] 1. An integration circuit for connecting a capacitor between an inverting input terminal and an output terminal of an operational amplifier and inputting a signal to the inverting input terminal via a first resistor, wherein the input signal rises and rises. An integrating circuit for a semiconductor integrated device, comprising current limiting means for limiting a current to be reduced. 2. The integration circuit according to claim 1, wherein the current limiting means inverts a supplied signal and outputs the inverted signal as the input signal, and a current limiting means for limiting a rising current of the input signal. An integrated circuit for a semiconductor integrated device, comprising: one current source; and a second current source that limits a falling current of the input signal. 3. The semiconductor integrated circuit according to claim 1, further comprising a voltage dividing circuit for dividing a voltage of the input signal between the signal inverting means and the first resistor. The integration circuit of the device.