JP2002099407A - Start-code retrieval circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten detecting time for detecting a start-code by retrieving a bit stream. SOLUTION: In accordance with the results of comparison between shift output of a shifter circuit S1 shifting the bit stream and comparison information of a shifting-amount output table T3, the start-code retrieval circuit is provided so that a shifting amount of the shifter circuit S1 is given and the start-code is detected in retrieving the bit stream.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a start code search circuit for searching a bit stream and detecting a start code included in the bit stream.

[0002]

2. Description of the Related Art For example, M which is one of information compression standards
As a decoding device for decoding compressed image data (hereinafter, referred to as a bit stream) based on PEG, for example, there is a decoding device as shown in FIG. In FIG. 5, the decoding device includes a variable length code decoder circuit B1, an RLD circuit B2, an inverse quantization circuit B3, an inverse DCT circuit B4, a motion compensation / frame prediction circuit B5, and a frame memory M1.

In such a decoding device, a bit stream is transmitted to, for example, an external device such as a satellite radio receiver or a DV.
D or the like. From the input bit stream, a variable length code decoding circuit B1 searches for a start code as a mark in the bit stream. In the search, run level information of a DCT coefficient of an image, a motion vector, and other header information are sequentially decoded from a bit stream. The decoded run level information of the DCT coefficient is converted into a DCT coefficient by the RLD circuit B2, and further inversely quantized by the inverse quantization circuit B3 with a value determined by the quantization characteristic and the quantization matrix. And the inverse DCT circuit B4
Inverse discrete cosine transform by
It is input to the frame prediction circuit B5. In the case of an I picture, the motion compensation / frame prediction circuit B5 outputs a decoded image as a decoded signal. In the case of a P or B picture, a predicted image is generated using a motion vector from the image information stored in the frame memory M1 as appropriate according to each image type,
The sum of the decoded image and the predicted image is output as a decoded signal.

FIG. 6 is a diagram showing a configuration of a conventional variable length code decoding circuit with a start code search function. In FIG. 6, a variable-length code decoding circuit with a start code search function includes registers R1 to R5, an adder A1, a shifter circuit S1, a conversion table T1 for converting a bit stream into a run-level format of DCT coefficients, and the like. Is provided with a code length output table T2 for outputting a code length from a code word in the above, and a determination circuit C1 for detecting a start code. Note that in MPEG, the start code is 32 bits long, and 2 bits from the most significant bit.
The third bit is characterized by "0" and the 24th bit is "1". It is assumed that the start code is byte-aligned in the bit stream.

In FIG. 6, a bit stream is stored in a register R2, R3, R4 in the FIFO in order from the head. The first bit position of the bit stream stored in the registers R2 to R4 is held in the register R1. In this state, when the clock is advanced by one cycle, the bit stream output from the registers R2 to R4 is searched by the shifter circuit S1 and stored in the register R5. This is an initial state.

Next, by referring to the determination circuit C1 with the value of the register R5, it is determined whether or not the cueed data stored in the register R5 is a start code. Until the start code is determined, the bit stream for 8 bits is truncated from the beginning. That is, the following processing is performed.

[0007] 1. Adder A adds the value of register R1 and "8"
The value added by 1 (this is referred to as n) becomes the position of the head of a new bit stream. The lower 5 bits of this value n are
It is stored in the register R1.

[0008] 2. FIFO (registers R2, R3, R
The output from 4) is shifted by n bits using the shifter circuit S1, and the cueed bit stream is stored in a register R5.
To be stored.

3. If n is a value of 32 or more, F
Update the IFO by 32 bits.

By performing such a search process, a start code is detected from a given bit stream, and the detected start code is stored in the register R5.

[0011]

As described above,
In a conventional search circuit that searches for a start code from a bit stream, when a 32-bit start code is detected from the bit stream, 8 bits per cycle from the head of a series of bit streams (= byte interval of the start code) Search was progressing one by one. For this reason, in order to detect a start code from a bit stream, a problem that a long search time is required is caused.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and it is an object of the present invention to provide a start code search circuit in which a bit stream is searched for a start code to reduce a detection time. It is in.

[0013]

In order to achieve the above object, a first means for solving the problem is to shift input compressed data (bit stream) according to a given shift amount, and A shifter circuit that outputs a unit bit stream having the same number of bits as the start code from the bit stream obtained, and a determination circuit that determines whether the unit bit stream output from the shifter circuit is a start code, A start code search circuit for sequentially searching while shifting a series of bit streams by a shifter circuit and detecting a start code from the series of bit streams receives a unit bit stream output from the shifter circuit, It is prepared in advance according to the stream and the bit array of the start code. Comparing the plurality of comparison information, characterized by comprising the shift amount output table giving the shift amount of the shifter circuit according to the comparison result.

[0014] The second means is the first means,
The shift amount output table indicates that the relationship between the comparison information (bit stream) and the shift amount (cutoff amount) corresponding to the comparison information is as follows:

[0015]

[Table 3] It is characterized by being.

A third means is that, in the shift amount output table, the relationship between the comparison information (bit stream) and the shift amount (cutoff amount) corresponding to the comparison information is as follows.

[0017]

[Table 4] It is characterized by being.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a start code search circuit according to one embodiment of the present invention. In FIG. 1, the start code search circuit of this embodiment includes a shift amount output table T3 in addition to the configuration shown in FIG. 6, and decodes a variable length code from a bit stream in the same manner as the circuit shown in FIG. (Not a feature of the present invention), the conversion table T1 and the code length output table T2 similar to those shown in FIG. 6 are exclusively used when decoding a variable length code from a bit stream. Components. Also, the registers R1 to R
5. The adder A1 and the shifter circuit S1 are used when detecting a start code from a bit stream and also when decoding a variable length code from a bit stream. In this embodiment,
The start code has the same bit configuration as in the related art, and is assumed to be byte-aligned in the bit stream.

The shift amount output table T3 includes a register R
5 and the 32-bit bit stream stored in FIG.
Is compared with four pieces of comparison information of 32 bits shown in (1), and a truncation amount (shift amount) m is output according to the comparison result. 32
The bit comparison information is, as shown in FIG.

[Table 5] (1) 00000000_00000000_00000001_XXXXXXXX (2) XXXXXXXX_00000000_00000000_00000001 (3) XXXXXXXX_XXXXXXXX_00000000_00000000 (4) XXXXXXXX_XXXXXXXX_XXXXXXXX_00000000 When the 32-bit bit stream stored in the register R5 matches the comparison information shown in the above (1), if both match, the bit stream stored in the register R5 is a start code and the determination circuit The start code is detected by C1. Therefore, no truncation is performed, and the truncation amount m is “0”. Next, in the comparison between the 32-bit bit stream stored in the register R5 and the comparison information shown in the above (2), if both match, the shift amount output table T3 sets “8” as the truncation amount m. Is output. In the comparison between the 32-bit bit stream stored in the register R5 and the comparison information shown in the above (3), if both match, the shift amount output table T3
Outputs “16” as the truncation amount m. In the comparison between the 32-bit bit stream stored in the register R5 and the comparison information shown in the above (4), if both match, the shift amount output table T3 outputs “24” as the truncation amount m. . If the 32-bit bit stream stored in the register R5 does not match any of the values in the shift amount output table, the shift amount output table T3 outputs “32” as the truncation amount m. . Such a shift amount output table T3 is composed of, for example, a logic gate, a RAM of a memory, a ROM, and the like.

In such a configuration, first, the FIFO
(Registers R2, R3, R4) store bit streams in order from the top. The first bit position of the bit stream stored in the FIFO is held in the register R1.
If the clock is advanced by one cycle in this state, the FIFO
The shifter circuit S1 outputs a 32-bit bit stream from the bit stream output from, and performs cueing, and stores it in the register R5. This is an initial state.

In such an initial state, the judgment circuit C
By referring to 1 by the value of the register R5, it is determined whether or not the value stored in the register R5 is a start code. Until the start code is determined, the bit stream for m bits is sequentially discarded from the beginning. The value of the truncation amount m is the value of the shift amount output table T3 when the value of the register R5 is sequentially compared with the value shown in FIG. When the value of the lower 24 bits of the register R5 is “00”
000000_00000000_00000001 ”is determined, and if they match, m = 8. It is determined whether or not the value of the lower 16 bits of the register R5 matches "00000000_00000000". If the value matches, m = 16. When the value of the lower 8 bits of the register R5 is “0000000”
It is determined whether or not it matches "0", and if matched, m = 24. If neither is the case, m = 32.

As described above, when the truncation amount m is output from the shift amount output table T3, the bit stream supplied from the FIFO (registers R2, R3, R4) to the shifter circuit S1 is based on the truncation amount. The data is shifted in S1 and truncated. The truncation process is performed in the same manner as in the related art, and the shift amount output table T
3 is added to the value stored in the register R1 by the adder A1, and the result of the addition is given to the shifter circuit S1 from the FIFO (registers R2, R3, R4) as a shift amount. Is the shifter circuit S
Shifted by one.

Such search processing is sequentially performed until a start code is detected from the bit stream. Therefore, in the above-described embodiment, the provision of the shift amount output table T3 makes it possible to advance the search of the bit stream at a maximum of 32 bits per cycle. As a result, the time required to detect the start code from the bit stream can be reduced as compared with the related art.

FIG. 3 is a diagram showing a configuration of a start code search circuit according to another embodiment of the present invention. In FIG. 3, the feature of this embodiment is that the start code can be applied to a code that is not byte-aligned in the bit stream, and the shift amount output table T3 shown in FIG. Table T4
The other configuration is the same as that of FIG. In FIG. 3, components having the same reference numerals as those in FIG. 1 have the same configuration, and a description thereof will be omitted.

The shift amount output table T4 includes a register R
4 and the 32-bit bit stream stored in FIG.
And outputs a truncation amount (shift amount) m according to the comparison result. As shown in FIG. 4, the 32-bit comparison information is “00000000_0000000”.
0_00000001_XXXXXXXX ''-`` XXXXXXXX_XXXXXXXX_XXXXXX ''
XX_XXXXXXX0 ", and the truncation amount m is m = 0 to 31, as shown in FIG. 4, corresponding to the respective pieces of comparison information. If no match is found, m = 32.

Using such a shift amount output table T4, the shifter circuit S1 shifts based on the truncation amount m output from the shift amount output table T4 in exactly the same manner as in the previous embodiment, and searches for a bit stream. To detect the start code from the bit stream. Therefore, in such an embodiment, even when the start code is not byte-aligned in the bit stream, the same effect as in the previous embodiment can be obtained.

[0028]

As described above, according to the present invention, the shift amount of the shifter circuit is given according to the comparison result between the shift output of the shifter circuit for shifting the bit stream and the comparison information of the shift amount output table. With this configuration, the start code is detected by searching the bit stream, so that the time required to detect the start code can be reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a start code search circuit according to one embodiment of the present invention.

FIG. 2 is a diagram showing the contents of a shift amount output table T3 shown in FIG. 1;

FIG. 3 is a diagram showing a configuration of a start code search circuit according to another embodiment of the present invention.

4 is a diagram showing the contents of a shift amount output table T4 shown in FIG.

FIG. 5 is a diagram showing a configuration of a conventional device for decoding compressed image data.

FIG. 6 is a diagram showing a configuration of a conventional variable-length code decoding circuit having a start code search function.

[Explanation of symbols]

 R1, R2, R3, R4, R5 Register A1 Adder S1 Shifter circuit C1 Judgment circuit T1 Conversion table T2 Code length output table T3, T4 Shift amount output table

Claims (3)

[Claims] 1. A shifter circuit for shifting input compressed data (bit stream) according to a given shift amount, and outputting a unit bit stream having the same number of bits as a start code from the shifted bit stream; A determination circuit for determining whether or not the unit bit stream output from is a start code. The shifter circuit sequentially searches a series of bit streams while shifting, and starts from a series of bit streams. In a start code search circuit for detecting a code, receiving the unit bit stream output from the shifter circuit, and comparing the unit bit stream with a plurality of pieces of comparison information prepared in advance according to the bit arrangement of the start code, The shift amount of the shifter circuit is given according to the comparison result. A start code search circuit comprising a shift amount output table. 2. The relationship between the comparison information (bit stream) and the shift amount (truncated amount) corresponding to the comparison information in the shift amount output table is as follows. 2. The start code search circuit according to claim 1, wherein: 3. The shift amount output table shows a relationship between comparison information (bit stream) and a shift amount (cutoff amount) corresponding to the comparison information. 2. The start code search circuit according to claim 1, wherein: