JP2002098993A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make occurrence of shorting due to working defects between data signal lines including drain electrodes and source electrodes of a liquid crystal display device having thin-film transistors(TFTs) less likely to occur. SOLUTION: The end edges on the side of the data signal lines 3 facing the TFTs 4 are formed to a straight form, extending in the column direction. The straight-form end edges are used commonly as drain electrodes 6. The direction where the gate electrodes 5, drain electrodes 6, and source electrodes 7 of the TFTs 4 are arranged, i.e., a channel length direction, is the row direction. The shapes of the channels between the source electrodes 7 and the drain electrodes 6 and the data signal lines 3 near the same are therefore formed to the straight form, extending in the column direction which is the same direction as the direction in which the data signal lines 3 are arranged. Consequently, when the data signal lines 3 which includes the drain electrodes 6 and the source electrodes 7 are formed through wet etching, etchant hardly stagnates in these channels any longer and the occurrence of working defects are less likely to occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art In a liquid crystal display device, R (red), G
There are several types depending on how the (green) and B (blue) color filter elements and the corresponding pixel electrodes are arranged, and one of them is a delta arrangement. In the liquid crystal display device of this delta arrangement, scanning is performed because three pixel electrodes of R, G, and B constituting one pixel are arranged at positions corresponding to respective vertices of an isosceles triangle (Greek letter Δ). The signal lines are arranged linearly in the row direction, while the data signal lines are arranged meandering in the column direction.

FIG. 8 is a partially transparent plan view of an example of such a conventional liquid crystal display device. The three pixel electrodes 1 of R, G, and B constituting one pixel are arranged at positions corresponding to respective vertices of an isosceles triangle, and the scanning signal lines 2 are linearly arranged in the row direction between the upper and lower pixel electrodes 1. The data signal lines 3 are arranged in a meandering manner in the column direction between the left and right pixel electrodes 1 and between the upper and lower pixel electrodes 1.

[0006] For example, the lower left corner of the pixel electrode 1 in the odd row (upper in FIG. 8) and the lower right corner of the pixel electrode 1 in the even row (lower in FIG. 8) are cut out in a square shape. The thin film transistors 4 are arranged symmetrically in the column direction in odd rows and even rows. Thin film transistor 4
This is because, for the same color, for example, G pixel electrodes 1 arranged in a staggered manner in the column direction, they are connected to the same data signal line 3 via the thin film transistor 4.

The thin film transistor 4 is connected to the scanning signal line 2 via the gate electrode 5, connected to the data signal line 3 via the drain electrode 6, and connected to the pixel electrode 1 via the source electrode 7. In this case, the arrangement direction of the gate electrode 5, the drain electrode 6, and the source electrode 7, that is, the channel length direction is the column direction, and the drain electrode 6 projects from the data signal line 3 in the row direction.
The reason why the thin film transistor 4 has such a structure will be described later.

Below the upper side of the pixel electrode 1, auxiliary capacitance lines 8 are linearly arranged in the row direction. In this case, the auxiliary capacitance electrode 8 extending downward from the auxiliary capacitance line 8
“a” is disposed below a part of the right side of the left pixel electrode 1, a part of the left side of the right pixel electrode 1, and the data signal line 3 disposed therebetween. The portion of the data signal line 3 that intersects with the scanning signal line 2, the portion overlapped with the tip of the auxiliary capacitance electrode 8a, and the portion located near the thin film transistor 4 are slightly wider than other portions. . This is especially true for data signal line 3
The reason is that the portion over the step at the both ends in the width direction of the scanning signal line 2 and the portion over the step at the tip of the auxiliary capacitance electrode 8a are hardly disconnected.

Next, a specific structure of a part of the liquid crystal display device will be described with reference to FIG.
This will be described with reference to FIG. A scanning signal line 2 including a gate electrode 5 is provided at a predetermined location on the upper surface of the glass substrate 11, and an auxiliary capacitance line 8 including an auxiliary capacitance electrode 8a is provided at another predetermined location on the upper surface of the glass substrate 11. A gate insulating film 12 made of silicon nitride is provided on the entire upper surface. Gate insulating film 1 on gate electrode 5
A semiconductor thin film 13 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the semiconductor device 2. Semiconductor thin film 1
A channel protection film 14 (see FIG. 8) made of silicon nitride is provided at a predetermined position on the upper surface of the second substrate 2. Ohmic contact layers 15 and 16 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 14 in the channel length direction and on the upper surface of the semiconductor thin film 13.

The data signal line 3 including the drain electrode 6 is provided at a predetermined position on the upper surface of one ohmic contact layer 15 and the upper surface of the gate insulating film, and the source electrode 7 is provided on the upper surface of the other ohmic contact layer 16. The overcoat film 17 made of silicon nitride is provided on the entire upper surface. A contact hole 18 is provided in a portion of the overcoat film 17 corresponding to a predetermined portion of the source electrode 7. Overcoat film 17
The pixel electrode 1 is connected to the source electrode 7 via a contact hole 18 at a predetermined location on the upper surface of the pixel electrode 1. Here, the thin film transistor 4 is constituted by the gate electrode 5, the gate insulating film 12, the semiconductor thin film 13, the channel protective film 14, the ohmic contact layers 15, 16, the drain electrode 6, and the source electrode 7.

Next, a method of manufacturing a part of the liquid crystal display device will be described with reference to FIGS. First, as shown in FIG. 10, the scanning signal line 2 including the gate electrode 5 is formed at a predetermined position on the upper surface of the glass substrate 11, and the auxiliary capacitance electrode 8a is formed at another predetermined position on the upper surface of the glass substrate 11. An auxiliary capacitance line 8 including the same is formed.
Next, a gate insulating film 12 made of silicon nitride, a semiconductor thin film 13 made of intrinsic amorphous silicon, and a film 14a for forming a channel protective film made of silicon nitride are formed on the entire upper surface of the glass substrate 1 including the scanning signal lines 2 and the auxiliary capacitance lines 8. Are continuously formed.

Next, a photoresist film 21 for forming a channel protective film is formed at a predetermined location on the upper surface of the film 14a for forming a channel protective film on the gate electrode 5 by surface exposure using an exposure mask. Next, the photoresist film 21
When the film 14a for forming a channel protective film is etched with the mask as a mask, as shown in FIG.
The channel protective film 14 is formed under the channel protection film 1. Next, the photoresist film 21 is peeled off.

Next, as shown in FIG. 12, an ohmic contact layer forming layer 22 made of n-type amorphous silicon and a metal film 23 made of chromium or the like are continuously formed on the entire upper surface of the semiconductor thin film 13 including the channel protective film 14. To form a film. Next, photoresist films 24a and 24b are formed at predetermined positions on the upper surface of the metal film 23, respectively. In this case, the photoresist film 24a is for forming the data signal line 3 including the drain electrode 6, and the photoresist film 24b is for forming the source electrode 7. Next, when the metal film 23 is wet-etched using the photoresist films 24a and 24b as a mask, the data signal line 3 including the drain electrode 6 is formed below the photoresist film 24a as shown in FIG.
Source electrode 7 is formed below 4b.

Next, the photoresist films 24a, 24b,
Ohmic contact layer forming layer 22 and semiconductor thin film 13 using drain electrode 6 and source electrode 7 as masks
Is dry-etched, one ohmic contact layer 15 is formed below the drain electrode 6, and the other ohmic contact layer 16 is formed below the source electrode 7, as shown in FIG. Further, the semiconductor thin film 1 is formed under both the ohmic contact layers 15 and 16 and under the channel protective film 14.
3 remain. Next, the photoresist films 24a, 24
b is peeled off.

Next, as shown in FIG. 9, an overcoat film 17 made of silicon nitride is formed on the entire upper surface of the gate insulating film 12 including the thin film transistor 4 and the like. next,
A contact hole is formed in a portion of the overcoat film corresponding to a predetermined portion of the source electrode. next,
The pixel electrode 1 is formed at a predetermined position on the upper surface of the overcoat film 17.
Is formed by connecting to the source electrode 7 via the contact hole 18.

Here, the reason why the arrangement direction of the gate electrode 5, the drain electrode 6, and the source electrode 7 of the thin film transistor 4, that is, the channel length direction is set as the column direction, and the drain electrode 6 is projected from the data signal line 3 in the row direction will be described. I do. As described above, the photoresist film 21 for forming the channel protective film shown in FIG. 10 is formed by surface exposure using an exposure mask. At this time, if a misalignment occurs in the row direction in FIG. Is shifted to the right side, for example.

On the other hand, as described above, in the case of the delta arrangement, the thin film transistors 4 are symmetrical in odd rows and even rows. Therefore, the formation position of the channel protective film 14 is also symmetrical between the odd-numbered rows and the even-numbered rows as designed. However, even if the channel protective film 14 is shifted to the right as a whole, in FIG. 8, the distance between the upper side of the channel protective film 14 and the upper side of the gate electrode 4 is the same between the odd rows and the even rows. As a result, the overlapping area of the gate electrode 5 and the source electrode 7 at the above-described interval is the same between the odd-numbered rows and the even-numbered rows without any difference. It is possible to make it hard to be different from an even-numbered row. This is the reason.

[0016]

However, in the above-mentioned conventional liquid crystal display device, as shown in FIG. 8, the arrangement direction of the gate electrode 5, drain electrode 6 and source electrode 7 of the thin film transistor 4, that is, the channel length direction is the column direction. Since the drain electrode 6 projects from the data signal line 3 in the row direction, a substantially L-shaped groove is formed between the source electrode 7 and the drain electrode 6 and the data signal line 3 in the vicinity thereof. Will be. As shown in FIG. 13, when the data signal line 3 including the drain electrode 6 and the source electrode 7 are formed, the grooves having a substantially L-shape in the plane become somewhat deep because the photoresist films 24a and 24b are present. As a result, the photoresist films 24a, 24b
When the metal film 23 is wet-etched using the mask as a mask, the etchant tends to stay in the substantially L-shaped groove on the plane, causing processing defects, and causing a gap between the data signal line 3 including the drain electrode 6 and the source electrode 7. However, there is a problem that a short circuit may occur. SUMMARY OF THE INVENTION It is an object of the present invention to prevent short-circuiting between a data signal line including a drain electrode and a source electrode due to processing defects.

[0017]

According to the first aspect of the present invention, a pixel electrode is provided in a region surrounded by a scanning signal line extending in a row direction and a data signal line extending in a column direction. Is disposed, a thin film transistor is disposed in a cutout provided in the pixel electrode, a gate electrode of the thin film transistor is connected to the scanning signal line, and a drain electrode disposed on one side of the gate electrode is disposed in the data signal line. In a liquid crystal display device in which a source electrode disposed on the other side of the gate electrode is connected to the pixel electrode, a channel length defined by a drain electrode and a source electrode of the thin film transistor is disposed in a row direction. The two edges of the channel protective film provided on the gate electrode in the channel length direction are aligned by self-alignment of the gate electrode. It is obtained by forming. According to a second aspect of the present invention, in the first aspect of the present invention, the edge of the data signal line on the side facing the thin film transistor is formed in a linear shape extending in a column direction, and the linear edge is formed on the linear edge. It also serves as a drain electrode. Claim 3
The width of a portion of the data signal line facing the thin film transistor is substantially the same as the width of a portion where the data signal line intersects with the scanning signal line in the invention according to claim 2, The width is larger than the width of the data signal line between the portion facing the thin film transistor and the intersection of the scanning signal line. According to a fourth aspect of the present invention, in the third aspect of the present invention, the edge of the channel protective film on the side of the drain electrode is defined by a portion of the data signal line facing the thin film transistor and an intersection of the scanning signal line. It is located inside the width of the data signal line between them. According to a fifth aspect of the present invention, in the first aspect of the present invention, the pixel electrodes are arranged in a delta arrangement,
The data signal lines are arranged in a meandering manner in a column direction. According to a sixth aspect of the present invention, in the fifth aspect of the invention, the thin film transistors are arranged symmetrically in odd and even rows in the column direction. According to the first aspect of the present invention, the channel length defined between the drain electrode and the source electrode of the thin film transistor is arranged in the row direction. Between the data signal line including the drain electrode and the source electrode, resulting in a short circuit due to processing defects. It can be difficult to do. In this case, the both ends in the channel length direction of the channel protection film provided on the gate electrode are formed by self-alignment of the gate electrode. When the channel protection film is formed, no misalignment occurs in the row direction. That is to ensure.

[0018]

FIG. 1 is a transmission plan view of a main part of a liquid crystal display device according to an embodiment of the present invention. Also in this liquid crystal display device, R forming one pixel,
G and B pixel electrodes 1 are arranged at positions corresponding to respective vertices of an isosceles triangle, scanning signal lines 2 are arranged linearly in the row direction between upper and lower pixel electrodes 1, and data signal lines 3 are arranged. Between left and right pixel electrodes 1 and upper and lower pixel electrodes 1
They are arranged meandering in the column direction between them.

For example, the lower left corner of the odd-numbered row of pixel electrodes 1 shown in FIG. 1 and the lower right corner of the even-numbered row of pixel electrodes 1 (not shown) are cut out in a rectangular shape. And even rows are symmetrically arranged in the column direction. Also in this case, the pixel electrodes 1 of the same color arranged in a staggered manner in the column direction are connected to the same data signal line 3.
Are connected via a thin film transistor 4.

In this case, however, the edge of the data signal line 3 on the side facing the thin film transistor 4 has a linear shape extending in the column direction, and the linear edge also serves as the drain electrode 6. The arrangement direction of the gate electrode 5, the drain electrode 6, and the source electrode 7 of the thin film transistor 4, that is, the channel length direction is the row direction. The gate electrode 5 is connected to the scanning signal line 2, and the source electrode 7 is connected to the pixel electrode 1. Further, both ends of the channel protective film 14 of the thin film transistor 4 in the channel length direction are:
For the reason to be described later, it is formed in a self-aligned manner with the gate electrode 5, and is located at the same position as the both ends of the gate electrode 5 in the same direction or slightly inside.

Below the upper side of the pixel electrode 1, auxiliary capacitance lines 8 are linearly arranged in the row direction. Also in this case, the auxiliary capacitance electrode 8a extending downward from the auxiliary capacitance line 8 is disposed at a part of the right side of the left pixel electrode 1, a part of the left side of the right pixel electrode 1, and between them. It is arranged below the data signal line 3. The portion of the data signal line 3 that intersects with the scanning signal line 2, the portion overlapped with the tip of the auxiliary capacitance electrode 8a, and the portion located near the thin film transistor 4 are slightly wider than other portions. . In other words, the data signal line 3
In the portion extending in the column direction, the auxiliary capacitance electrode 8a
Are formed narrow. This is because the area shielded by the data signal line 3 is reduced to improve the aperture ratio. However, at the intersection with the scanning signal line 2 and the stepped portion riding on the auxiliary capacitance line 8,
The width is widened to prevent disconnection. Further, the edge of the channel protective film of the thin film transistor on the drain electrode 6 side is arranged close to the data signal line 3 side so as to be inside the edge of the narrow portion of the data signal line 3 described above. ing. This is also to improve the aperture ratio by bringing the position of the thin film transistor 4 as close to the data signal line 3 as possible. Here, it should be noted that the length of the narrow portion of the data signal line 3 is much shorter than the actual length for the sake of illustration.

FIG. 2 is a sectional view taken along line XX of FIG. 1 showing a specific structure of a part of the liquid crystal display device.
This will be described with reference to FIG. A scanning signal line 2 including a gate electrode 5 is provided at a predetermined location on the upper surface of the glass substrate 11, and an auxiliary capacitance line 8 including an auxiliary capacitance electrode 8a is provided at another predetermined location on the upper surface of the glass substrate 11. A gate insulating film 12 made of silicon nitride is provided on the entire upper surface. Gate insulating film 1 on gate electrode 5
A semiconductor thin film 13 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the semiconductor device 2. Semiconductor thin film 1
A channel protection film 14 made of silicon nitride is provided at a predetermined location on the upper surface of the second substrate 2. Ohmic contact layers 15 and 16 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 14 in the channel length direction and on the upper surface of the semiconductor thin film 13.

The data signal line 3 including the drain electrode 6 is provided at a predetermined position on the upper surface of one ohmic contact layer 15 and the upper surface of the gate insulating film, and the source electrode 7 is provided on the upper surface of the other ohmic contact layer 16. The overcoat film 17 made of silicon nitride is provided on the entire upper surface. A contact hole 18 is provided in a portion of the overcoat film 17 corresponding to a predetermined portion of the source electrode 7. Overcoat film 17
The pixel electrode 1 is connected to the source electrode 7 via a contact hole 18 at a predetermined location on the upper surface of the pixel electrode 1. Here, the thin film transistor 4 is constituted by the gate electrode 5, the gate insulating film 12, the semiconductor thin film 13, the channel protective film 14, the ohmic contact layers 15, 16, the drain electrode 6, and the source electrode 7.

Next, a method of manufacturing a part of the liquid crystal display device will be described with reference to FIGS. First,
As shown in FIG. 3, the scanning signal line 2 including the gate electrode 5 is formed at a predetermined location on the upper surface of the glass substrate 11, and the auxiliary capacitance electrode 8a is provided at another predetermined location on the upper surface of the glass substrate 11. The capacitance line 8 is formed. next,
A gate insulating film 1 made of silicon nitride over the entire upper surface of the glass substrate 1 including the scanning signal lines 2 and the auxiliary capacitance lines 8
2. Semiconductor thin film 13 made of intrinsic amorphous silicon
Protective film forming film 14 made of silicon and silicon nitride
a is continuously formed.

Next, a photoresist film 21 for forming a channel protective film is formed on a predetermined portion of the upper surface of the film 14a for forming a channel protective film on the gate electrode 5 by using a back surface exposure using the gate electrode 5 as a mask and an exposure mask. It is formed by the exposed surface exposure. In this case, the photoresist film 21 is exposed on the back surface using the gate electrode 5 as a mask, that is, formed by self-alignment, and both end edges of the photoresist film 21 in the row direction in FIG. At the same position or slightly inside (due to light wraparound). In addition, the position of both ends in the column direction in FIG. 1 of the photoresist film 21 is determined by the surface exposure using the exposure mask.

Next, the channel protective film forming film 14a is etched using the photoresist film 21 as a mask.
As shown in FIG. 4, a channel protective film 14 is formed below the photoresist film 21. In this case, since both end edges of the photoresist film 21 in the row direction in FIG. 1 are located at the same positions as or slightly inside of both end edges of the gate electrode 5 in the same direction, the row of the channel protection film 14 in FIG. Both ends in the direction, that is, the channel length direction are located at the same positions as the both ends of the gate electrode 5 in the same direction or slightly inside. Therefore, when forming the channel protective film 14,
It is possible to prevent misalignment in the row direction. Next, the photoresist film 21 is peeled off.

Next, as shown in FIG. 5, an ohmic contact layer 16 made of n-type amorphous silicon and a metal film 23 made of chromium are continuously formed on the entire upper surface of the semiconductor thin film 13 including the channel protective film 14. I do. Next, photoresist films 24a and 24b are formed at predetermined positions on the upper surface of the metal film 23, respectively. In this case, the photoresist film 24a is connected to the data signal line 3 including the drain electrode 6.
And a photoresist film 24b.
Is for forming the source electrode 7. Next, the metal film 2 is formed using the photoresist films 24a and 24b as a mask.
6, the data signal line 3 including the drain electrode 6 is formed below the photoresist film 24a, and the source electrode 7 is formed below the photoresist film 24b, as shown in FIG.

Here, as shown in FIG. 1, the arrangement direction of the gate electrode 5, the drain electrode 6, and the source electrode 7 of the thin film transistor 4, that is, the channel length direction is set as the row direction. 6 and the data signal line 3 have a linear shape extending in the column direction, which is the same direction as the arrangement direction of the data signal line 3. For this reason, the shape of the groove between the photoresist films 24a and 24b formed on the drain electrode 7 and the source electrode 7 is also a linear shape extending in the column direction which is the same direction as the arrangement direction of the data signal lines 3. . As a result, when the metal film 23 is wet-etched using the photoresist films 24a and 24b as a mask, the etchant is less likely to stay in the groove, and a gap between the data signal line 3 including the drain electrode 6 and the source electrode 7 is formed. It is possible to prevent short-circuiting due to processing defects from occurring. In this case, if the channel length, that is, the distance between the drain electrode 6 and the source electrode 7 is increased to some extent, the etchant can be made more difficult to stay in the groove.

Next, the photoresist films 24a, 24b,
When the ohmic contact layer 16 and the semiconductor thin film 13 are dry-etched using the drain electrode 6 and the source electrode 7 as masks, as shown in FIG.
One ohmic contact layer 15 is formed below, and the other ohmic contact layer 16 is formed below the source electrode 7. In addition, both ohmic contact layers 15, 16
The semiconductor thin film 13 remains below and below the channel protective film 14. Next, the photoresist films 24a and 24b are peeled off.

Next, as shown in FIG. 2, an overcoat film 17 made of silicon nitride is formed on the entire upper surface of the gate insulating film 12 including the thin film transistor 4 and the like. next,
A contact hole is formed in a portion of the overcoat film corresponding to a predetermined portion of the source electrode. next,
The pixel electrode 1 is formed at a predetermined position on the upper surface of the overcoat film 17.
Is formed by connecting to the source electrode 7 via the contact hole 18.

In the liquid crystal display device obtained as described above, as described above, the back surface exposure using the photoresist film 21 for forming the channel protective film shown in FIG. The surface protection layer 14 is formed by the above-described surface exposure, and the both ends of the channel protective film 14 in the row direction, that is, the channel length direction in FIG. 1 are located at the same positions as the two ends of the gate electrode 5 in the same direction or slightly inside. In FIG. 1, the distance between the right side of the channel protection film 14 and the right side of the gate electrode 4 is the same for the odd rows and the even rows. As a result, the overlapping area between the gate electrode 5 and the source electrode 7 at the above-mentioned interval is the same between the odd-numbered rows and the even-numbered rows, and is the same.
Between the odd-numbered rows and the even-numbered rows. Further, since the data signal line 3 also serves as the drain electrode 7, the aperture ratio can be improved as compared with the case where the drain electrode 7 is formed to protrude from the data signal line 3.

In the above embodiment, the case where the present invention is applied to a liquid crystal display device having a delta arrangement has been described. However, the present invention is not limited to this, and may be applied to a liquid crystal display device having another arrangement such as a stripe arrangement. it can. In the above embodiment, the pixel electrode 1 is formed on the overcoat film 17 covering the thin film transistor 4, but the pixel electrode is formed on the gate insulating film, and the thin film transistor and the pixel electrode are covered with the overcoat film. It is also applicable in the case of a structure.

[0033]

As described above, according to the present invention, since the channel length defined between the drain electrode and the source electrode of the thin film transistor is arranged in the row direction, the source electrode and the drain electrode and the drain electrode near the source electrode are arranged. The shape of the groove between the data signal line and the data signal line becomes a straight line extending in the column direction, which is the same direction as the arrangement direction of the data signal line. As a result, processing defects occur between the data signal line including the drain electrode and the source electrode. Short circuit is less likely to occur.

[Brief description of the drawings]

FIG. 1 is a transmission plan view of a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line XX in FIG. 1;

FIG. 3 is a sectional view of an initial manufacturing process when manufacturing the liquid crystal display device shown in FIGS. 1 and 2;

FIG. 4 is a sectional view of the manufacturing process following FIG. 3;

FIG. 5 is a sectional view of the manufacturing process following FIG. 4;

FIG. 6 is a sectional view of the manufacturing process following FIG. 5;

FIG. 7 is a sectional view of the manufacturing process following FIG. 6;

FIG. 8 is a partially transparent plan view of an example of a conventional liquid crystal display device.

FIG. 9 is a sectional view taken along the line YY of FIG. 8;

FIG. 10 is a sectional view of an initial manufacturing process when manufacturing the liquid crystal display device shown in FIGS. 8 and 9;

FIG. 11 is a sectional view of the manufacturing process continued from FIG. 10;

FIG. 12 is a sectional view of the manufacturing process following FIG. 11;

FIG. 13 is a sectional view of the manufacturing process continued from FIG. 12;

FIG. 14 is a sectional view of the manufacturing process following FIG. 13;

[Explanation of symbols]

 Reference Signs List 1 pixel electrode 2 scanning signal line 3 data signal line 4 thin film transistor 5 gate electrode 6 drain electrode 7 source electrode 8 auxiliary capacitance line 14 channel protective film

Continued on the front page F-term (reference) 2H092 JA26 JA29 JA38 JA42 JA43 JA47 JB13 JB23 JB32 JB33 JB38 JB51 JB57 JB63 JB69 KA05 KA07 KA12 KA24 KB14 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA35 MA37 MA41 NA02 AA NAA AA48 AA55 BA03 BA43 CA19 CA20 DA13 DB04 EA04 EA05 EA10 EB02 FA01 FB12 FB14 FB15 GB10 5F110 AA26 CC07 DD02 FF03 GG02 GG15 GG35 HK04 HK09 HK16 HK21 NN12 NN24 NN72 NN77 QQ09 QQ12

Claims (6)

[Claims] 1. A pixel electrode is disposed in a region surrounded by a scanning signal line extending in a row direction and a data signal line extending in a column direction, and a notch provided in the pixel electrode is provided. A thin film transistor is arranged, a gate electrode of the thin film transistor is connected to the scanning signal line, a drain electrode arranged on one side of the gate electrode is connected to the data signal line, and arranged on the other side of the gate electrode. In the liquid crystal display device in which the source electrode is connected to the pixel electrode, the channel length defined by the drain electrode and the source electrode of the thin film transistor is arranged in the row direction, and the channel protection provided on the gate electrode is provided. The two end edges in the channel length direction of the film are formed by self-alignment of the gate electrode. Liquid crystal display. 2. The invention according to claim 1, wherein an edge of said data signal line on a side facing said thin film transistor is a linear shape extending in a column direction, and said linear edge is said drain. A liquid crystal display device, which also serves as an electrode. 3. The invention according to claim 2, wherein a width of a portion of the data signal line facing the thin film transistor is substantially the same as a width of a portion where the data signal line intersects with the scanning signal line. A liquid crystal display device, wherein the width of the data signal line between the thin film opposing portion and the scanning signal line intersection is larger than the width of the data signal line. 4. The data protection circuit according to claim 3, wherein an edge of the channel protection film on the drain electrode side is provided between the portion of the data signal line facing the thin film transistor and the intersection of the scanning signal line. A liquid crystal display device which is located inside the width of a signal line. 5. A liquid crystal display device according to claim 1, wherein said pixel electrodes are arranged in a delta arrangement, and said data signal lines are arranged meandering in a column direction. . 6. The liquid crystal display device according to claim 5, wherein the thin film transistors are arranged symmetrically in the column direction in odd rows and even rows.