JP2002093063A - Phase calculating method, phase calculating device method of testing for the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase calculating device which deals with an input signal of a high frequency and can lessen the influence of noise. SOLUTION: An amplifier circuit 21 is a high-gain amplifier which is previously highly set with a gain, amplifies the input signal in and outputs the signal SG12 obtained by adding correction voltage SG11 to this amplified signal to a comparator 22. The cooperator 22 is previously set with a prescribed decision range (range) set by the first threshold on a high-potential side and the second threshold on a low-potential side, samples the output signal SG12 of the amplifier circuit 21 in response with a clock signal CLK, compares the sampling level and the first and second thresholds and outputs a decision signal SG13 of many values (three values in this embodiment).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for calculating a phase in a recording (information) reproducing apparatus, an apparatus therefor, and a test method for the apparatus.

[0002] A recording / reproducing apparatus reads data from a recording medium such as a magnetic disk, and outputs a reproduced signal (read data) obtained by performing various processes on the data. The recording / reproducing apparatus calculates phase data from the read data, and performs phase servo for positioning the read head based on the phase data.

In recent years, in a recording / reproducing apparatus, the frequency of read data (input signal) has been increased by increasing the density of the recorded data, the reading speed, and the driving speed of the medium. Higher speed is required. In addition, the power supply voltage has been reduced for the purpose of lowering the power consumption of the apparatus and lowering the temperature of the apparatus. As a result, the phase calculation circuit that calculates the phase data is easily affected by noise, and thus it is necessary to reduce the effect of noise.

[0004]

2. Description of the Related Art FIG. 26 shows a phase calculation circuit in a data reading device for reading data from a recording medium such as a magnetic disk.

The AGC circuit 1 receives data read from a recording medium via a read head (not shown) as an analog input signal in. AGC circuit 1
Has a gain set based on an AGC control voltage SG1 output from a D / A converter (DAC) 2, amplifies an input signal in based on the gain, and outputs an output signal to a low-pass filter (LPF) 3. SG2 is output.

LPF3 is an output voltage SG of AGC circuit 1.
2, an unnecessary high-frequency component is removed, and an output signal SG3 including a fundamental wave component is output to an A / D converter (ADC) 4.
The A / D converter 4 converts the analog output signal SG3 output from the LPF 3 into a digital output signal SG4,
Output to the FT operation circuit 5.

The DFT operation circuit 5 converts the digital output signal SG4 of the A / D converter 4 into a DFT (Discrete Fourier Tra
nsform) and outputs the calculated phase data PD.
This phase data PD is used for servo control of the reading position by the reading head.

[0008] The output signal SG 4 of the A / D converter 4 is also input to a gain calculation circuit 6. The gain calculation circuit 6 calculates A
The output signal SG4 of the / D converter 4 is compared with a target value, and the digital output signal SG5 obtained by integrating the error component is converted to a D / A signal.
Output to converter 2. This target value is a value that causes the output signal SG3 of the LPF 3 to have a substantially full range with respect to the input level of the A / D converter 4.

The D / A converter 2 converts the digital output signal SG5 of the gain calculation circuit 6 into an analog signal,
The signal is output to the C circuit 1 as the AGC control voltage SG1. As described above, the gain of the AGC circuit 1 is optimized by the gain control loop that feeds back the control voltage SG1 based on the output signal SG2 of the AGC circuit 1, and the signal SG3 having an amplitude corresponding to the input range of the A / D converter 4 is obtained. I'm trying to get

The A / D converter 4, the DFT operation circuit 5, the gain calculation circuit 6, etc. operate based on the clock signal CLK generated by the PLL circuit 7. Thus, the phase calculation circuit amplifies the input signal in, which is data read from the recording medium, to a predetermined amplitude, and extracts a signal SG3 including a fundamental wave component from the amplified signal SG2. Further, the digital signal SG4 obtained by converting the signal SG3 is
The phase data PD calculated by the FT operation is output.

[0011]

However, when the medium is rotated at a high speed in order to increase the density of the recording medium and to increase the reading speed, an input signal in having a high frequency is input. Therefore, it is necessary to make analog circuits such as the AGC circuit 1, the LPF 3, and the D / A converter 2 compatible with high frequencies. However, an analog circuit corresponding to a high frequency itself is complicated and sophisticated, and it has been difficult to create an analog circuit. Also, in order to reduce the consumption and prevent the equipment from becoming hot,
It is necessary to lower the power supply voltage. However, there is a problem that the reduction of the power supply voltage is susceptible to noise.

As shown in FIG. 27, the system LS
The microcomputer 12 and the DSP 13 are mounted on one semiconductor chip 10 together with the above-described phase calculation circuit 11 by the I method. However, the use of a system LSI requires the microcomputer 12
The analog signal (in, S,
G1, SG2, and SG3) increase the noise, which causes a problem that the phase calculation circuit 11 cannot be implemented as a system.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a phase calculation method, a phase calculation apparatus, and a phase calculation method capable of responding to a high-frequency input signal and reducing the influence of noise. To provide a test method.

[0014]

In order to achieve the above object, according to the first and third aspects of the present invention, an input signal is amplified with a high gain, and the amplified signal is sufficiently lower than its peak level. At least one or more decision levels are converted into a multivalued digital signal, and the phase of the fundamental wave component included in the amplified signal is calculated based on the digital signal.

According to a second aspect of the present invention, an input signal is amplified so as to exceed a predetermined determination range, and the amplified signal is converted into at least a binary digital signal based on the determination range. The phase of the fundamental wave component included in the amplified signal is calculated based on the digital signal.

By doing so, the analog circuit only needs to amplify the fundamental wave component of the signal, and the circuit configuration is simple and can be easily realized. In addition, by setting the peak level of the amplified signal sufficiently higher than the judgment level and the judgment range, the influence of noise can be reduced.

The input signal is a signal of a different phase read from a plurality of areas in the phase calculation area recorded on the recording medium, as in the invention of claim 5, and the calculation circuit is configured to output the input signal. The result of the DFT operation of the fundamental wave component is output.

According to a sixth aspect of the present invention, a judgment signal from the comparator is input, and a center value of an output signal of the amplifier circuit substantially matches a center value of a range of the comparator based on the judgment signal. An intermediate value correction circuit that outputs a correction signal generated so as to cause the correction signal to be converted into an analog signal, and a D / A converter that outputs a correction voltage to the amplifier circuit. The correction voltage is added to the signal and output. Thereby, the offset of the amplifier circuit can be easily corrected.

The intermediate value correction circuit counts the maximum value and the minimum value of the determination signal from the comparator, respectively, and matches them when the two count values are different. Generate a correction signal. This facilitates generation of the correction signal.

According to the present invention, a judgment signal from the comparator is input, and a data string to be corrected consisting of the judgment signal is judged as a data string expected from the data string to be corrected. A data string correction circuit for outputting a signal obtained by correcting the determination signal based on the data string to the calculation circuit; Thereby, the data string can be easily corrected.

The data string correction circuit stores a plurality of data strings that can be expected as known data strings and determines whether or not the corrected data string contains a predetermined value. Is determined, and one of the plurality of known data strings is selected based on the determination result, and the corrected data string is corrected using the selected data string. This makes it possible to stably correct the data string.

The invention described in claim 10 is the invention according to claims 3 to 9
Is connected to a digital signal generator, and a rectangular wave generated by the generator is supplied as the input signal to perform an operation test of the phase calculation. This eliminates the need for expensive AWGs (arbitrary generators) and SGs (signal generators) for the test.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block circuit diagram of the phase calculation circuit of the present embodiment.

The phase calculation circuit 20 includes an amplifier circuit (Am
p) 21, a comparator 22, a correction circuit 23, a D / A converter (DAC) 24, a DFT operation circuit 25, and a PLL circuit 26.

The amplifier circuit 21 receives data read from a recording medium via a read head (not shown) as an analog input signal in. Amplifier circuit 2
Reference numeral 1 denotes a high-gain amplifier whose gain (gain) is previously set high, amplifies an input signal in, and adds a signal SG12 obtained by adding a correction voltage SG11 to the amplified signal to a comparator 2
Output to 2.

In the comparator 22, a predetermined judgment range (range) set by a first threshold value on the high potential side and a second threshold value on the low potential side is set in advance, and sampling from the PLL circuit for sampling is performed. A clock signal CLK is supplied. The comparator 22 samples the output signal SG12 of the amplifier circuit 21 in response to the clock signal CLK, compares the sampling level with the first and second thresholds, and outputs a multi-level (three-level in this embodiment). Judgment signal SG
13 is output.

When the level of the output signal SG12 is equal to or higher than the first threshold value, the comparator 22 of this embodiment outputs a judgment signal SG13 having a value of "1". When the signal SG12 is between the first threshold value and the second threshold value, the comparator 22 determines that the determination signal S is “0”.
G13 is output. Further, the comparator 22 outputs the signal S
If G12 is equal to or smaller than the second threshold value, the judgment signal SG13 of "-1" is output.

The correction circuit 23 has a center value correction function and a data string correction function. The center value correction function is provided by the comparator 2
This is a function for maintaining the symmetry of the second output signal SG13.

When the correction circuit 23 finds asymmetry in the output signal SG13 of the comparator 22, it outputs a correction signal SG14 generated to correct the asymmetry to the D / A converter 24. The D / A converter 24 outputs the correction signal S
G14 is digital-to-analog converted to a correction voltage SG11 and output to the amplifier circuit 21. In this way, an offset is given to the output signal SG12 of the amplifier circuit 21 so that the center value of the amplitude substantially matches the center value of the first and second threshold values of the comparator 22.

Note that a possible change in the center value is sufficiently slow in comparison with the frequency of the output signal SG12 for performing the change. Therefore, it is not necessary to operate the D / A converter 24 at high speed.
The D / A converter that operates at a low speed has a simpler circuit configuration and consumes less current than the D / A converter 2 that requires a high-speed operation.

The data string correction function of the correction circuit 23 is as follows.
This is a function for correcting an error generated in the output signal SG13 of the comparator 22 due to noise or waveform distortion.
The data sequence of the output signal SG13 from which the phase servo pattern has been read has a repetitive pattern that repeats at the cycle of the fundamental wave. The data sequence of this pattern includes a data sequence of a predetermined number of consecutive codes “1” and a data sequence of the same number of consecutive codes “−1”.

Accordingly, the correction circuit 23 monitors the consecutive numbers of the codes "1" and "-1", and if they do not match, corrects the data string so that they match, and corrects each of the corrected data strings. The bits are sequentially output to the DFT operation circuit 25 as a signal SG15.

The output signal SG12 of the comparator 22
The data string composed of a plurality of bits may or may not include the code "0", and the expected data string differs depending on the case. Therefore, the expected data columns include
A first correction data string including the code “0” and a second correction data string not including the code “0” are set in advance.

The correction circuit 23 outputs an output signal SG15 having the same sign as the input signal SG13 to the DFT operation circuit 25 when the data string does not need to be corrected. When the correction circuit 23 determines that the data string needs to be corrected,
The output signal SG15 obtained by correcting the input signal SG13 is
Output to the FT operation circuit 25.

The DFT operation circuit 25 performs a DFT operation on the output signal SG15 of the correction circuit 23 to calculate phase data.
The phase difference data PD calculated from the plurality of phase data is output. That is, the DFT operation circuit 25 includes a register for storing the calculated plurality of phase data, and outputs the phase difference data PD having a difference between the phase of the reference waveform and the phase of the waveform. This phase difference data PD is used for servo control of the position of the read head, the rotation speed of the recording medium, and the like.

FIG. 2 shows the output signal SG12 of the amplifier circuit 21.
FIG. 4 is a waveform diagram showing a relationship between the threshold value of the comparator 22 and the threshold value. FIG. 3 is a waveform diagram showing the determination signal SG13 of the comparator 22. In FIG. 2, the sampling points in the comparator 22 are given the same symbols as in FIG. 3 at the same timing to make it easier to understand the correspondence.

A plurality (four) of single frequency signals SG12a to SG12d shown in FIG. 2 are signals read from one of a number of phase detection areas recorded on a recording medium. A large number of phase detection areas are respectively included in servo areas that are partially recorded on each track of the recording medium. The single frequency is used for easy understanding.

The phase detection area includes four fields,
Each field records a pattern that is phase-shifted corresponding to the position of the track at every predetermined clock pitch determined by the reference clock. Signals obtained by reading and amplifying these patterns are SG12a to SG12d.

On the other hand, the comparator 22 shown in FIG.
The full range is set to a value (0.2, -0.2) sufficiently lower than the peak level of each of the signals SG12a to SG12d. These values are the first and second
Is the threshold value.

The comparator 22 outputs signals SG12a to SG12a
The sampling level of the SG 12d is compared with the first and second thresholds, and as shown in FIG. 3, judgment signals SG13a to SG13d having codes based on the comparison result are output.

These judgment signals SG13a to SG13d
Has a fundamental wave phase difference substantially equal to the fundamental wave phase difference of the signals SG12a to SG12d. Therefore, the phase calculation circuit 20 of FIG. 1 calculates the phase difference between the fundamental waves of the determination signals SG13a to SG13d, thereby obtaining the signals SG12a to SG1.
It is possible to obtain a result substantially equal to the case where the phase difference of the 2d fundamental wave is calculated.

The decision signals SG13a to SG13d have three values (-1, 0, 1), and these values are represented by 2-bit digital values. Therefore, the correction circuit 23 and the DFT
The arithmetic circuit 25 only needs to be configured to be able to operate with a small number of bits, thereby reducing the circuit scale and the current consumption.

Next, the configuration and operation of the correction circuit 23 will be described with reference to FIGS. FIG.
3 is a block circuit diagram of a center value correction circuit 23a included in the correction circuit 23. FIG.

The amplifier circuit 21 includes resistors R1 to R3 and an operational amplifier OP1. The operational amplifier OP1 receives input signals in and D via first and second resistors R1 and R2.
The output signal SG11 of the / A converter 24 is input, and the output signal SG12 is fed back via the third resistor R3.

The center value correction circuit 23a includes first and second counters 31 and 32 and a judgment circuit 33. The determination signal SG13 of the comparator 22 in FIG. 1 and the enable signal EN are input to the first and second counters 31 and 32. The enable signal EN is a signal indicating a period during which the first and second counters 31 and 32 perform a counting operation, and is input from a control circuit (not shown). First and second
The counters 31 and 32 perform a counting operation for a period that is an integral multiple of the cycle of the output signal SG13.

The first counter 31 counts the value “1” of the data of the determination signal SG13, and the second counter 32
Counts the value "-1". First and second counters 3
1 and 32 output the count value to the determination circuit 33 after a predetermined count period ends.

The determination circuit 33 includes the first and second counters 3
Comparing the count values of 1, 32, and when the first count value of the value “1” is larger than the second count value of the value “−1”,
The value of the correction signal SG14 is increased according to the difference. Conversely, when the first count value is smaller than the second count value, the determination circuit 33 reduces the value of the correction signal SG14 according to the difference.

As a result, the level of the correction voltage SG11 output from the D / A converter 24 changes. The offset voltage of the amplifier circuit 21 rises and falls due to the correction voltage SG11, and corrects the center value of the signal SG12.

When the output signal SG13 is sampled at eight samples per cycle, the data sequence that can be expected to be output is the first data sequence D1 not including "0" or "0" as shown in FIG. Any of the included second data strings D2. However, when the center value is shifted, the data sequence becomes, for example, the data sequence D3 or D4 shown in FIG. The data string D3 does not include “0”, and the number of consecutive “1” is smaller than the number of consecutive “−1”. The data string D4 includes “0” and “1”
Is less than the number of consecutive “−1”.

As described above, the continuous number of "1" and "-1" are counted, and the output signal S is counted by comparing them.
It is determined whether G13 is the expected data sequence. And
Amplifier circuit 2 based on the difference between the number of consecutive “1” and “−1”
By adjusting the offset of 1, the center value of the output signal SG13 is corrected, and an expected data string is obtained.

FIG. 5 is a block circuit diagram of the data string correction circuit 23b included in the correction circuit 23. The data string correction circuit 23b includes a counter 34, a determination circuit 35, and a correction circuit 36.

The counter 34 includes the comparator 2 shown in FIG.
2 and the enable signal EN are input. The enable signal EN is a signal indicating a period during which the counter 34 performs a count operation, and is input from a control circuit (not shown). The counter 34 performs a counting operation for a period that is an integral multiple of the cycle of the output signal SG13. The counter 34 counts the value “0” in the data of the determination signal SG13, and outputs the count value to the determination circuit 35 after a predetermined count period ends.

The judgment circuit 35 stores a predetermined judgment value M, compares the judgment value M with the count value of the counter 34, and judges whether or not the data string contains "0". Then, the determination circuit 35 outputs the result of the determination to the correction circuit 36.

The correction circuit 36 stores the expected data strings D1 and D2 in FIG. Note that stored data strings D1,
D2 is the number of bits necessary for correcting the data string of the input determination signal SG13 (for example, in the case of 8 samples per cycle,
If the data sequence to be corrected is 2 cycles (16 bits), then 3
(24 bits) is stored.

When the data string does not include "0" based on the result of the determination by the determination circuit 35, the correction circuit 36 shown in FIG.
The data sequence D1 is used. When the data sequence contains "0", the data sequence D2 is used, and the determination signal S is used in accordance with the procedure shown in FIG.
The data string of G13 is corrected. Then, the correction circuit 36
Outputs each bit of the corrected data string as a signal SG15.

FIG. 7 is a flowchart of a data string correction process performed by the correction circuit 36. First, in step 41, the correction circuit 36 determines the data sequence D to be corrected.
A is shifted by one bit. Next, the correction circuit 36 calculates the absolute value of the difference between the data sequence DA and the correction data sequence (the data sequence D1 or D2 in FIG. 6) for each bit in step 42, and in step 43, calculates the absolute value. Find the total value of

In step 44, the correction circuit 36
It is determined whether the total value obtained in step 43 is equal to or greater than a predetermined value. The predetermined value is set to determine the likelihood of the data string DA (how close each bit of the data string DA is to the sequence of the bits of the correction data string), and is set to “3” in the present embodiment. Have been. That is,
As the total value obtained in step 43 is smaller, the data string D
It can be said that A is close to the correction data string D2.

Therefore, when the total value is larger than the predetermined value, the correction circuit 36 determines that the data string DA is not similar to the correction data string, and returns to step 41 to return to the data string DA.
Is further shifted by one bit.

On the other hand, when the total value is equal to or smaller than the predetermined value in step 44, the correction circuit 36
The arrangement of the bits of the correction data string corresponding to A is set as a correction data string, and the correction data string is output instead of the data string DA.

As described above, the correction circuit 36 outputs the data string D
A total value of the bits A and the bits of the correction data string is obtained, and when the total value is equal to or less than a predetermined value, the correction data string at that time is obtained as a correction data string.

The operation of the correction circuit 36 will be described with reference to FIGS.
0 will be described. Now, the data sequence D shown in FIG.
Correct A1. In this case, since the data sequence DA1 includes three “0” s, the correction circuit 36 determines that the data sequence D2 in FIG.
Is a correction data string D2a shown in FIG.

First, as shown in FIG. 8C, the correction circuit 36 calculates the absolute value of the difference between each bit of the data sequence DA1 and the correction data sequence D2a for each bit, and obtains the total value thereof. . In this case, the total value is “15”, which is larger than the predetermined value, so that the correction circuit 36 shifts the data string DA1 by one bit as shown in FIG. In this case, since the total value is "23", which is larger than the predetermined value, the correction circuit 36 further shifts the data string DA1 by one bit.

FIG. 9A shows a data sequence DA1 shifted by 2 bits, and the total value at this time is "25". FIG.
(B) shows the data string DA1 shifted by 3 bits, and the total value at this time is "25". FIG. 9C shows the data sequence DA1 shifted by 4 bits, and the total value at this time is “17”. These sums are all greater than a predetermined value.

FIG. 10A shows a data string DA1 shifted by 5 bits, and the total value at this time is "9". FIG.
0 (b) indicates a data string DA1 shifted by 6 bits,
The total value at this time is “1”. The total value at this time is equal to or smaller than a predetermined value, and the data sequence DA1 when the data is shifted by 6 bits is very similar to the correction data sequence D2a.

Accordingly, as shown in FIG. 10C, the correction circuit 36 obtains a correction data sequence DA2 composed of a bit sequence corresponding to the data sequence DA1 shifted by 6 bits, and converts each bit of the data sequence DA2 to the signal SG15. Output as

Next, the operation of the phase calculation circuit 20 of FIG. 1 configured as described above will be described. FIG. 11 to FIG. 13 are explanatory diagrams of the phase calculation by the conventional method. FIG. 13 shows FIG.
6 shows an output signal SG3 from the LPF 3 of No. 6, in which four signals SG3a to SG3d having different phases used for phase servo are superimposed and displayed. FIG. 11 shows a value obtained by sampling one cycle of these eight times, that is, the output signal SG4 of the A / D converter 4 in FIG. 26 for each of the signals SG3a to SG3d.

The phase of the input signal when eight samples are taken in one cycle is

[0068]

(Equation 1) Is required. On the other hand, the phase of the fundamental wave is only the first term of the above equation (1),

[0069]

(Equation 2) Is required.

When the above equation (2) is expanded,

[0071]

(Equation 3) And,

[0072]

(Equation 4) Is obtained.

The DFT operation circuit 5 shown in FIG. 26 calculates the signals SG3a to SG3 from the real axis and the imaginary axis in the equation (4).
The phase of the fundamental wave of d is calculated. FIG. 12 shows the progress of the calculation in equation (4). In FIG. 12, the phase (P
1) are the signals SG3a to SG3S obtained by the above equation (4).
G3d is the phase of the fundamental wave. The phase difference (PD1) is the phase difference between the fundamental waves of each signal (the first and second signals SG3a, SG3).
3b, the phase difference between the second and third signals SG3b and SG3c, and the phase difference between the third and fourth signals SG3c and SG3d). The phase difference (PD2) is a phase difference between the second to fourth signals SG3b to SG3d with respect to the first signal SG3a.

FIGS. 14 to 16 are explanatory diagrams of the phase calculation according to the present embodiment. FIG. 16 shows the comparator 22 shown in FIG.
And three signals SG13a to SG13 having different phases used for phase servo.
13d (same as in FIG. 3) is superimposed and displayed. FIG. 14 shows the values of the eight samples in one cycle, that is, the output data of the comparator 22 in FIG.
This is shown for each G13d.

The DFT operation circuit 25 of FIG. 1 calculates the signals SG13a to SG13 from the real axis and the imaginary axis in the above equation (4).
The phase of the fundamental wave of 13d is calculated. FIG. 12 shows the progress of the calculation in equation (4). In FIG. 12, the phase (P1) is the signal SG13 obtained by the above equation (4).
a to SG13d are the phases of the fundamental waves. Phase difference (PD
1) is a phase difference between the fundamental waves of each signal (the first and second signals SG).
13a, SG13b, the second and third signals SG1
3b, the phase difference between SG13c, the third and fourth signals SG13
c, phase difference of SG 13d). Phase difference (PD2)
Are the second to fourth signals SG1 with respect to the first signal SG13a.
3b to 13d are phase differences.

The phase difference (PD2) obtained as shown in FIG.
In contrast, the phase difference shown in FIG. 15 has an error, but such an error in the value does not affect the phase servo of the read head. As described above, the phase calculation circuit 20 calculates the phase difference between the signals SG13a to SG13d by using the DFT calculation circuit 25 that handles a small number of bits and has a simplified circuit configuration.

By increasing the number of samples in one cycle,
A highly accurate phase calculation result can be obtained. Also, by increasing the number of bits of the output signal of the comparator 22 in FIG. 1, a highly accurate phase calculation result can be obtained.

For example, first and second comparators 22
In addition to the threshold values TH1 and TH2 (0.2, -0.2) (see FIG. 2), a third threshold value TH3 (= 0) is set. The comparator 22 sets the value “0” when the sampling level of the input signal SG12 is lower than the second threshold TH2, and sets the value “0” when the sampling level is between the second and third thresholds TH2 and TH3. "1" is set to the third and first threshold values TH
3, if it is between TH1, the value "2"
If the value is larger than H1, the value "3" is output. That is, the comparator 22 is configured to output a quaternary signal. FIGS. 17 to 19 show the phase calculation in the case of such a configuration.

FIG. 19 shows a quaternary determination signal SG13 output from the comparator 22, in which four signals SG13a to SG13d having different phases used for phase servo are displayed in an overlapping manner. FIG. 17 shows the sampling level for one cycle, that is, the output of the comparator.
In this way, it is possible to obtain a phase calculation result that is closer to the calculation result of FIG. 12, that is, a phase calculation result with higher accuracy than the calculation result of FIG.

Next, an operation test of the phase calculation circuit 20 configured as described above will be described. As shown in FIG. 20, the phase calculation circuit 20 (phase calculation device, system LSI)
It is connected to the digital tester 51 during the operation test. The digital tester 51 includes first and second drivers 52 and 53. The first driver 52 generates a rectangular waveform source waveform shown in FIG. 21 and the second driver 53 generates a clock signal CLK as a reference for phase calculation.

The phase calculation circuit 20 can calculate the phase of the signal even in the data sequence D1 shown in FIG. Therefore, the operation test of the phase calculation circuit 20 can be performed by using the digital tester 51 having the drivers 52 and 53 that generate the rectangular wave in FIG. 20, and the cost for the test is reduced. This is because the operation test of the conventional phase calculation circuit requires a waveform generator that supplies a sine wave, and such a waveform generator is expensive, and the digital tester 51 is inexpensive.

As described above, the present embodiment has the following advantages. (1) The amplifier circuit 21 is a high gain amplifier in which the gain (gain) is set high in advance, amplifies the input signal in, and adds a correction voltage SG11 to the amplified signal to obtain a signal S.
G12 is output to the comparator 22. Comparator 2
2, a predetermined determination range (range) set by a first threshold value on the high potential side and a second threshold value on the low potential side is set in advance, and the amplifier circuit 2 responds to the clock signal CLK.
One output signal SG12 is sampled, and the sampling level is compared with the first and second thresholds to output a multi-valued (three-valued in this embodiment) determination signal SG13. As described above, since the amplifier circuit 21 only amplifies the input signal in, high-speed operation of the analog circuit portion is not required, and the analog circuit can be easily realized.

(2) The amplifier circuit 21 includes the comparator 2
The input signal in is amplified by a gain set so as to shake out the input range of No. 2. By setting the peak level of the amplified signal to be larger than the judgment level and the judgment range in this way, even if noise is mixed in the analog signal, the judgment result of the comparator 22 is less affected by the noise. Becomes easier.

(3) The comparator 22 outputs the input signal SG
12 is converted into a ternary determination signal SG13. As described above, since the phase difference can be calculated by inputting a small number of bits, the circuit configuration of the DFT operation circuit 25 is simplified, and the phase difference data PD can be obtained without increasing the circuit scale.

(4) The center value correction circuit 23a counts the number of “1” and “−1” of the determination signal SG13 from the comparator 22 and compares them to obtain the output signal S.
It is determined whether G13 is the expected data sequence. And
The correction signal S generated based on the difference between the numbers "1" and "-1" so that the center value of the output signal SG12 of the amplifier circuit 21 substantially matches the center value of the input range of the comparator 22.
G14 is output. The D / A converter 24 outputs a correction voltage SG11 obtained by converting the correction signal SG14 into an analog signal to the amplifier circuit 21, and the amplifier circuit 21 outputs the correction voltage SG11.
Is output as a signal SG12. As a result, by adjusting the offset of the amplifier circuit 21, the output signal SG
Thus, the expected data sequence can be easily obtained by correcting the center value of the thirteen.

(5) The D / A converter 24 includes the amplifier circuit 2
The operation may be performed when the offset of 1 needs to be corrected, and since the correction does not depend on the frequency of the input signal in, it is not necessary to operate at a high speed, and the configuration is simplified.

(6) The data string correction circuit 23b outputs the data string DA based on the judgment signal SG13 from the comparator 22.
And the total value of the bits of the correction data strings D1 and D2 is obtained. When the total value is equal to or less than a predetermined value, the correction data string at that time is obtained as a correction data string. As a result, a correction data string can be easily obtained without requiring a complicated operation.

The above embodiment may be changed to the following mode. The correction circuit 23 of the above-described embodiment corrects the central value with the signal read for phase calculation (the signal read from the phase detection area of the recording medium) to correct the center value.
Is generated, but the center value may be corrected by the servo mark.

A plurality of servo areas are partially recorded on each track of the recording medium, and each servo area includes an R / W recovery area, a servo mark area, and a phase detection area. FIG. 22 shows an input signal in when the recorded content of such a servo area is read. The input signal in shown in FIG.
It is actually a Lorentz waveform, but for simplicity, s
Display in waveform.

The input signal in (servo mark) from which the recorded content of the servo area is read has a non-amplitude (or small amplitude) waveform. When the waveform is input to the comparator 22 in FIG. "0" continues.
When the continuous "0" continues for a predetermined number (for example, 3 samples) or more, the servo mark detection signal SB is set to the H level. The input signal in is converted into a digital signal by the A / D converter based on the H-level detection signal SB, and the digital signal is stored. This digital signal is converted to a D / A converter 2 of FIG.
4 is input as the correction signal SG14 to offset the output signal SG12 of the amplifier circuit 21.

As described above, the intermediate value correction is performed by the signal read from the servo mark area through which the read head passes before the phase detection area, so that the input signal in read from the phase detection area has the data string correction and the DFT operation. And the time required to calculate the phase difference is reduced.
This makes it possible to read data stably and at high speed.

The A / D converter outputs the correction signal SG14 until the servo mark ends, that is, the input signal in in response to the H-level servo mark detection signal SB.
A / D conversion may be performed by holding the data, and there is no need for high-speed conversion. Therefore, the circuit configuration is simple, and an analog circuit can be easily realized.

In the above embodiment, the correction circuit 23 corrects the center value of the output signal SG12 of the amplifier circuit 21. However, the calculation result (phase) of the DFT calculation circuit 25 is used.
The center value may be corrected based on That is,
The signals X1 and X2 with a phase difference of A ° were previously written on the recording medium, and the phase difference calculation resulted in A ± B. If the value of B is a large value (out of the allowable range), increase the center value, or
Lower it and calculate the phase again. And the operation result is A ± C
The central value is determined when the value of C becomes 0 or a small value (within an allowable range). With this method, the center value can be corrected.

For example, the enable signal EN shown in FIG.
Are the H level, and the two periods t1 and t2 are the phase calculation periods. These periods are two cycles of the input signal in,
Since the first phase calculation period in the first half and the second phase calculation period in the second half are shifted by two samples, the phase difference calculated by these is (360 ° / 8) × 2 = 90 °.

Therefore, the phase difference of the input signal in read out from the phase detection area is calculated, and the calculated result is 90 °.
The signal (code) supplied to the D / A converter 24 is raised and lowered so as to be within ± α (α is an allowable range), and the center value is corrected.

In the DFT circuit 25 of the above embodiment, the phase is calculated by the sign of the real and imaginary components and the magnitude (large or small) of the sign of the real and imaginary components without using the arc tangent (ARCTAN) calculation. You may.

That is, a plane having the real component as the X axis and the imaginary component as the Y axis is divided into four parts by the sign of the real and imaginary components, and divided into eight parts according to the magnitude of the real and imaginary components. If the difference between the imaginary components is 2 times or more and 2 times or less, it is divided into 16 parts, and 2En (2n) or 2En or less
+3 split. For example, FIG. 24 shows an example in which the sign of the real number component and the sign of the imaginary number component, and the magnitude thereof are divided into eight.

In the figure, X = real number component and Y = imaginary number component. The eight divided areas represent the phase (ISOU) = angle, and are divided into eight, so that the phase of each area is 1 = 0 to
45 °, 2 = 45-90 °, 3 = 90-135 °, 4 =
135-180 °, 5 = -180--135 °, 6 =-
135-90 °, 7 = -90 ° -45 °, 8 = -4
5 ° to 0 °.

On the other hand, it is determined according to the procedure shown in FIG. 23 in which region the values of the real component and the imaginary component are included. The phase difference is calculated based on the determination result. Although such a calculation result (phase difference) includes an error, the error can be reduced by increasing the number of divisions. As described above, it is possible to calculate a phase difference including a (sufficient) error required for the phase servo, that is, to configure the number of divisions, that is, an arithmetic circuit according to the required arithmetic accuracy.

In the above embodiment, the phase may be obtained based on the start point of the sample. FIG. 25 shows the angles of the data strings D1 and D2 with respect to the sample start points. For example, if the corrected data sequence is "-1, -1, -1,0,1,1,1,0, -1, -1, -1,0,1,1,1,0", Since the data sequence D1 in FIG. 25 matches from the second bit from the left, the phase thereof is 135 °. Similarly, the phase of the data string "1,1,0, -1, -1, -1,0,1,1,1,0, -1, -1, -1,0,1" is 0 ° , `` 1,0, -1, -1, -1,0,1,1,1,0, -1, -1, -1,0,1,
The phase of `` 1 '' is 45 ° and `` 0, -1, -1, -1,0,1,1,1,0, -1, -1,-
1,0,1,1,1 ”has a phase of 90 ° and“ -1,0,1,1,1,0, -1, -1,-
The phase of "1,0,1,1,1,0, -1, -1" is -135 degrees. Also, if the data string is "-1, -1, -1, -1,1,1,1,1, -1, -1, -1, -1,1,1
1,1,1 ", the phase is 122.5 ° from the data string D2.
And "-1, -1,1,1,1,1, -1, -1, -1, -1, -1,1,1,1,1, -1, -1
Is -157.5 °.

The configuration of the phase calculation circuit 20 of the above embodiment may be changed as appropriate. For example, a configuration may be employed in which a low-pass filter that transmits a fundamental wave component is inserted between the amplifier circuit 21 and the comparator 22.

In the above embodiment, the clock signal CLK
, The input signal in is sampled at eight samples in one cycle, but the number of samples in one cycle may be changed as appropriate. At this time, it is needless to say that the expressions (1) to (4) and the expected data strings D1 and D2 are changed in accordance with the number of samples.

The following summarizes the various embodiments described above. (Supplementary Note 1) The input signal is amplified at a high gain, and a multi-valued digital signal is obtained at at least one or more (including 1) determination levels sufficiently lower than the peak level of the amplified signal including the fundamental wave component. And calculating a phase of the fundamental wave component based on the digital signal. (Supplementary Note 2) The input signal is amplified so as to shake out a predetermined determination range, the amplified signal including a fundamental wave component is converted into at least a binary digital signal based on the determination range, and the input signal is converted based on the digital signal. A phase calculation method, wherein a phase of a fundamental wave component is calculated. (Supplementary Note 3) An amplifier circuit that outputs a signal obtained by amplifying an input signal by a predetermined gain, and one or more (including 1) determination levels are set, and the one or more determination levels and the output of the amplifier circuit are set. A comparator for comparing the output signal to a multi-valued digital signal of two or more values, and a calculating circuit for calculating a phase of the multi-valued digital signal;
A phase calculating device, wherein a gain of the amplifier circuit is set so that an output signal of the amplifier circuit exceeds a maximum value and a minimum value of the determination level, respectively. (Supplementary Note 4) An amplifier circuit that outputs a signal obtained by amplifying an input signal with a predetermined gain, a predetermined input range is set, and the output signal of the amplifier circuit is compared with the input range to determine the output signal by 2. A comparator for converting the multi-level digital signal into a multi-valued digital signal having a value greater than or equal to a value, and a calculating circuit for calculating a phase of the multi-valued digital signal. A phase calculation device wherein a gain of a circuit is set. (Supplementary Note 5) The input signal is a signal of a different phase read from a plurality of areas in a phase calculation area recorded on a recording medium, and the calculation circuit outputs a fundamental wave component of the input signal. 5. The phase calculation device according to claim 3, wherein the phase calculation device is characterized in that: (Supplementary Note 6) A judgment signal from the comparator is input, and a correction signal is generated based on the judgment signal so that the center value of the output signal of the amplifier circuit substantially matches the center value of the range of the comparator. An intermediate value correction circuit; and a D / A converter that outputs a correction voltage obtained by converting the correction signal into an analog signal to the amplifier circuit, wherein the amplifier circuit adds the correction voltage to the amplified signal and outputs the amplified signal. The phase calculation device according to any one of supplementary notes 3 to 5, wherein (Supplementary Note 7) The intermediate value correction circuit counts a maximum value and a minimum value of the determination signal from the comparator, respectively, and generates a correction signal so as to match them when the count values are different. 7. The phase calculation device according to claim 6, wherein (Supplementary Note 8) The determination signal from the comparator is input, and the data string to be corrected including the determination signal is determined based on the data string expected from the corrected data string, and the determination signal is corrected based on the data string. 8. The phase calculation device according to claim 3, further comprising: a data string correction circuit that outputs the calculated signal to the calculation circuit. 8. (Supplementary Note 9) The data string correction circuit stores a plurality of data strings that can be expected as known data strings, determines whether the corrected data string includes a predetermined value, and based on the determination result. 9. The phase calculating apparatus according to claim 8, wherein one of the plurality of known data strings is selected, and the data string to be corrected is corrected by the selected data string. (Supplementary Note 10) The data sequence correction circuit prepares a known data sequence having a bit number that is at least one cycle longer than the data sequence to be corrected, and converts the corrected data sequence to one bit with respect to the known data sequence. Wherein the known data sequence corresponding to each bit of the data to be corrected when the total value is the smallest is output as a corrected data sequence. The phase calculation device according to any one of the preceding claims. (Supplementary Note 11) The phase is calculated in advance for each bit of the known data sequence, and the calculation circuit determines the start point of the sampling of the corrected data sequence when the sum is the smallest in the data sequence correction circuit. 11. The phase calculating device according to claim 9 or 10, wherein a phase of the input signal is obtained from bits of the known data sequence corresponding to the start point based on data. (Supplementary Note 12) A signal having a different phase in advance is input as the input signal, and the intermediate value of the output signal of the amplifier circuit is corrected by a correction signal generated so that the calculated phase difference between the signals becomes a predetermined value. 7. The phase calculating apparatus according to claim 6, wherein (Supplementary Note 13) The phase calculation area is included in a servo area of a recording medium, the servo area further includes a servo mark area, and an input signal read from the servo mark area has no waveform. The intermediate value correction circuit generates a correction signal based on the value of the servo mark so that the intermediate value of the output signal of the amplifier circuit substantially matches the intermediate value of the input range of the comparator. The phase calculation device according to any one of the preceding claims. (Supplementary Note 14) The calculation circuit may obtain a real component and an imaginary component of a fundamental wave in the DFT operation, and calculate a phase by an arc tangent thereof.
5. The phase calculation device according to any one of the items 5. (Supplementary Note 15) The calculation circuit may use a plane having the real component as the X axis and the imaginary component as the Y axis based on the sign and value of the real component and the imaginary component without using the arc tangent in a plurality of regions. It is determined in which region the data of the real component and the imaginary component are included, and based on the determination result, the phase corresponding to the region including the data is set as the phase of the input signal. 15. The phase calculating device according to claim 14, wherein the phase calculating device is characterized in that: (Supplementary Note 16) The phase calculation device according to Supplementary Notes 3 to 15 is connected to a digital signal generator, and a rectangular wave generated by the generator is supplied as the input signal to perform an operation test of the phase calculation. A test method for a phase calculation device, characterized in that:

[0104]

As described in detail above, according to the present invention,
It is possible to provide a phase calculation method, a phase calculation device, and a test method thereof that correspond to a high-frequency input signal and reduce the influence of noise.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a phase calculation circuit according to an embodiment.

FIG. 2 is a waveform diagram of an output signal of an amplifier.

FIG. 3 is a waveform diagram of an output signal of a comparator.

FIG. 4 is a block circuit diagram of an amplifier and a center value correction circuit.

FIG. 5 is a block circuit diagram of a data string correction circuit.

FIG. 6 is an explanatory diagram of center value correction.

FIG. 7 is a flowchart of a data string correction process.

FIG. 8 is an explanatory diagram of correction of a data string.

FIG. 9 is an explanatory diagram of correction of a data string.

FIG. 10 is an explanatory diagram of correction of a data string.

FIG. 11 is an explanatory diagram of a sampling result of an input signal.

FIG. 12 is an explanatory diagram of a phase calculation.

FIG. 13 is a waveform chart of FIG. 11;

FIG. 14 is an explanatory diagram of a comparator output.

FIG. 15 is an explanatory diagram of a phase calculation.

FIG. 16 is a waveform chart of FIG.

FIG. 17 is an explanatory diagram of a comparator output.

FIG. 18 is an explanatory diagram of a phase calculation.

FIG. 19 is a waveform chart of FIG.

FIG. 20 is a block circuit diagram of an operation test of the phase calculation circuit.

FIG. 21 is a waveform chart of an operation test.

FIG. 22 is an explanatory diagram of another center value correction method of the amplifier.

FIG. 23 is an explanatory diagram of another phase calculation.

FIG. 24 is an explanatory diagram of another phase calculation.

FIG. 25 is an explanatory diagram of another phase calculation.

FIG. 26 is a block circuit diagram of a conventional phase calculation circuit.

FIG. 27 is a schematic diagram of a system LSI.

[Explanation of symbols]

 Reference Signs List 21 amplifier circuit 22 comparator 23 correction circuit 23a center value correction circuit 23b data string correction circuit 24 D / A converter 25 calculation circuit (DFT calculation circuit)

Claims (10)

[Claims] An input signal is amplified with a high gain, and a multilevel digital signal is obtained at at least one or more (including 1) determination levels sufficiently lower than a peak level of the amplified signal including a fundamental wave component. A phase calculation method, wherein the phase is converted into a signal and the phase of the fundamental wave component is calculated based on the digital signal. 2. Amplifying an input signal so as to pass through a predetermined determination range, converting the amplified signal including a fundamental wave component into at least a binary digital signal based on the determination range, and based on the digital signal. A phase calculation method, wherein a phase of the fundamental wave component is calculated. 3. An amplifier circuit for outputting a signal obtained by amplifying an input signal with a predetermined gain, and one or more (including 1) determination levels are set, and the one or more determination levels and the amplifier circuit A comparator for comparing the output signal with the output signal and converting the output signal into a multi-valued digital signal having two or more values; and a calculation circuit for calculating the phase of the multi-valued digital signal. 2. A phase calculating device according to claim 1, wherein the gain of said amplifier circuit is set so as to exceed a maximum value and a minimum value of said determination level, respectively. 4. An amplifier circuit for outputting a signal obtained by amplifying an input signal by a predetermined gain, a predetermined input range being set, and comparing the output signal of the amplifier circuit with the input range to obtain the output signal. A comparator for converting the binary signal into a multi-valued digital signal; and a calculating circuit for calculating a phase of the multi-valued digital signal, wherein the output signal of the amplifier circuit is swept over the input range. A phase calculation device wherein a gain of an amplifier circuit is set. 5. The input signal is a signal of a different phase read from a plurality of areas in a phase calculation area recorded on a recording medium, and the calculation circuit outputs a fundamental wave component of the input signal. The phase calculation device according to claim 3 or 4, wherein: 6. A determination signal is input from the comparator, and a correction signal is generated based on the determination signal such that a center value of an output signal of the amplifier circuit substantially matches a center value of a range of the comparator. And a D / A converter that outputs a correction voltage obtained by converting the correction signal into an analog signal to the amplifier circuit, wherein the amplifier circuit adds the correction voltage to the amplified signal. The phase calculation device according to claim 3, wherein the phase calculation device outputs the output. 7. The intermediate value correction circuit counts a maximum value and a minimum value of a determination signal from the comparator, respectively, and generates a correction signal such that when the count values are different, the two match. The phase calculation device according to claim 6, wherein 8. A judgment signal from the comparator is inputted, a data string to be corrected composed of the judgment signal is judged as a data string expected from the data string to be corrected, and the judgment signal is determined based on the data string. The phase calculation device according to claim 3, further comprising a data string correction circuit that outputs a corrected signal to the calculation circuit. 9. The data string correction circuit stores a plurality of data strings that can be expected as known data strings, determines whether or not the corrected data string contains a predetermined value, and based on the determination result. One of the plurality of known data strings
9. The phase calculating apparatus according to claim 8, wherein one of the two is selected, and the data string to be corrected is corrected by the selected data string. 10. A phase calculation device according to claim 3, wherein the phase calculation device is connected to a digital signal generator, and a rectangular wave generated by the generator is supplied as the input signal to perform an operation test of the phase calculation. A method for testing a phase calculation device, characterized in that: