JP2002091375A - Method for processing gradation display of plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce granular noise corresponding to a minimum display level generated when gradations of a PDP(Plasma Display Panel) is increased by error diffusion processing. SOLUTION: When analog video signals for two adjacent pixels A, B of a PDP are inputted, each of them is converted into a digital data and this digital data is processed by an inverse γ-correction, and the data processed by the inverse γ-correction is processed by error diffusion, to generate a minimum display level value. Then, prescribed values based on the generated minimum display level values for the pixels A, B are distributed to the digital data for the pixels A, B processed by the inverse γ-correction, and the pixel is replaced with the pixel B for each line or each field.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gradation display processing method for a plasma display panel.

[0002]

2. Description of the Related Art In a plasma display panel (PDP) of this type, one frame period is constituted by a plurality of subfields SF1 to SF8, each of which has a different relative ratio of a lighting period (sustain discharge period; proportional to light emission luminance). are doing. Then, the input analog video signal is converted into a digital signal having the number of bits corresponding to the number of subfields by A / D conversion, and a corresponding pixel is turned on by an appropriate subfield based on the bit data to thereby perform a predetermined operation. A gradation image is displayed.

[0005] In the example of FIG.
This is an example of displaying 56 gradations, and the most significant gradation bit (8
Bit) corresponds to SF1, the gradation bit (7th bit) corresponds to SF2, the gradation bit (6th bit) corresponds to SF3, and the gradation bit (5th bit) corresponds to SF1.
4, the gradation bit (the fourth bit) corresponds to SF5, the gradation bit (the third bit) corresponds to SF6, and the gradation bit (the second bit) corresponds to SF7. (Bit) corresponds to SF8. In each of the subfields SF1 to SF8, the sustain discharge period is set to, for example, 128, 64, 32, 16, 8, 4, 2, 1 as the number of gradations (relative ratio of light emission luminance: proportional to the number of light emission pulses (sustain pulses)). Weighted.

[0004] In general, PDP employs an error diffusion process used for a printing process of a printer or the like when increasing the display gradation. Here, the error diffusion processing is
When printing a photo with a device that can only express binary values of white and black, such as a monochrome printer, expresses intermediate colors such as gray until the color changes from white to black depending on the pixel density of white and black per unit area of the photo Then, it is a method of recognizing the image as if it were a pseudo-smooth image. In an actual PDP, as described above, since n-value gradation display is possible, the n-value error diffusion processing is performed for R (red), G (green),
For each color of B (blue), 167.9 million colors are generally realized.

[0005]

In the error diffusion method used in the above-described error diffusion processing, for example, when a value 7/32 is expressed in a PDP having a pixel capable of displaying 16 values, one pixel expresses only 16 values. Therefore, the value 7/32 cannot be expressed as 3.5 / 16. Therefore, the value 7/32 is divided into values of 3/16, and one of the divided values, 3/16, is left as it is.
A value 4 is obtained by adding the value 1/16 to the other divided value 3/16.
/ 16. That is, the value 7/32 is changed to 3/16 and 4/16
Using two adjacent pixels A and B, one pixel A expresses a value of 3/16, and the other pixel B expresses a value of 4/16
To express.

Here, the value 1/16 of the pixel B is the display minimum level value. In the error diffusion method, the display minimum level value 1/16 is calculated, and the calculated display minimum level value 1/16 is calculated. An intermediate gradation from the value 3/16 to the value 4/16 is expressed by how many 16 are added to the value 3/16. In this example, one display minimum level value 1/16 is added. A conventional PDP using such an error diffusion process has a problem that when displaying a natural image such as a photograph, granular noise corresponding to the minimum display level value is generated, and good image quality cannot be obtained.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the granular noise corresponding to the minimum display level value generated when the gradation of a PDP is increased by an error diffusion process, and to obtain an image of good quality.

[0008]

SUMMARY OF THE INVENTION In order to solve such a problem, the present invention relates to a display device having a PDP constituted by a plurality of unit display areas and performing a gradation display of the PDP, comprising a plurality of units. A first step of setting two adjacent unit display areas of the display area as a pair of display areas, and a first unit display area data and a second unit display area data forming a pair of display areas. A second step of exchanging for each adjacent display block;
When the analog video signal for the unit display area is input, a third step of converting the analog video signal into digital data and a fourth step of performing predetermined correction processing on the digital data converted based on the processing of the third step and outputting the result. Step 4
A fifth step of performing an error diffusion process on the digital data based on the processing of the step to calculate a display minimum level value required for the intermediate gradation, and a first and a second calculation based on the processing of the fifth step. Based on the display minimum level value for the unit display area of No. 2, the first processing result of the fourth step
And a sixth step of allocating a predetermined value to the digital data for the second unit display area, and a seventh step of outputting digital data based on the processing result of the sixth step to the PDP to perform gradation display And

[0009] The processing in the sixth step is a step of performing predetermined processing on the digital data for the first and second unit display areas based on the calculated display minimum level values for the first and second unit display areas. 1st mode without value distribution and 1st mode
In the second mode, the value "1" is distributed as a predetermined value to the digital data for the unit display area, and the value "1" is distributed as the predetermined value to the digital data for the first and second unit display areas. It has a process of selecting any one of the third modes. Further, the second step includes the first step.
Performing a process of exchanging the data for the unit display area with the data for the second unit display area in each adjacent line.
Having the following steps. The second step includes a ninth step of performing a process of exchanging the data for the first unit display area and the data for the second unit display area in adjacent fields.

[0010] A tenth step of setting n (n is an integer of 3 or more) adjacent unit display areas of one of the plurality of unit display areas as one field, and an analog step for n unit display areas. An eleventh step of receiving a video signal and converting it into digital data, a twelfth step of performing a predetermined correction process on the digital data converted based on the processing of the eleventh step, and outputting the digital data;
A thirteenth step of performing error diffusion processing on the digital data based on the processing of the second step to calculate a display minimum level value required for the intermediate gradation, and n unit display areas obtained as a result of the eleventh step A display minimum level value based on the twelfth processing result to any one of the digital data, and outputting the digital data to a PDP for display. The PDP includes N (N = n) The processing in the thirteenth step includes the step of sequentially selecting any one of the n pieces of digital data for the unit display area for every N fields and adding the display minimum level value Is included.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a PDP (plasma display panel) device to which the present invention is applied.

In FIG. 1, the present PDP device is a PDP 1
And an A / D converter 11 for converting the input analog video signal a into digital video data, a frame memory 15 for storing digital video data, and a PDP 10 for storing digital video data in the frame memory 15.
0, an output processing section 16 for outputting a synchronizing signal from the analog video signal a, a timing generating section 18 for generating a timing pulse based on the synchronizing signal, and a frame memory 15 based on the timing pulse. Control unit 1 that controls the accumulation of data into the memory and the output of data from the frame memory 15 to the output processing unit 16
9 and a drive timing control unit 20 that controls the output processing unit 16 based on the timing pulse to output the data of the frame memory 15 to the PDP 100, and outputs a drive pulse to the PDP 100 to perform gradation display of the PDP 100. are doing.

In addition to the above components, the present PDP apparatus has a γ-reverse correction, which is a reverse correction of gradation correction (γ correction) for digital video data A / D-converted by the A / D converter 11. Γ inverse correction unit 12 for performing a correction operation, and γ inverse correction unit 12
Error diffusion processing unit 14 that performs error diffusion processing on the data that has been subjected to γ inverse correction calculation to calculate the display minimum level value required for the intermediate gradation, and digital data that has been subjected to γ inverse correction calculation by γ inverse correction unit 12. It is determined whether or not a predetermined value is to be distributed based on the display minimum level value from the error diffusion processing unit 14, and the addition processing unit 13 that accumulates processing data based on the determination result in the frame memory 15. Have.

FIG. 2 is a block diagram showing a configuration of a main part of the present PDP apparatus, and shows a configuration of the addition processing unit 13. As shown in FIG. The addition processing unit 13 includes the addition units 21 and 22 and the delay unit 2
3 and 24, and a control unit 25. By the way, A / D
The digital video data A / D-converted by the conversion unit 11 is subjected to the γ inverse correction operation by the γ inverse correction unit 12 and output to the addition processing unit 13 as described above. On the other hand, the output data of the inverse γ correction unit 12 is subjected to error diffusion processing by the error diffusion processing unit 14 to calculate a display minimum level value, and the calculated display minimum level value is output to the addition processing unit 13.

Here, adjacent pixels A and B in PDP 100
(Pixel A = first unit display area of PDP, pixel B = PD
Assuming that each data for P (a second unit display area adjacent to the first unit display area) sequentially arrives at the addition processing unit 13, the display for the pixel A processed by the error diffusion processing unit 14 is performed. The minimum level value a is delayed by one pixel in the delay unit 24, and then input to the control unit 25 at the same time as the display minimum level value b for the pixel B from the error diffusion processing unit 14. On the other hand, the data for pixel A corrected by the inverse γ correction unit 12 is input to the addition unit 22 after being delayed by one pixel by the delay unit 23 via the addition unit 21. At this time,
The data for pixel B corrected by the inverse γ correction unit 12 is simultaneously input to the addition unit 21.

That is, the timing at which the data for pixel A from the inverse γ correction section 12 is input to the addition section 22 and the timing at which the data for pixel B from the γ inverse correction section 12 are input to the addition section 21. The timing at which the display minimum level values a and b for the pixel A and the pixel B from the error diffusion processing unit 14 are input to the control unit 25 is the same timing.

The control unit 25 in the addition processing unit 13 determines the display minimum level values a and b for the pixel A and the pixel B from the error diffusion processing unit 14, and based on the determination result, One of the three outputs (1) to (3) is selected. (1) When both the display minimum level value a for the pixel A and the display minimum level value b for the pixel B are “0”, “0” is added to both the pixels A and B. (2) When only one of the display minimum level value a for the pixel A and the display minimum level value b for the pixel B is “0”, “1” is added to only the pixel A. (3) When both the minimum display level value a for the pixel A and the minimum display level value b for the pixel B are “1”, “1” is added to both the pixels A and B.

That is, when the display minimum level value a for the pixel A and the display minimum level value b for the pixel B are both “0”, the control unit 25 outputs “0” to both the addition units 21 and 22.
Is output. As a result, the pixel A from the inverse γ correction unit 12
The data for pixel B and the data for pixel B are stored in the frame memory 15 without being added, and output from the output processing unit 16 to the PDP 100 for display.

When only one of the display minimum level value a for the pixel A and the display minimum level value b for the pixel B is “0”, the control unit 25 adds “0” to the addition unit 21. Part 22
Is output as “1”, so that “1” is added only to the data for pixel A from the inverse γ correction unit 12. When the display minimum level value a for the pixel A and the display minimum level value b for the pixel B are both “1”, the control unit 25 adds
"1" is output to both 1 and 22. As a result, the data for pixel A and the pixel B
After adding “1” to the data for each and accumulating them in the frame memory 15, the data is further output from the output processing unit 16 to the PDP 100 and displayed.

Here, when the data of the adjacent pixels A and B are exchanged between an odd field and an even field among a plurality of display fields of the PDP 100, when the gradation of the PDP is increased by the error diffusion processing, The generated granular noise corresponding to the minimum display level value can be reduced by approximately 6 dB, and it is possible to obtain an image with a good S / N ratio. That is, as shown in FIG.
When the display area 101 of the DP 100 is composed of the odd field F + 1 and the even field F + 2, the data of the pixel A and the data of the pixel B adjacent to the pixel A are exchanged between the odd field F + 1 and the even field F + 2. Further, as shown in FIG. 3, each data of the adjacent pixels A and B is exchanged between the odd line n + 1 and the even line n + 2.

In the present embodiment, an example of two adjacent pixels A and B has been described. However, not only a pair of two adjacent pixels A and B but also n adjacent pixel blocks and n fields in the same manner. The minimum display level can be reduced to 1 / n by alternating the pattern that goes around the field.

That is, as shown in FIG. 4, four adjacent pixel blocks Block1 (field F + 1) to Block4 (field F + 4) each having four adjacent pixels A, B, C, and D are removed from the pixel block Block1. Pixel block Block2 → Pixel block Block in order
When the display is performed in one cycle from 3 to the pixel block Block4, the display minimum level is displayed on the pixel A as shown in FIG. 4A in the display of the adjacent pixel block Block1, and as shown in FIG. 4B in the display of the adjacent pixel block Block2. Displays the minimum display level on the pixel B, and displays the adjacent pixel block Block.
In the display of No. 3, the minimum display level is displayed on the pixel C as shown in FIG. 4C, and in the display of the adjacent pixel block Block 4, the minimum display level is displayed on the pixel D as shown in FIG. 4D. As a result, the minimum display level can be reduced to 1/4.

[0023]

As described above, according to the present invention, P
In a display device that performs a DP gray scale display, two adjacent unit display regions among a plurality of unit display regions are set as a pair of display regions, and data of a first unit display region forming the pair of display regions is stored in the display device. When the data of the second unit display area can be exchanged for each adjacent display block, and when analog video signals for the first and second unit display areas are input, the data is converted into digital data, and the converted digital data is converted. While performing predetermined correction processing on the data and outputting the result, error diffusion processing is performed on the output data to calculate a display minimum level value required for the intermediate gradation, and the calculated first and second unit display areas A predetermined value is distributed to the digital data for the first and second unit display areas based on the display minimum level value for the first unit and output to the PDP. It is possible to reduce granular noise corresponding to the display minimum level value generated when increased, thus making it possible to obtain a good image of the S / N ratio.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PDP device to which the present invention has been applied.

FIG. 2 is a block diagram showing a main configuration of the PDP device.

FIG. 3 is a diagram showing an arrangement pattern of adjacent pixels A and B of a PDP.

FIG. 4 is a diagram showing an arrangement pattern of adjacent pixels A, B, C, and D of a PDP.

FIG. 5 is a diagram showing an arrangement configuration of subfields used in a PDP device.

[Explanation of symbols]

11 A / D conversion unit, 12 γ inverse correction unit, 13 Addition processing unit, 14 Error diffusion processing unit, 15 Frame memory,
16 output processing section, 17 synchronization separation section, 18 timing generation section, 19 memory control section, 20 drive timing control section, 21, 22 addition section, 23, 24 delay section, 2
5: control unit, 100: plasma display panel (P
DP), 101: display area of PDP, a: input video signal.

Claims (5)

[Claims] 1. A display device having a plasma display panel composed of a plurality of unit display areas and performing a gradation display of the plasma display panel, wherein two adjacent unit display areas of the plurality of unit display areas are provided. A first step of setting as a pair of display areas; a second step of replacing each data of the first and second unit display areas constituting the pair of display areas for each adjacent display block; When an analog video signal for the first and second unit display areas is input, a third step of converting the analog video signal into digital data, and a predetermined correction process is performed on the digital data converted based on the processing of the third step. A fourth step of outputting, and performing an error diffusion process on the digital data based on the process of the fourth step, and A fifth step of calculating a 示最 small level value, the first and second calculated based on the processing of the fifth step
Based on the minimum display level value for the unit display area of
A sixth step of allocating a predetermined value to the digital data for the first and second unit display areas of the processing result of the step of: outputting digital data based on the processing result of the sixth step to the plasma display panel; A gradation display processing method for a plasma display panel. 2. The processing according to claim 1, wherein the processing in the sixth step is based on the calculated minimum display level values for the first and second unit display areas. A first mode in which the predetermined value is not allocated to the digital data of the first mode, a second mode in which the value “1” is allocated as the predetermined value to the digital data for the first unit display area, and first and second modes. A gradation display processing method for a plasma display panel, comprising a process of selecting any one of a third mode in which a value “1” is distributed as digital data for a unit display area as the predetermined value. 3. The method according to claim 2, wherein the second step performs a process of exchanging the data for the first unit display area and the data for the second unit display area with each adjacent line. A gradation display processing method for a plasma display panel, comprising the steps of: 4. The ninth step according to claim 2, wherein the second step performs a process of exchanging the data for the first unit display area and the data for the second unit display area in adjacent fields. A gradation display processing method for a plasma display panel, comprising the steps of: 5. A display device having a plasma display panel composed of a plurality of unit display areas and performing gradation display of the plasma display panel, wherein n (n is 3) adjacent to the plurality of unit display areas. A tenth step of setting the (integer) unit display areas as one field, an eleventh step of receiving the analog video signals for the n unit display areas, and converting the analog video signals into digital data, A twelfth step of performing a predetermined correction process on the digital data converted based on the process of the eleventh step and outputting the corrected data, and performing an error diffusion process on the digital data based on the process of the twelfth step to perform intermediate gradation A thirteenth step of calculating a display minimum level value necessary for the nth step, and a data for n unit display areas of the processing result of the eleventh step. And a thirteenth step of adding a display minimum level value based on the twelfth processing result to any one of the total data and outputting the same to the plasma display panel for display. = N) fields, and the processing in the thirteenth step is to sequentially select any one of the n pieces of digital data for the unit display area for every N fields and set the display minimum level value. A gradation display processing method for a plasma display panel, comprising a fourteenth step of adding.