JP2002091340A - Matrix array board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a matrix array board which is used for a flat-panel display device or the like and prevents the cut of a signal line at an intersecting position between a scanning line and the signal line without increasing a manufacturing cost or the like. SOLUTION: On each position where a signal line 8 gets over the outline 11b of a scanning line 8, the signal line 8 is expanded to the outside in the width direction and a signal line expanding part 8a is arranged so as to be extended while covering the outline 11b of the scanning line. Except the position of the signal line expanding part 8a, the width of the signal line 8 on the position overlapped with the scanning part is approximately the same as that of positions other than the overlapped position. Consequently the increment of electric capacity between the signal line 8 and the scanning line 11 can be minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix array substrate used for a flat panel display represented by a liquid crystal display.

[0002]

2. Description of the Related Art In recent years, flat display devices such as liquid crystal display devices have been used as display devices such as personal computers, word processors or TVs, and as projection display devices, taking advantage of the features of thinness, light weight, and low power consumption. It is used in various fields.

Among them, an active matrix type display device in which a switch element is electrically connected to each pixel electrode is capable of realizing a good display image without crosstalk between adjacent pixels. Have been done.

[0004] The structure of the active matrix type liquid crystal display device of the light transmission type will be briefly described below.

Generally, in an active matrix type liquid crystal display device, a matrix array substrate (hereinafter, referred to as an array substrate) and an opposing substrate are arranged close to each other at a predetermined interval, and are provided on the surface layer of both substrates during this interval. The liquid crystal layer is held via the aligned alignment film. In an array substrate, a plurality of signal lines, for example, as an upper metal wiring pattern, and a plurality of scanning lines, for example, as a lower metal wiring pattern, are arranged in a grid on a transparent insulating substrate such as glass via an insulating film. Pixel electrodes made of a transparent conductive material such as ITO (Indium-Tin-Oxide) are arranged in a region corresponding to each grid of the grid. At each intersection of the grid, a switching element for controlling each pixel electrode is arranged. The switching element is a thin film transistor (hereinafter, T
Abbreviated as FT. In the case of (1), the gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to the pixel electrode.

[0006] The opposing substrate is formed by disposing an opposing electrode made of ITO or the like on a transparent insulating substrate such as glass, and a color filter layer for realizing color display.

However, in the array substrate as described above, the signal line formed of the upper wiring pattern may cross over the scanning line formed of the lower wiring pattern, so that "step disconnection" may occur in the signal line. That is, where the signal line extends over the edge of the scanning line, disconnection may occur completely or partially. This is because, when a first conductive layer pattern including a scanning line is formed by etching a metal layer, an end face (edge) defining a contour of the thin film pattern is often formed with a steep (high) slope with respect to a substrate surface. (Taper angle). That is,
Since the edge of a scanning line having a large film thickness forms a sharp cliff, disconnection may occur in a signal line superimposed via an insulating film.

In order to solve the problem of disconnection, Japanese Patent Laid-Open No.
JP-A-372934 and JP-A-9-064366 propose a technique in which the edge of the first conductive layer pattern is tapered (small taper angle). These are methods of patterning a metal thin film by wet etching, and are techniques for setting the metal thin film as a multilayer metal thin film including a plurality of metal layers having different etching rates.

More specifically, a two-layer film is used in which the lower layer is made of metal molybdenum (Mo) having a low wet etching rate, and the upper layer is metal aluminum (Al) metal having a high wet etching rate. It is drawn inward from the outline of.

[0010]

However, such a method requires two kinds of metal targets and increases the material cost, and also requires a plurality of film forming apparatuses, resulting in an increase in cost and a decrease in productivity. Cause.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has been made in view of the above-mentioned problems.
An object of the present invention is to provide a signal line capable of preventing a reduction in production yield of a signal line due to a disconnection at a crossing point between a scanning line and a signal line.

[0012]

According to the first aspect of the present invention, there is provided an array substrate comprising: a plurality of scanning lines arranged substantially in parallel; a plurality of signal lines arranged substantially orthogonal to the scanning lines; A pixel electrode arranged in a matrix-shaped region defined by a scanning line and a signal line, a thin film transistor arranged for each pixel electrode and switching a signal input from the signal line to the pixel electrode, and the scanning line; A first conductive layer including a gate electrode of the thin film transistor, the first conductive layer covering the first conductive layer, forming a gate insulating film of the thin film transistor, and a semiconductor active film of the thin film transistor Including the signal line, the source and drain electrodes of the thin film transistor, and patterned under the same mask pattern as the semiconductor layer. A matrix array substrate provided with a second conductive layer, where the signal line crosses the contour of the scanning line, the signal line swells outward in the width direction and the vicinity of the contour is A width of the signal line is larger than a width of a region on the scanning line and a region sandwiching the scanning line adjacent to the signal line at the crossing point.

According to the above configuration, it is possible to easily prevent a reduction in manufacturing yield due to disconnection of a signal line. In addition, an increase in the capacitance between the signal line and the scanning line can be minimized.

An array substrate according to a fourth aspect of the present invention includes a third conductive layer disposed on the second conductive layer and including the pixel electrode,
An auxiliary conductive layer made of the third conductive layer is arranged as a redundant wiring along the signal line made of the second conductive layer, and the auxiliary conductive layer bulges outward in the width direction at the place where the auxiliary conductive layer crosses, and the contour is formed. It is characterized by forming a bulging portion that covers the vicinity of the line.

Thus, disconnection of the signal line is further prevented.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A matrix array substrate according to an embodiment will be described with reference to FIGS.

FIG. 1 is a plan view showing a configuration of a pixel portion of the array substrate 10. FIG. 2 shows the direction along the scanning line at the intersection of the scanning line and the signal line (A-A in FIG. 1).
FIG. 3 is a longitudinal sectional view taken along a signal line (line BB in FIG. 1) at the same location. FIG. 4 shows the TFT portion (CC line in FIG. 1).
FIG.

The matrix array substrate of the embodiment has a UXGA-TF having a diagonal dimension of an image display area of 20 inches.
It is used for a T-type normally white mode light transmission type liquid crystal display device.

In this matrix array substrate 10, 1600 × 3 signal lines 8 and 1200 scanning lines 11 are arranged so as to be orthogonal to each other. The lower metal wiring pattern including the scanning line 11 and the gate electrode 11a is
The gate insulating film 17 is formed entirely of a single-layer molybdenum-tungsten (Mo-W) alloy.

In each pixel opening defined by the signal line 8 and the scanning line 11, a TFT 9 as a switching element is disposed near the intersection of the signal line 8 and the scanning line 11. As shown in FIG. 4, the TFT 9 is of an inverted stagger type using the extending portion 11a of the scanning line 11 as a gate electrode, and a portion covering the gate electrode 11a is provided with an amorphous silicon An a-Si: H) layer 36 is provided. On the amorphous silicon layer 36, a channel protective film 2 is disposed at a substantially central channel portion, and phosphorus-doped amorphous silicon (n + a-Si: H)
The layers 37 are stacked. Further thereon, a source electrode 33 and a drain electrode 32 made of aluminum (Al) are formed.
Is arranged. The upper metal wiring pattern including the source electrode 33 and the drain electrode 32 is entirely covered with the interlayer insulating film 4 made of a silicon nitride film.

On the interlayer insulating film 4, an IT
A pixel electrode 52 made of an O layer is provided, and is electrically connected to the source electrode 33 via a source-pixel electrode contact hole 42 penetrating the interlayer insulating film 4.

The signal line 8 has a redundant wiring structure of a lower wiring (Al) 31 formed simultaneously with the drain electrode 32 and an upper wiring (auxiliary conductive layer) (ITO layer) 51 formed simultaneously with the pixel electrode 3. The upper and lower wirings 31 and 51 are provided with contact holes 4 penetrating through the interlayer insulating film 4.
1 are electrically connected to each other.

At a place where the signal line 8 goes over the contour line 11b of the scanning line 11, that is, at a place where the signal line 8 overlaps the end face of the scanning line 11, the signal line 8 bulges outward in the width direction. A portion 8a is provided. This bulging portion 8a
It is arranged in a region sandwiching the contour line 11b of the scanning line 11 near the intersection of the contour line 11b of the scanning line 11 and the original contour line of the signal line (the contour line when there is no bulge). Bulge 8a
The dimensions and arrangement of the
The setting is made so as to surely cover the contour line 11b of the scanning line 11. That is, the size of the bulging portion 8a in the direction along the signal line 8 is set to a size that can absorb the positional displacement between the wiring patterns.

In the example shown in FIG. 1, the bulging portion 8a is provided on both sides in the width direction of the signal line 8 at each position where the signal line 8 overlaps the contour line 11b of the scanning line 11. Each of the bulging portions 8a on both sides is rectangular and has substantially the same dimensions.

In the illustrated embodiment, the width of the signal line upper layer wiring 51 is substantially equal to the width of the signal line lower layer wiring 31 at any point, and the width of the signal line lower layer wiring 31 is equal to the width of the bulging portion 8a. And the outline of the signal line upper layer wiring 51 substantially match. That is, the bulging portion 8a is composed of the bulging portion 31a of the signal line lower layer wiring 31 and the bulging portion 51 of the signal line upper layer wiring.
a are superimposed so that they substantially coincide with each other.

The line width of the signal line 8 is substantially constant except for the location of the drain electrode 32 and the location of the bulging portion 8a. That is, the line width of the signal line 8 is substantially the same at a portion 8b where the swelling portion 8a is removed from the portion overlapping the scanning line 11 and a portion 8c along the pixel electrode 52.

As described above, the swelling portion 8a of the signal line 8 is always provided at the position where the signal line 8 overlaps the contour of the scanning line 11, that is, the end face. Occurrence can be reduced.

In the area where the signal line 8 and the signal line lower wiring 31 overlap the scanning line 11, the signal line 8 and the signal line lower wiring 31 become wider only in the vicinity of the contour of the scanning line 11. Therefore, an increase in the electric capacity formed between the signal line lower wiring 31 and the scanning line 11 can be suppressed to a necessary minimum.

If a specific example of the dimensional configuration is shown, the signal line 8
Has a width of 5 μm excluding the portion of the bulging portion 8a and the drain electrode 32, and is 8 μm at the portion of the bulging portion 8a. The size of the bulging portion 8a in the direction along the signal line 8 is 6 μm.
By design, it is set such that the contour line 11b of the scanning line is located at the center of the bulging portion 8a. That is, a margin of about 3 μm is set on both sides in the direction along the signal line 8 from the contour line 11b of the scanning line, so that the displacement of the patterning can be sufficiently absorbed, and the contour line 11b is overcome. The configuration is such that a decrease in the conductivity of the signal line 8 at a location can be sufficiently suppressed.

Further, in this specific example, the increase in the electric capacity between the signal line 8 and the scanning line 11 due to the provision of the bulging portion 8a is caused by the case where all the portions overlapping the scanning line 11 are 8 μm. % ((3 × 3) × 2 ÷ (30 × 3) ×
100 = 20 (%)).

A semiconductor layer 38 that is patterned under the same mask pattern as the signal line lower wiring 31 is disposed below the signal line lower wiring 31. This semiconductor layer 38 is made of the above-mentioned amorphous silicon layer (a-Si: H) 3
6 and a phosphorus-doped amorphous silicon (n + a-Si: H) layer 37 superposed thereon. Signal line lower layer wiring 31
Are laid on the linear semiconductor film 38a made of the semiconductor layer 38, and the linear semiconductor film 38a also has a bulged portion substantially corresponding to the bulged portion of the signal line 8. However,
The width of the linear semiconductor film 38a is smaller than the width of the signal line lower wiring 31. For example, the width of the signal line lower wiring 51 is 5 μm.
On the other hand, the linear portion 38 composed of the semiconductor layer 38
The width of a is 7 μm.

As described above, where the signal line lower wiring 31 extends over the end face (edge) of the pattern of the scanning line 11,
The semiconductor layer 38 is always located, and the semiconductor layer 38 covers the edge of the scanning line 11 and forms a sufficiently gentle slope. Therefore, disconnection of the signal line 8 at the edge of the scanning line 11 is further prevented.

Even if the signal line lower layer wiring 31 is disconnected, the signal line 8 does not break due to the presence of the signal line upper layer wiring 51 as a redundant wiring. Further, the signal line upper layer wiring 51 is also provided with the bulged portion 51a substantially matching the bulged portion 31a of the signal line lower layer wiring 31, so that the occurrence of disconnection is further reduced.

Next, an outline of a manufacturing process of the array substrate 10 will be described.

(1) First Patterning On the glass substrate 18 (FIG. 3), for example, a molybdenum-tungsten alloy film (MoW film) is formed by sputtering.
After being deposited to a thickness of 35 nm, etching using a mixed acid of phosphoric acid, nitric acid, acetic acid and water is performed under the pattern of the photoresist, so that the scanning line 11 and the gate electrode 11a comprising the extended portion thereof are formed. To form

(2) Second Patterning A 35 made of a silicon oxide film is formed by a plasma CVD method.
A first gate insulating film 15 having a thickness of 0 nm and a second gate insulating film 16 having a thickness of 50 nm made of a silicon nitride film are deposited.
An amorphous silicon (a-Si: H) layer 36 having a thickness of 0 nm and a silicon nitride film are successively deposited.

Thereafter, the silicon nitride film is patterned to form a channel protective film 2 at a position corresponding to the channel portion of the TFT 9.

(3) Third Patterning A 50 nm-thick phosphorus-doped amorphous silicon (n + a-Si: H) layer 37 is deposited by a plasma CVD method, and a metal layer made of, for example, aluminum (Al) is deposited by sputtering. Is deposited. The metal layer and the semiconductor layers 36 and 37
Are collectively patterned under the same mask pattern, thereby forming a signal line lower layer wiring 31, a drain electrode 32 composed of this extended portion, and a source electrode 33.

At this time, the metal layer is patterned by wet etching using a mixed acid of phosphoric acid, nitric acid, acetic acid and water. Next, the semiconductor layers 36 and 37 are patterned by plasma etching. The metal layer is slightly eroded to the inside of the pattern from the edge of the mask pattern by side etching at the time of wet etching,
Semiconductor layer 3 patterned by plasma etching
No such erosion occurs in 6,37. In this manner, under the same mask pattern, the signal line lower wiring 31 having a width of 5 μm and the width of 7 μm including the semiconductor layers 36 and 37 are formed.
Can be obtained at the same time.

(4) Fourth Patterning After depositing the interlayer insulating film 4 made of silicon nitride, the upper and lower interlayer contact holes 41 of the signal lines and the source-pixel electrode contact holes 42 are simultaneously formed.

(5) Fifth Patterning After depositing, for example, ITO as a transparent conductive layer, the signal line upper layer wiring 51 and the pixel electrode 5 are patterned by patterning.
Create 2. The signal line upper layer wiring 51 is entirely formed of a thin line portion 51a having a width of 4 to 5 μm, except for a place where the contact hole 41 is arranged. In the bulging portion 8a of the signal line 8,
A bulged portion 51a which is the same as or slightly smaller than the bulged portion 31a of the signal line lower wiring 31 is provided.

With the matrix array substrate of the above-described embodiment, in the type in which the channel protective film 2 is disposed on the TFT 9, it can be manufactured by five patterning steps and without increasing the manufacturing cost. In addition, disconnection of the signal line 8 can be sufficiently prevented. In addition, an increase in electric capacitance between the scanning line and the signal line can be minimized.

[0043]

According to the matrix array substrate of the present invention, it is possible to easily prevent a reduction in manufacturing yield due to disconnection of a signal line. In addition, an increase in the capacitance between the signal line and the scanning line can be minimized.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a pixel portion of an array substrate 10. FIG.

FIG. 2 is a longitudinal sectional view of a crossing point between a scanning line and a signal line in a direction along the scanning line (AA line in FIG. 1).

FIG. 3 is a direction along a signal line including a bulge of the signal line at a crossing point of a scanning line and a signal line (a line BB in FIG. 1).
FIG.

FIG. 4 is a vertical cross-sectional view of the TFT portion (line CC in FIG. 1).

[Explanation of symbols]

 Reference Signs List 10 array substrate 11 scanning line 11a gate electrode 31 signal line lower wiring 31a bulge of signal line lower wiring 32 drain electrode 33 source electrode 38 semiconductor layer 41 upper and lower interlayer contact holes of signal line 42 contact hole between source electrode and pixel electrode 51 Signal line upper layer wiring (ITO) 51a Swelling portion of signal line upper layer wiring 52 Pixel electrode 8 Signal line 8a Swelling portion

Continued on the front page F-term (reference) 2H092 HA04 HA06 JA26 JA38 JA42 JA44 JB23 JB32 JB33 JB35 KB04 MA05 MA08 MA17 NA15 5C094 AA42 AA43 AA44 BA03 CA19 DA09 EA04 EA05 5F110 AA02 AA16 AA26 BB02 CC03 DD02 FF02 GG02 FF02 GG02 FF02 GG45 HK03 HK09 HK16 HK21 HK25 HK33 HK35 NN02 NN12 NN16 NN24 NN35 NN72 QQ04 QQ05

Claims (5)

[Claims] A plurality of scanning lines arranged substantially in parallel, a plurality of signal lines arranged substantially orthogonal to the scanning lines, and a plurality of matrix-shaped regions defined by the scanning lines and the signal lines; A pixel electrode to be arranged, a thin film transistor arranged for each pixel electrode to switch a signal input from the signal line to the pixel electrode, a gate electrode of the thin film transistor including the scanning line, and a part or extension of the scanning line A first insulating layer covering the first conductive layer, forming a gate insulating film of the thin film transistor, a semiconductor layer including a semiconductor active film of the thin film transistor, the signal line, and a source of the thin film transistor. And a second pattern including a drain electrode and patterned under the same mask pattern as the semiconductor layer.
A matrix layer substrate having a conductive layer, wherein at a place where the signal line passes over the contour of the scanning line, the signal line bulges outward in the width direction and bulges the vicinity of the contour. A width of the signal line in a portion which crosses over the contour line of the scanning line is larger than a width of an adjacent area on the scanning line and an area sandwiching the scanning line. substrate. 2. The matrix array substrate according to claim 1, wherein said bulging portions are provided on both sides in a width direction of said signal line. 3. A width of the signal line in a region where the signal line overlaps with the scanning line is substantially equal to a width of a thin line region in which the signal line extends along the pixel electrode, except for a portion where the signal line crosses. The matrix array substrate according to claim 1, wherein 4. A semiconductor device comprising: a third conductive layer disposed on the second conductive layer and including the pixel electrode; and an auxiliary conductive layer made of the third conductive layer is formed along a signal line made of the second conductive layer. The matrix according to claim 1, wherein the auxiliary conductive layer is arranged as a redundant wiring, and the auxiliary conductive layer bulges outward in the width direction to form a bulge portion that covers the vicinity of the contour at the place where the vehicle crosses the auxiliary conductive layer. Array substrate. 5. The matrix array substrate according to claim 4, wherein the outline of the bulge of the auxiliary conductive layer substantially matches the outline of the bulge of the signal line made of the second conductive layer. .