JP2002084182A - System control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit for system control, in which the output end of an output buffer is fixed at a desired logical level, when a reset signal is active without any pull-down resistor. SOLUTION: The system control circuit 100 comprises a flip-flop FF 12, having an output end connected with the control end of an output buffer 13; an MPX 11 receiving a reset signal *RST and a set signal SA from an external set terminal 21, and delivering control signals pr and rst to the control ends 12a and 12b of the FF, based on a set signal SA for designating an enable signal OE to the output buffer being provided, when the reset signal is active, and then delivering the enable signal from the output end of the FF to the control end of the output buffer; and a buffer input setting means for giving the input end of the output buffer with the desired logical level, when the external set terminal 21 is provided with the set signal SA for instructing enable state of the output buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system control circuit for fixing a predetermined output terminal to a desired logic level when a reset signal is output, and more particularly, to an output terminal connected to an external output terminal and an enable signal connected to the control terminal. And an output buffer which outputs data of an input terminal to an output terminal upon receiving the output signal, and makes the output terminal a high impedance when a disable signal is received at a control terminal, wherein the output buffer is provided when a given reset signal becomes active. And an integrated circuit for controlling the system for setting the output terminal of the system to a desired logic level.

[0002]

2. Description of the Related Art In a system control integrated circuit configured in the form of an LSI or the like, a reset signal * RST may be used to disconnect an input / output terminal or an output terminal of a predetermined input / output port from an internal circuit. FIG. 3 simply shows a circuit around the output terminal 69 to be controlled by the reset signal * RST output as described above. That is, the internal circuit is connected so that output data can be output to the output terminal 69 via the output buffer 61. The output buffer 61 functions as receiving an enable signal when the control signal OE applied to the control terminal goes to a high level, outputs data from an internal circuit to an output terminal 69, and outputs the control signal OE to a low level. , The output terminal 61 is set to high impedance Hi-Z, and the output terminal 69 is electrically disconnected from the internal circuit.

Therefore, when the reset signal * RST is activated, the control signal OE goes low (disable), and when the reset signal * RST is inactive, the control signal OE goes high (enable signal). When the reset signal * RST is activated, the internal circuit can be disconnected from the output terminal 69 when the reset signal * RST is activated. Further, after the reset signal * RST is released and becomes inactive, a predetermined program is performed. If the output terminal 69 is determined to have a desired level, the intended purpose of disconnecting the internal circuit from the output terminal 69 when the reset signal * RST is activated can be achieved. However, in this case, if the output terminal 69 is kept at a high impedance for a certain period of time, a disadvantage such as that described later (FIG. 4) may occur. Therefore, in order to fix the level of the output terminal 69,
A pull-down resistor 68 or the like may be connected to the output terminal 69. The circuit of FIG. 3 is one example. Considering the case where a pull-down resistor or the like is not connected to the output terminal 69 as shown in FIG. 4, when the LSI 460 sets the output terminal 69 to high impedance, the transistor 66 repeatedly turns on and off at that moment. Yes, relay 67
To turn on and off, and may adversely affect the subsequent circuit 65 connected to the relay 67, such as occurrence of abnormal operation.

[0004]

In the above-described output circuit, when the reset signal * RST is activated, the output terminal is not set to high impedance.
A pull-down resistor or pull-up resistor is connected to the output terminal from the outside.However, such output terminals usually have a large number of output ports, so many external parts are required, and mounting is required. This leads to an increase in man-hours and mounting area. In addition, if a countermeasure is made by using a pull-down resistor or a pull-up resistor, a hardware-based connection relationship must be changed each time a change or the like is made, and the circuit configuration is not flexible.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and does not use a pull-down resistor or a pull-up resistor, and sets the output terminal to high impedance when a reset signal * RST is activated. Without
The logic level can be fixed to a desired logic level, the logic level to be fixed can be changed without hardware change, and if desired, a high impedance can be set as before. An object of the present invention is to provide a certain system control integrated circuit.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, according to the present invention, when an output terminal is connected to an external output terminal and an enable signal is received at a control terminal, data at an input terminal is output to an output terminal. A system control for setting an output terminal of the output buffer to a desired logic level when a given reset signal becomes active when the control terminal receives a disable signal to make the output terminal high impedance. Circuit for providing an enable signal to the output buffer when the reset signal becomes active, supplying a desired logic level to an input terminal of the output buffer, and providing the output signal via the output buffer. Output level setting means for setting the output terminal of the buffer to a desired logic level is provided.

With this configuration, when the reset signal becomes active, the output level setting means supplies an enable signal to the output buffer and supplies a desired logic level to the input terminal of the output buffer. The buffer outputs the input logic level to the output terminal, so that the output terminal can be fixed at a desired logic level. Therefore, there is no need to connect a pull-up resistor or a pull-down resistor to the output terminal.

In order to make the present invention more specific, the output level setting means includes a flip-flop having an output terminal connected to a control terminal of the output buffer, and a setting from the reset signal and an external setting terminal. A control signal to a control terminal of the flip-flop based on a setting signal indicating an enable signal to the output buffer, which is given when a reset signal is active,
A multiplexer configured to output an enable signal from an output terminal of the flip-flop to a control terminal of the output buffer; and, when a setting signal instructing enabling of the output buffer is provided to an external setting terminal, the input terminal of the output buffer includes: A buffer input setting means for providing a desired logic level may be provided. The buffer input setting means may be configured to set, for example, a level signal determined by a program as a means for determining output data. According to such a configuration, it is easy to form an integrated circuit to configure a system control integrated circuit.

Further, similarly to the above, the output level setting means inputs a flip-flop having an output terminal connected to the input terminal of the output buffer, a reset signal and a setting signal from an external setting terminal, A control signal is supplied to a control terminal of the flip-flop based on a setting signal indicating the desired logical level when the reset signal is active, and a desired logical level is applied from the output terminal of the flip-flop to the input terminal of the output buffer. It may be configured to have a multiplexer for outputting, and enable signal setting means for supplying an enable signal to the control terminal of the output buffer when the reset signal is active. In addition,
This enable signal setting means can be configured to set a level signal determined by a program, for example, as an input / output setting signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below with reference to the accompanying drawings, taking an example of a system control integrated circuit. FIG. 1 is a block diagram showing a system control integrated circuit according to the first embodiment, and FIG. 2 is a block diagram showing a system control integrated circuit according to the second embodiment. In the system control integrated circuits 100 and 200 of FIG. 1 or FIG. 2, the multiplexer 11 (hereinafter, referred to as MPX11)
And a flip-flop 12 (hereinafter referred to as FF12)
, An output buffer 13 and an input buffer 14. When the reset signal * RST is active, the input / output terminal 29 of the input / output port is fixed at a desired logic level. The reset signal * RST is supplied from another circuit to the system control integrated circuits 100 and 200 shown in FIG. 1 or 2 when the power is turned on.

Embodiment 1 In the system control integrated circuit 100 shown in FIG. 1, the MPX 11 outputs a reset signal * R
ST and a setting signal SA applied to the external setting terminal 21 are inputted, and the control signal pr and the control signal rst are respectively set to F.
This is applied to the control ends 12a and 12b of F12. In this case, when the reset signal * RST is active (in this example, low level (L level)), the logical level of the setting signal SA applied to the external setting terminal 21 is output from the output terminal Q of the FF 12 as the control signal OE. It is provided to the control end of the output buffer 13. Therefore, in this example, the reset signal * R
When ST is active (L level), the setting signal S
By setting A to a high level (H level), the output terminal Q of the FF 12 is set to the high level, that is, the enable signal is set to the high level, and the output data of the output buffer 13 is set to the low level (L level). The terminal 29 can be fixed at a low level (L level). In this case, the output data may be set internally or may be supplied from any of the external terminals. If necessary, the input / output terminal 29 can be fixed at the H level by setting the output data to the H level, and the input / output terminal 29 can be set to the high impedance (Hi) by setting the setting signal SA to the L level. -Z).

If the operation of the circuit of FIG. 1 described above is shown as a truth table, it can be shown as the following truth table 1. That is,

Truth Table 1: To MPX * Input of RST L LH H Control signal pr HL HH input to external setting terminal 21 L HL H FF Output of control signal rst L H H H FF Output terminal Q L H Previous value Previous value

As described above, the system control integrated circuit 10
0, the reset signal * RST is active (L
(Level), the input / output terminal 29 can be set to the H level, the L level, or the Hi-Z, without any modification in hardware, and can be freely handled in software. For example, this is specifically shown in FIG.
Is applied to the LSI 460, the function of the system control integrated circuit 100 is applied to the LSI 460, and the setting signal SA
Is set to the H level and the output data is set to the L level. When the reset signal * RST is active, the input / output terminal 69 is fixed at the L level, the transistor 66 is turned off, and the relay 67 is abnormally driven. Never. After the reset signal * RST becomes inactive (H level), the output data is changed to H at appropriate timing.
When the level is set, the transistor 66 is turned on from that point on, and the relay 67 is driven to operate, for example, the subsequent circuit 65 normally. In this case, the output data can be easily set by a program or the like. Incorporation of the circuit as shown in FIG. 1 when forming an integrated circuit is advantageous in terms of man-hours and occupied area as compared with the case where many external resistors are used. .

Embodiment 2 In the system control integrated circuit 200 of FIG. 2, when the reset signal * RST is active, the logic level of the input of the output buffer 13 is set by the setting signal SB applied to the external setting terminal 22. The control signal OE for the output buffer 13 is externally supplied via the input / output setting terminal 23. Therefore, as compared with the system control integrated circuit 100 in FIG. 1, the output buffer 13 has a relationship in which the terminal for providing the control signal OE and the terminal for providing output data are interchanged. That is, when the reset signal * RST is active, for example, the input / output setting signal SK applied to the input / output terminal 23 is set to the H level and the setting signal SB is set to the L and H levels. 29 are fixed at L and H levels, respectively. If the input / output setting signal SK is set to L level, the input / output terminal 29 becomes Hi-Z. Therefore, the system control integrated circuit 200 has the same advantages as the system control integrated circuit 100.

[0016]

The system control circuit according to the present invention is constructed as described above. When the reset signal becomes active, the output level setting means supplies the enable signal to the output buffer and the input terminal of the output buffer. The output buffer outputs the input logic level to the output terminal, so that the output terminal can be fixed at the desired logic level. Therefore,
The output terminal can be fixed to a desired logic level without connecting a pull-up resistor or a pull-down resistor to the output terminal of the output buffer, and the logic level to be fixed can be changed without hardware change. For example, high impedance can be set as in the prior art, and it is possible to flexibly respond to various requests. Further, since no pull-up resistor or pull-down resistor is required, the load is small and advantageous in terms of man-hour and occupied area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a system control integrated circuit according to the present invention;

FIG. 2 is a block diagram showing a second embodiment of a system control integrated circuit according to the present invention;

FIG. 3 is a circuit diagram showing the vicinity of an output buffer of a conventional system control integrated circuit.

FIG. 4 is a diagram showing a circuit example driven by the system control integrated circuit of FIG. 3;

[Explanation of symbols]

 11 multiplexer (MPX) 12 flip-flop (FF) 12a, 12b control terminal 13 output buffer 14 input buffer 21, 22 external setting terminal 25 control signal input terminal 29 input / output terminal * RST reset signal pr, rst, OE control signal SA, SB setting signal SK I / O setting signal 100, 200 System control integrated circuit pr FF preset input rst FF reset input

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Toyoaki Yokoi 2-93-2 Nakamachi, Musashino-shi, Tokyo F-term in Yokogawa Electric Corporation (reference) 5J056 AA04 BB54 BB57 BB58 CC00 CC14 DD02 FF07 FF08 GG11 GG12

Claims (3)

[Claims] An output terminal is connected to an external output terminal, and outputs data of an input terminal to an output terminal when receiving an enable signal at a control terminal, and makes the output terminal high impedance when receiving a disable signal at the control terminal. A system control circuit that has an output buffer, and sets an output terminal of the output buffer to a desired logic level when a given reset signal is activated, wherein when the reset signal is activated, Output level setting means for supplying an enable signal to the output buffer, supplying a desired logic level to an input terminal of the output buffer, and setting an output terminal of the output buffer to a desired logic level via the output buffer. A circuit for controlling a system, comprising: 2. An output level setting means, comprising: a flip-flop having an output terminal connected to a control terminal of the output buffer; a reset signal and a setting signal from an external setting terminal; A multiplexer that supplies a control signal to a control terminal of a flip-flop based on a setting signal indicating an enable signal to the output buffer, and outputs an enable signal from an output terminal of the flip-flop to a control terminal of the output buffer. 2. A system control system according to claim 1, further comprising a buffer input setting means for applying said desired logic level to an input terminal of said output buffer when a setting signal for instructing enabling of said output buffer is applied to an external setting terminal. circuit. 3. The output level setting means receives a flip-flop having an output terminal connected to an input terminal of the output buffer, a reset signal and a setting signal from an external setting terminal, and outputs a reset signal when the reset signal is active. A multiplexer that supplies a control signal to a control terminal of a flip-flop based on a setting signal indicating the desired logic level, and outputs a desired logic level from an output terminal of the flip-flop to an input terminal of the output buffer; 2. The system control circuit according to claim 1, further comprising enable signal setting means for providing an enable signal to a control terminal of the output buffer when the reset signal is active.