JP2002083004A - Method, device, and program for cell arrangement of lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an arrangement result of good quality by combining a partitioning-based system and a resistive network system and supplementing their weak points. SOLUTION: This device is equipped with a partitioning-based arrangement processing means 2 which assigns respective cells to areas obtained by dividing a chip and determines tentative arrangement of the cells and a resistive-network system arrangement processing means 4 which assumes that virtual nets are extended to the respective cells from the tentative arrangement and the nets are spring and then determines the arrangement of the cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method, an apparatus, and a program for improving a cell arrangement on an LSI (Large Scale Integrated Circuit).

In the design of an LSI, first, an AND (AN
D) Determine connections (nets) between cells such as circuits and OR (OR) circuits, etc., and cells (logic design), then determine the positions of the cells on the chip (arrangement), and finally, Is determined (wiring) how to draw the net. In addition, 1
One cell usually includes a plurality of transistors, such as two to four transistors.

[0003]

2. Description of the Related Art A method called partitioning base is often used in arranging LSI cells, and another method called resistive network is used as an LSI cell arranging method. Exists. Hereinafter, these methods will be described.

(1): Description of Partitioning Base Arrangement Method In a system called partitioning base, it is repeated to divide a chip and allocate cells to each of the divided blocks (areas). Finally, when each block is finely divided to include only about one cell, the position of the cell is determined.

FIG. 6 is an explanatory diagram of a conventional partitioning-based arrangement method. In FIG. 6, the entire chip is first divided into two as a first cut. The dividing line is called a cut line. Then, all cells are allocated to each of two regions (blocks). As a criterion for sorting the cells, as a result of dividing the cells into two regions, the number of nets existing over the two regions is taken as a cost, and a grouping method that minimizes this cost is adopted (min -cut method) is often used. An FM method or the like is known as an algorithm for performing such processing.

[0006] At this time, on condition that the total area of the cells to be divided into the two regions falls within a certain range, the operation is performed so that the cells do not shift to either region.

For example, the area of two regions is S1,
Assuming that the total values of the areas of the cells allocated to S2 and the area are s1 and s2, respectively, the following condition must be satisfied.

| S1 / S1−s2 / S2 | ≦ α (α is a positive constant) Similarly, as the second cut, the division is repeated in the order of horizontal and then vertical to obtain the cell Was determined.

(2): Description of the resistive network method As another method that can be used for arranging cells of LSI, there is a method called a resistive network method (for example, refer to the reference document Chung-Kuan Cheng and Ernest S. et al.
Kuh. Module Placement Based on Resistive Network O
ptimization.IEEE Trans. On Computer-Aided Design,
3 (3): 218-225, July 1984 and reference H. Eisenmann an
d FM Johannes. Generic Global Placement and Floor
planning. ACM / IEEE Design Automation Conference, Vo
l.35, pp.269-274, 1998.).

In this method, the net is regarded as a spring, and a cell position which minimizes the mechanical energy of the spring is obtained. FIG. 7 is an explanatory diagram of a conventional resistive network system, and FIG. 7A is an explanatory diagram of a resistive network system. 7A, a net between the external terminal 11 and the cell A is regarded as a spring 21, a net between the external terminal 12 and the cell B is regarded as a spring 22, and a net between the cells A and B is regarded as a spring 23. , Cell B and other nets are regarded as springs 24, 25, 26.

However, this alone does not consider the area of the cell (the cell is assumed to be a point) and causes an overlap. Therefore, it is considered that a repulsive force is generated in a portion where the cell overlaps. Then, an arrangement that minimizes the mechanical energy of the spring with the repulsive force applied thereto is determined. FIG.
(B) is a description of a method in which the cell area is considered. FIG.
In (b), the resistive network method is used to consider the cell area. The force of the net of the cell A is F21, the force of the net of the cell B is F22, F23, and the cells A and B overlap. The repulsive forces generated by this are F1 and F2, respectively. In this state, an arrangement that minimizes the mechanical energy of the spring is determined.

Also, when an area is difficult to route due to congestion of the net, similarly, by assuming a repulsive force to the cells in the area, the cells are expelled from the area to improve the wiring property. Can be.

(3): Comparison between the partitioning-based method and the resistive network method-Both the partitioning-based method and the resistive network method have advantages and disadvantages, respectively. The advantages of the partitioning-based method are that processing can be performed quickly, and a recent improvement in the partitioning algorithm results in a net having a short net line length. The disadvantage is that it is difficult to predict the final placement result of the cells at the initial stage of chip division, and it is difficult to determine whether the wiring property is good or bad when the processing is continued as it is.

For example, FIG. 8 is an explanatory diagram of a problem of the conventional partitioning-based system. In FIG. 8, if a region having a larger number of nets than other regions is generated during the progress of the division, it becomes difficult to wire the region. However, at the initial stage of the division, it is impossible to know whether or not there is a region having a larger number of nets than others. For this reason, an area where wiring is difficult may occur.

The advantages of the resistive network method are that the processing speed is high and the final cell arrangement result can be predicted. The disadvantage is that it is difficult to estimate the wiring length because the net is approximated as a spring between two cells.
In the LSI, the wiring can be drawn only in the vertical and horizontal directions, and cannot be formed in an oblique direction. Therefore, the net length is | x |
+ | Y |.

FIG. 9 is an explanatory diagram of the line length estimation of the conventional resistive network system. In FIG. 9, the wiring lengths of the net A and the net B are both equal to 2L. However, when calculating as the elongation of the spring by the resistive network method, the line length of the net B is longer because square-root (x ² + y ² ) is the length.

Further, when there is a net connected to three or more cells, this is approximated by a combination of springs between the two cells. Therefore, the solution with the minimum mechanical energy is not necessarily the line length. It did not give the minimum solution.

FIG. 10 is an explanatory diagram of a net connected to three or more cells by the conventional resistive network method. In FIG. 10, a cell A penetrates a cell B and is connected to a cell C by one net. In the resistive network method, a plurality of springs 31, 32, 3
3, the adjustment of the strength of these springs becomes complicated, and the solution with the minimum mechanical energy does not always give the solution with the minimum line length.

As described above, the partitioning-based method and the resistive network method have advantages and disadvantages, respectively. Therefore, a method in which the partitioning-based method and the resistive network method are combined to take advantage of the respective advantages can be considered.

For example, there is known a method in which an approximate position is determined by a resistive network method, and the solution is given as an initial solution of a partitioning algorithm. However, recent partitioning algorithms are designed to search from the initial solution to a solution that is significantly different from the initial solution in order to find the optimal solution. It will be different. If the search range of the solution is narrowed to avoid this, the optimization ability is reduced, and the disadvantage that the line length is increased remains.

[0021]

The above-mentioned prior art has the following problems.

(1): In the partitioning-based method, it is difficult to predict the final arrangement result of cells at an initial stage of chip division, and when processing is advanced, an area where wiring is difficult occurs. There was sometimes.

(2) The resistive network method has a problem that the wiring length is difficult to estimate because the net is approximated as a spring between two cells.

(3): A method of determining an approximate position by the resistive network method and giving the solution as an initial solution of the partitioning algorithm narrows the search range of the solution so as not to be largely different from the initial solution. In this case, the optimization ability is reduced, and the disadvantage that the wire length is increased remains.

An object of the present invention is to solve such a conventional problem, to combine a partitioning-based method and a resistive network method, and to obtain a high-quality arrangement result by compensating for each disadvantage. And

[0026]

FIG. 1 is a block diagram of an apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes an input unit, 2 denotes a partitioning-based arrangement processing unit, 3 denotes an extraction unit, and 4 denotes a resistive network type arrangement processing unit.

The present invention has the following configuration in order to solve the above-mentioned conventional problems.

(1): Partitioning-based placement processing means 2 for allocating each cell to an area obtained by dividing a chip and determining provisional placement of each cell, and a virtual net is set up in each cell from the provisional placement. And a resistive network type arrangement processing means 4 which determines the arrangement of cells by considering the net as a spring.

(2): An input means 1 for inputting a cell arrangement result, and from the position of each cell in the inputted arrangement result, it is assumed that a virtual net is stretched to each cell, and the net is formed as a spring. And a resistive network type arrangement processing means 4 for deciding the arrangement of cells in consideration.

(3) Extraction means 3 for extracting a region where a net is locally congested or a net having a large signal transmission delay is provided, and only the extracted region is described in the above (2).
Resistive network type arrangement processing means 4 described
To perform the placement processing.

(Operation) The operation based on the above configuration will be described.

Each cell is allocated to a region obtained by dividing the chip by the partitioning-based arrangement processing means 2 and a provisional arrangement of each cell is determined. Assuming that the net is stretched, the cell arrangement is determined considering the net as a spring. For this reason, even if a region where the nets are concentrated occurs in the partitioning-based method, the placement result can be improved by the resistive network method, and a high-quality placement result can be obtained at high speed.

The cell arrangement result is inputted by the input means 1, and it is assumed that a virtual net is extended to each cell from the position of each cell in the inputted arrangement result. The processing unit 4 determines the cell arrangement by considering the net as a spring. Therefore, by inputting an arbitrary arrangement position, the arrangement result can be improved by the resistive network method, and a high-quality arrangement result can be obtained at high speed.

Further, the extraction means 3 extracts a locally congested area of the net or a net area having a large signal transmission delay, and uses only the extracted area as a resistive network type placement processing means. At step 4, an arrangement process is performed. For this reason, a processing result is small, and an arrangement result of good quality can be obtained at higher speed.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, it is assumed that there is a net (virtual net) connecting a provisional arrangement position of a cell and the cell, and the cell arrangement of an LSI is obtained by a resistive network method.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(1) Description of LSI Cell Arrangement Apparatus FIG. 1 is an apparatus configuration diagram of the present invention. In FIG. 1, LS
The cell arrangement apparatus of I includes an input unit 1, a partitioning-based arrangement processing unit 2, an extraction unit 3, and a resistive network type arrangement processing unit 4.

The input means 1 is for inputting an arbitrary arrangement position or the like of a cell. The partitioning-based arrangement processing means 2 performs cell arrangement processing based on a partitioning-based method. The extraction means 3 extracts a region where the number of nets exceeds a certain value (an area where wiring is congested), a region of a net where signal transmission delay is large, and the like. The resistive network type arrangement processing means 4 has a virtual net generation means and performs a cell arrangement processing by the resistive network method.

(2) Description of LSI Cell Arrangement Processing: Description of Case of Provisional Arrangement by Partitioning-Based Method FIG. 2 is an explanatory diagram of LSI cell arrangement processing. Hereinafter, description will be given according to the processing S1 to the processing S3 in FIG.

S1: First, the partitioning-based arrangement processing means 2 obtains a provisional arrangement of cells by a partitioning-based method, determines a provisional position of the cell,
Move to processing S2.

S2: Next, the virtual net generation means considers that there is a net connecting each cell to the provisional position of the cell (generates a virtual net), and executes processing S3.
Move on to

S3: The arrangement processing means 4 of the resistive network system obtains the cell arrangement by the resistive network system.

Since the cells are attracted to the provisional positions by adding the virtual nets as described above, the arrangement positions do not largely change. If the virtual net does not exist, the result is the same as when the resistive network method is used from the beginning, and the cell is placed at a completely different position.

Further, as in the conventional resistive network system, a repulsive force is generated in a region where the number of nets exceeds a certain value and wiring is considered to be difficult. Can be kicked out of the area. In this way, even if a region where the nets are concentrated occurs in the partitioning-based arrangement, the arrangement result can be improved.

As described above, by improving the result obtained by the partitioning-based method by using the resistive network method, it is possible to compensate for each disadvantage and obtain a high-quality cell arrangement result.

Description of Input of Arbitrary Arrangement Position Cell Improving Unit by Registive Network System (Registration Network Arrangement Processing Unit 4)
Does not need to work as part of the deployment system, only the improvement can operate independently. in this case,
Using the arrangement position of an arbitrary cell (for example, a position obtained by an arrangement processing unit other than the partitioning-based method) as an input, a virtual net is added and the resistive network method is applied. In this way, a cell placement improvement system using the resistive network method can be created.

Description of Improvement of Cell Arrangement of Only Necessary Portion It is not necessary to improve the cell arrangement by the resistive network method for all data. If there is an area where the wiring is congested locally (part of the chip), the area is extracted by the extracting means 3 and only that area is input to the resistive network type arrangement processing means 4,
Cell arrangement can be improved by the resistive network method.

Similarly, when it is desired to improve a part of the net in which the delay is large because the net is too long, the extracting means 3 extracts a part where the slack value is equal to or less than a predetermined value, and registers only that part. Active network type arrangement processing means 4
To improve the cell arrangement by the resistive network method.

Here, the slack is a value indicating a margin of how much a delay of a certain net can be increased within a range of a timing constraint. That is, the time at which the signal must arrive at this time at worst (target delay) minus the time at which the signal actually arrives (actual delay) (slack = target delay−actual delay).

(3): Description of processing using min-cut method In the case of using the min-cut method as a partitioning algorithm, in the phase of improving the cell arrangement by the resistive network method, the degree of wiring congestion is a reference. A repulsive force is generated for cells in an area higher than the value. By making the spring strength of the virtual net larger than that of the normal net, the result of the partitioning-based arrangement is respected in areas other than the area where the net is crowded and cannot be routed, and the resistive network method is used in areas where wiring is difficult. This allows the cell density to be reduced.

Next, the processing when the min-cut method is used as the partitioning algorithm will be described with reference to the drawings. FIG. 3 is an explanatory diagram of an arrangement phase based on the partitioning-based system, FIG. 4 is an explanatory diagram of a virtual net generation phase, and FIG. 5 is an explanatory diagram of an improvement phase according to the resistive network system. Hereinafter, description will be given according to the processing S11 to the processing S23 of FIGS.

Description of the arrangement phase by the partitioning-based method (partitioning-based arrangement processing means 2) S11: All blocks (areas) are divided, and the process proceeds to S12.

S12: Apply the FM algorithm to all the blocks, determine which of the divided blocks the cell inside the block belongs to, and proceed to processing S13.

S13: It is determined whether the block is sufficiently small (for example, the number of cells in one block is 1 or 2). In this determination, if the block is sufficiently small, the process proceeds to the next phase (process S14), and if not, the process returns to process S11.

Description of Virtual Net (by Virtual Net Generation Means) Generation Phase S14: The variable “i” is set to 1 and the process proceeds to S15.

S15: The i-th cell is taken out and the process S
Move to 16.

S16: A net (virtual net) is generated between the cell i and the center point of the block in which the cell i is located, and the process proceeds to step S17.

S17: The variable “i” is set to i + 1, and the processing S
Move to 18.

S18: It is determined whether i is larger than the number of cells. In this determination, if i is larger than the number of cells, the process proceeds to the next phase (process S19), and if not, the process returns to process S15.

Description of the improvement phase by the resistive network method (the arrangement processing means 4 of the resistive network method) S19: Determine the weight of the net (spring strength) (the strength of the virtual net is ten times that of a normal net) ), And then proceeds to step S20.

S20: Calculate the wiring congestion degree, and process S21
Move on to

S21: It is determined whether or not there is a region where the degree of wiring congestion is higher than the reference value. If it is determined that there is a region where the wiring congestion is higher than the reference value, the process proceeds to step S22
The process proceeds to step S3, and if not, the process ends.

S22: The repulsive force due to the wiring congestion is calculated (the repulsive force is increased), and the process proceeds to S23.

S23: The cell arrangement that minimizes the mechanical energy of the spring is determined, and the process returns to step S20.

(4): Description of Installation of Program The input unit 1, the partitioning-based arrangement processing unit 2, the extracting unit 3, the arrangement processing unit 4 of the resistive network system, and the like can be constituted by a program. C
PU) and are stored in the main memory. This program is generally processed by a computer. This computer is configured by hardware such as a main control unit, a main memory, a file device, a display device, and an input device such as a keyboard.

The program of the present invention is installed on this computer. This installation is performed on portable recording (storage) media such as floppy disks, magneto-optical disks, etc.
These programs are stored and installed in a file device provided in the computer via a drive device for accessing a recording medium provided in the computer or via a network such as a LAN. You. Then, program steps necessary for processing are read out from the file device to the main memory, and are executed by the main control unit.

[Supplementary Note 1] (Supplementary Note 1) A partitioning-based placement process for allocating each cell to an area obtained by dividing a chip is performed, a provisional placement of each cell is determined, and the provisional placement is assigned to each cell. A cell placement method for an LSI, characterized by performing a resistive network type placement process in which a virtual net is regarded as being stretched and a cell is placed by considering the net as a spring.

(Supplementary Note 2) A cell placement result is input, and a virtual net is assumed to be stretched to each cell from the position of each cell in the input placement result, and the net is considered as a spring, and A method of arranging cells of an LSI, comprising performing a resistive network type arrangement process for determining an arrangement.

(Supplementary Note 3) Partitioning-based placement processing means for allocating each cell to an area obtained by dividing a chip and determining provisional placement of each cell, and that a virtual net is set up in each cell from the provisional placement. A resistive network type arrangement processing means for deciding cell arrangement by considering the net as a spring.
Cell placement equipment.

(Supplementary Note 4) Input means for inputting a cell arrangement result, and a virtual net is assumed to be stretched to each cell from the position of each cell in the input arrangement result, and the net is considered as a spring. And a resistive network type arrangement processing means for deciding the cell arrangement by means of an LSI.

(Supplementary note 5) An extraction means for extracting a region where a net is locally congested is provided, and only the extracted region is subjected to arrangement processing by the arrangement processing means of the resistive network system. LSI described in Appendix 4
Cell placement equipment.

(Supplementary note 6) An additional means characterized by comprising extraction means for extracting a net having a large signal transmission delay, and arranging only the extracted area by the arrangement processing means of the resistive network system. An LSI cell arrangement apparatus as described in the above.

(Supplementary Note 7) It is assumed that each cell is allocated to an area obtained by dividing a chip, a partitioning-based arrangement processing means for determining a provisional arrangement of each cell, and that a virtual net is set up in each cell from the provisional arrangement. A program for causing a computer to function, or a computer-readable recording medium that records the program, as a resistive network type arrangement processing unit that determines the arrangement of cells by considering the net as a spring.

(Supplementary Note 8) An input means for inputting a cell arrangement result, and a virtual net is assumed to be attached to each cell from the position of each cell in the input arrangement result, and the net is considered as a spring. A program for causing a computer to function, or a computer-readable recording medium on which the program is recorded, as a resistive network type arrangement processing means for deciding the arrangement of cells.

[0075]

As described above, the present invention has the following effects.

(1): Each cell is allocated to an area obtained by dividing the chip by the partitioning-based arrangement processing means, and the cells are provisionally arranged, and the arrangement processing means of the resistive network system transfers the cells from the provisional arrangement position to each cell. The placement of cells is determined by considering the net as a spring, assuming that the virtual net is stretched, so even if there is an area where the net is concentrated by the partitioning-based method, it is arranged by the resistive network method The result can be improved, and a good quality placement result can be obtained at high speed.

(2): A cell arrangement result is inputted by the input means, and it is considered that a virtual net is extended to each cell from the position of each cell in the inputted arrangement result, and the resistive network system is used. Since the placement processing means determines the placement of cells by considering the net as a spring, it is possible to improve the placement result by the resistive network method by inputting an arbitrary placement position, and obtain high-quality placement results at high speed. Can be.

(3): A region where a net is locally congested or a region of a net having a large signal transmission delay is extracted by the extraction means, and only the extracted region is subjected to the resistive network type arrangement processing. Since the arrangement processing is performed by the means, the arrangement area is small, and a high-quality arrangement result can be obtained more quickly.

(4): Partitioning-based placement processing means for allocating each cell to an area obtained by dividing a chip and determining provisional placement of each cell, and that a virtual net is set up in each cell from the provisional placement. Considering the net as a spring, as a resistive network type arrangement processing means for deciding cell arrangement, a program for causing a computer to function or a computer-readable recording medium on which the program is recorded, the In this case, it is possible to easily provide an LSI cell arranging method and apparatus which can obtain high-quality arranging results at a high speed by being installed in the LSI.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an apparatus of the present invention.

FIG. 2 is an explanatory diagram of an LSI cell arrangement process according to the embodiment;

FIG. 3 is an explanatory diagram of an arrangement phase according to a partitioning-based scheme in the embodiment.

FIG. 4 is an explanatory diagram of a virtual net generation phase in the embodiment.

FIG. 5 is an explanatory diagram of an improvement phase according to the resistive network method in the embodiment.

FIG. 6 is an explanatory diagram of a conventional partitioning-based arrangement method.

FIG. 7 is an explanatory diagram of a conventional resistive network system.

FIG. 8 is an explanatory diagram of a problem of a conventional partitioning-based system.

FIG. 9 is an explanatory diagram of a line length estimation in a conventional resistive network system.

FIG. 10 is an explanatory diagram of a net connected to three or more cells by a conventional resistive network method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input means 2 Partitioning-based arrangement processing means 3 Extraction means 4 Resistive network type arrangement processing means

Claims (4)

[Claims] 1. A partitioning-based arrangement process for allocating each cell to an area obtained by dividing a chip to determine a provisional arrangement of each cell, and from the provisional arrangement, it is assumed that a virtual net is provided in each cell. And performing a resistive network type arrangement process for deciding cell arrangement by considering the net as a spring. 2. A partitioning-based placement processing means for allocating each cell to an area obtained by dividing a chip and determining a provisional placement of each cell, and assuming that a virtual net is extended to each cell from the provisional placement. And a resistive network type arrangement processing means for deciding cell arrangement by considering the net as a spring. 3. An input means for inputting a result of arranging cells, and a cell is regarded as a spring by assuming that a virtual net is stretched in each cell from the position of each cell in the inputted arrangement result. Characterized by comprising a resistive network type arrangement processing means for determining the arrangement of
I cell placement device. 4. A partitioning-based arrangement processing means for allocating each cell to an area obtained by dividing a chip and determining a provisional arrangement of each cell, and assuming that a virtual net is extended to each cell from the provisional arrangement. A program for causing a computer to function as a resistive network type placement processing unit that determines the placement of cells by considering a net as a spring.