JPS63153851A - Lsi lay out process - Google Patents
Lsi lay out processInfo
- Publication number
- JPS63153851A JPS63153851A JP61300831A JP30083186A JPS63153851A JP S63153851 A JPS63153851 A JP S63153851A JP 61300831 A JP61300831 A JP 61300831A JP 30083186 A JP30083186 A JP 30083186A JP S63153851 A JPS63153851 A JP S63153851A
- Authority
- JP
- Japan
- Prior art keywords
- blocks
- wirings
- wiring
- lsi
- repulsion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000008878 coupling Effects 0.000 abstract description 4
- 238000010168 coupling process Methods 0.000 abstract description 4
- 238000005859 coupling reaction Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明はLSI内部に配置される複数の機能ブロックの
配置方法、特に各機能ブロック相互間の最適配置を行な
うLSIのレイアウト法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for arranging a plurality of functional blocks arranged inside an LSI, and particularly to an LSI layout method for optimally arranging each functional block.
[従来の技術]
従来、この種のLSIレイアウト法は、設計者が設計時
の機能ブロック間の結合度の情報から配置を指示するか
、或いは各機能ブロック間の配線量、遅延許容時間1機
能ブロックの大きさ等を調べ、その情報によって人手に
てレイアウトを行っていた。[Prior Art] Conventionally, in this type of LSI layout method, the designer instructs the layout based on information on the degree of coupling between functional blocks at the time of design, or the amount of wiring between each functional block and the allowable delay time per function. The size of the blocks was investigated and the layout was done manually based on that information.
[発明が解決しようとする問題点]
上述した従来のLSIレイアウト法は、各機能ブロック
の配置を人手によって行っていたため、自動化ができず
、製造時間の増加を招くという欠点がある。[Problems to be Solved by the Invention] The above-described conventional LSI layout method has the drawback that each functional block is arranged manually, and therefore cannot be automated, resulting in an increase in manufacturing time.
また、レイアウトを行な−う人の熟練度等の個人差が生
じてしまうという欠点も同時に存在する。Furthermore, there is also the drawback that there are individual differences in the skill level of the person doing the layout.
本発明の目的は前記問題点を解消するしS■レイアウト
法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an S2 layout method.
[問題点を解決するための手段]
本発明はLSIの内部に配置される特定の動作を行なう
回路の集合である機能ブロックの配置方法において、各
機能ブロックの大きさ、機能ブロック間の配線量、遅延
許容時間等のパラメータを力学的な力にモデル化し、そ
の力の強弱によって最適配置を決定することを特徴とす
るLSIレイアウト法である。[Means for Solving the Problems] The present invention provides a method for arranging functional blocks, which are a collection of circuits that perform specific operations, arranged inside an LSI. This is an LSI layout method characterized by modeling parameters such as allowable delay time into dynamic forces and determining the optimal layout based on the strength of the forces.
[実施例] 次に、本発明の実施例について図面を用いて説明する。[Example] Next, embodiments of the present invention will be described using the drawings.
第2図は本発明の手法によって配置すべき機能ブロック
とその相互間の配線を示した例である。FIG. 2 is an example showing the functional blocks to be arranged by the method of the present invention and the interconnections between them.
この例では機能ブロック1,2.3.4を配置するもの
とする。この機能ブロック1,2間には5本、2,3間
には3本、1.3間には2本、3゜4間には2本のそれ
ぞれ配線13.14.15.16を施すものとする。ま
た各配線13.14.15.16には特に遅延時間に厳
しい配線がないものとする。In this example, functional blocks 1, 2, 3, and 4 are placed. There are 5 wires between functional blocks 1 and 2, 3 wires between 2 and 3, 2 wires between 1.3, and 2 wires between 3° and 4, respectively. shall be taken as a thing. Further, it is assumed that each of the wirings 13, 14, 15, and 16 does not include any wiring that has particularly severe delay times.
第1図は第2図で示した機能ブロックの関係を力学的モ
デルで表わしたものである。各機能ブロック5〜8は大
きざに対応した円で表わされており、各ブロック5〜8
間にはその円に対応した斥力を持つ。各ブロック間の配
線はブロック間を接続するバネにおきかえられており、
その長さは接続されているブロックの半径の和に等しく
、バネ定数は接続数に遅延許容度の重みをかけたものの
総和とする。第2図において、5.6.7.8は機能ブ
ロック1,2.3.4をモデル化したものを表わしてお
り、各ブロック間の配線はバネ9゜io、 11.12
によって表わされている。FIG. 1 shows the relationship between the functional blocks shown in FIG. 2 using a mechanical model. Each functional block 5 to 8 is represented by a circle corresponding to the size.
There is a repulsive force between them that corresponds to the circle. The wiring between each block has been replaced with a spring that connects the blocks.
Its length is equal to the sum of the radii of connected blocks, and its spring constant is the sum of the number of connections multiplied by the delay tolerance weight. In Figure 2, 5.6.7.8 represents a model of functional blocks 1 and 2.3.4, and the wiring between each block is a spring 9°io, 11.12
It is represented by
ここで、各バネ9〜12は遅延の重みが等しいので、バ
ネ9は5に、バネ10は3に、バネ11は2k。Here, each spring 9 to 12 has the same delay weight, so spring 9 has a weight of 5, spring 10 has a weight of 3, and spring 11 has a weight of 2k.
バネ12は2にのバネ定数をもつと仮定できる。また各
ブロック5〜8間はその半径の和に比例した斥力をもつ
ように設定されている。これは多くの配線が集中するブ
ロックに他のブロックがかたまり配線時に配線領域がな
くなってしまうのを防止するためである。各ブロック5
〜8間にはブロック間の距離をXとすると、F1=−k
xの力をこのモデルでは受け、またブロック間の斥力は
F2=]巧 (lは斥力係数)となる。It can be assumed that spring 12 has a spring constant of 2. Further, each block 5 to 8 is set to have a repulsive force proportional to the sum of their radii. This is to prevent other blocks from clumping together in a block where many wirings are concentrated and running out of wiring area during wiring. each block 5
~8, if the distance between blocks is X, then F1=-k
This model receives the force x, and the repulsive force between the blocks is F2=] (l is the repulsive force coefficient).
これらの力の平衡のとれる点まで受ける力の方向へ各ブ
ロックを移動し、平衡のとれる点まで移動すると、第3
図となる。この第3図が求める配置により、これを実機
能ブロックへ置きかえることにより第4図に示す各ブロ
ック1〜4の配置が完了する。すなわち、本発明のレイ
アウト法は、各機能ブロック間の結合の強さをその間の
配線量とその配線に許容されている遅延時間によって重
みづけされた引力にモデル化し、また各機能ブロックを
大きざに対応した半径の円で表現し、その円の大きざに
対応した斥力を機能ブロック相互間にもたせることによ
って、その力の平衡点を計韓によって求め、自動的に最
適配置を求めるものである。Move each block in the direction of the forces it receives until the point where these forces are balanced, and when you move to the point where the blocks are balanced, the third
It becomes a diagram. By replacing this arrangement with the actual functional blocks according to the arrangement required by this FIG. 3, the arrangement of each block 1 to 4 shown in FIG. 4 is completed. In other words, the layout method of the present invention models the strength of the coupling between each functional block as an attractive force weighted by the amount of wiring between them and the delay time allowed for that wiring, and also By expressing it as a circle with a radius corresponding to the size of the circle, and creating a repulsive force between the functional blocks that corresponds to the size of the circle, the equilibrium point of the force is determined by measuring, and the optimal arrangement is automatically determined. .
ブロック間の配線に遅延時間の厳しい配線がある場合に
は、その配線に対応したモデルのバネ定数を増加させる
ことによって対応することができる。If there is a wiring between blocks that has a severe delay time, this can be dealt with by increasing the spring constant of the model corresponding to that wiring.
[発明の効果]
以上説明したように本発明はしSI内に配置すべき機能
ブロックを、ブロックの大きざ、ブロック間の配線数、
配線遅延許容度をパラメータとして力学的なモデルへ置
きかえ、相互間の力の平衡をとることによって配置をす
ることによって、これまで数値化することが困難だった
ブロック間の結合度を数値化でき、計算によって配置す
ることができるため、これまで人手によって配置してい
たものを自動化することが可能となる。[Effects of the Invention] As explained above, the present invention can determine the functional blocks to be placed in the SI depending on the size of the blocks, the number of wires between the blocks,
By replacing the wiring delay tolerance with a mechanical model as a parameter and arranging the blocks by balancing the forces between them, it is possible to quantify the degree of coupling between blocks, which was previously difficult to quantify. Since placement can be done by calculation, it becomes possible to automate what was previously placed manually.
また作業者の熟練度によって配置効率が決定されていた
ものが一定の品質で配置できる効果がある。In addition, it has the effect that items can be placed with a constant quality, whereas the placement efficiency was determined by the skill level of the worker.
第1図は本発明の実施例においてモデル化されたモデル
を示す図、第2図はモデル化された実機能ブロックの配
線関係を示す図、第3図はモデルが平衡状態になったも
のを示す図、第4図は実機能ブロックが配置されたもの
を示す図である。Fig. 1 is a diagram showing a model modeled in an embodiment of the present invention, Fig. 2 is a diagram showing the wiring relationship of modeled actual functional blocks, and Fig. 3 is a diagram showing the model in an equilibrium state. The figure shown in FIG. 4 is a diagram showing the arrangement of actual functional blocks.
Claims (1)
路の集合である機能ブロックの配置方法において、各機
能ブロックの大きさ、機能ブロック間の配線量、遅延許
容時間等のパラメータを力学的な力にモデル化し、その
力の強弱によって最適配置を決定することを特徴とする
LSIレイアウト法。(1) In the method of arranging functional blocks, which are a collection of circuits that perform specific operations, arranged inside an LSI, parameters such as the size of each functional block, the amount of wiring between functional blocks, and the allowable delay time are dynamically determined. An LSI layout method characterized by modeling a force and determining the optimal layout based on the strength of the force.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61300831A JPS63153851A (en) | 1986-12-17 | 1986-12-17 | Lsi lay out process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61300831A JPS63153851A (en) | 1986-12-17 | 1986-12-17 | Lsi lay out process |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63153851A true JPS63153851A (en) | 1988-06-27 |
Family
ID=17889632
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61300831A Pending JPS63153851A (en) | 1986-12-17 | 1986-12-17 | Lsi lay out process |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63153851A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5309371A (en) * | 1989-06-28 | 1994-05-03 | Kawasaki Steel Corporation | Method of and apparatus for designing circuit block layout in integrated circuit |
US5493510A (en) * | 1992-11-10 | 1996-02-20 | Kawasaki Steel Corporation | Method of and apparatus for placing blocks in semiconductor integrated circuit |
JP2002083004A (en) * | 2000-06-22 | 2002-03-22 | Fujitsu Ltd | Method, device, and program for cell arrangement of lsi |
JP2010165365A (en) * | 2000-06-22 | 2010-07-29 | Fujitsu Ltd | Program and method for changing cell arrangement location information of lsi |
-
1986
- 1986-12-17 JP JP61300831A patent/JPS63153851A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5309371A (en) * | 1989-06-28 | 1994-05-03 | Kawasaki Steel Corporation | Method of and apparatus for designing circuit block layout in integrated circuit |
US5493510A (en) * | 1992-11-10 | 1996-02-20 | Kawasaki Steel Corporation | Method of and apparatus for placing blocks in semiconductor integrated circuit |
JP2002083004A (en) * | 2000-06-22 | 2002-03-22 | Fujitsu Ltd | Method, device, and program for cell arrangement of lsi |
JP4486276B2 (en) * | 2000-06-22 | 2010-06-23 | 富士通株式会社 | LSI cell arrangement information generating device, changing device, and program |
JP2010165365A (en) * | 2000-06-22 | 2010-07-29 | Fujitsu Ltd | Program and method for changing cell arrangement location information of lsi |
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