JP2002082819A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To drastically shorten the set-up time of a software break and also avoid the limitation of the number of times of the software break execution. SOLUTION: An optional program area including an address in which a break instruction is set is copied from the user program of a flash memory 5a into a RAM 7, and a break instruction is set. In such a case, the address of the program area stored in the RAM 7 is stored in an emulation address register 11. When the user program of the memory 5a is executed, the program of the RAM 7 is executed and is halted at a set break point in the case the program stored in the RAM 7 is accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to software emulation technology, and more particularly to technology effective when applied to setting of a break instruction of a program by an on-chip debugger.

[0002]

2. Description of the Related Art According to studies made by the present inventor, an on-chip debugger is an example of a support device that supports the development of a system using a microcomputer or the like from both software and hardware.

This on-chip debugger has a configuration in which a card emulator such as an IC card is connected to a user system via an interface cable, and the card emulator is inserted into a card slot provided in a host computer such as a personal computer. The user system can be debugged in a state close to the product form.

[0004] The user system includes a debugging microcomputer in which a circuit necessary for debugging is incorporated and a flash memory is incorporated.
Software such as a user program downloaded to the flash memory of the debugging microcomputer is debugged.

[0005] Examples of this type of emulator are described in detail on November 30, 1984, published by Ohm Co., Ltd., The Institute of Electronics and Communication Engineers (ed.)
There are "LSI Handbook" P558 to P568, and this document describes a description of system development tools.

[0006]

However, the inventor of the present invention has found that the above-described debugging technique in the on-chip debugger has the following problems.

That is, when setting a software break in a user program stored in the flash memory, the user program is temporarily transferred to a card emulator, and a program in which the software break setting portion is replaced with a break instruction is created. Since it is necessary to erase and rewrite the user program in the flash memory, it takes a long time to set a software break, and there is a problem that debugging efficiency is reduced.

In addition, the number of times of erasing and writing of a flash memory is generally limited to about 100 times.
The number of executions of software breaks is also limited,
This is a restriction when debugging.

An object of the present invention is to provide a semiconductor integrated circuit device capable of greatly shortening a software break setting time and avoiding a limitation on the number of executions of a software break.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention includes a first semiconductor memory for storing a user program to be debugged, and a program in which a break instruction is set among the user programs stored in the first semiconductor memory. A second semiconductor memory for storing a program in an arbitrarily designated area, and a program executed in the first semiconductor memory, and when the user program accesses a program area in the second semiconductor memory, the second semiconductor memory is stored in the second semiconductor memory. Access control means for selecting and controlling to execute the program of the second semiconductor memory.

Further, the semiconductor integrated circuit device of the present invention includes a first semiconductor memory for storing a user program to be debugged, and a program in which a break instruction is set among the user programs stored in the first semiconductor memory. A second semiconductor memory for storing a program in an arbitrarily designated area, an address storage unit for storing an address of a program stored in the second semiconductor memory, and an address for accessing a program area of the second semiconductor memory. A select signal generating unit for generating a select signal when input from an address bus, a memory select signal for selecting a second semiconductor memory when the select signal of the select signal generating unit is input, and an address of an address storage unit And the address input from the address bus, and When the address of the less and the address bus matches is obtained and an access control means comprising an address conversion unit for converting the address replacement accessing the second semiconductor memory program.

Further, according to the semiconductor integrated circuit device of the present invention,
A nonvolatile first semiconductor memory for storing a user program to be debugged, and a program in an arbitrarily designated area including a program in which a break instruction is set among the user programs stored in the first semiconductor memory. A volatile second semiconductor memory, an address storage unit for storing an address of a program stored in the second semiconductor memory, and a select signal when an address for accessing a program area of the second semiconductor memory is input from an address bus. A select signal generating unit for generating, a memory select signal for selecting a second semiconductor memory when a select signal of the select signal generating unit is input, and an address of an address storage unit and an address input from an address bus. And the address of the address storage unit and the address of the address bus are When the match is obtained and an access control means comprising an address conversion unit for converting the address replacement accessing the second semiconductor memory program.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an on-chip debugger according to an embodiment of the present invention, FIG. 2 is a block diagram of a debugging microcomputer according to an embodiment of the present invention, and FIG. Block diagram of a bus state controller provided in the debugging microcomputer according to the embodiment. FIG. 4 is an explanatory diagram showing an example of a user program for setting a break instruction in the on-chip debugger according to the embodiment of the present invention. .

In the present embodiment, one of the emulators
The on-chip debugger 1 debugs a user program and the like and supports system development. As shown in FIG. 1, the on-chip debugger 1 includes a card emulator 2, an interface cable 3, a host computer 4, and a microcomputer 5 for debugging.

The card emulator 2 is, for example, a PC
MCIA (Personal Computer Me)
more Card International A
Sociation) card or PCI (Pe
ripheral Component Interc
connect) cards. Host computer 4
Is a personal computer equipped with a PC slot such as a PCMCIA slot or a PCI slot.

The debugging microcomputer (semiconductor integrated circuit device) 5 is provided with a flash memory (first semiconductor memory) 5a for storing circuits necessary for debugging and a user program. The computer 5 is mounted on a printed circuit board PCB of the user system.

The card emulator 2 is inserted into a PC card slot of the host computer 4, and the card emulator 2 and the printed circuit board PC are connected via an interface cable 3. Then, the user program downloaded to the flash memory 5a is debugged.

Further, as shown in FIG. 2, the debugging microcomputer 5 includes a flash memory 5a, a data transfer circuit 6, a RAM (second semiconductor memory) 7, a processor 8, and a bus state controller (access control means) 9. , And each is connected via a bus 10.

The bus 10 includes a flash memory 5a, RA
An address bus for transmitting various address signals such as M7, a control bus for transmitting various control signals between the processor 8 and other internal peripheral circuits in the debugging microcomputer 5, and various data to be processed, or It comprises a data bus to which instructions and the like are transmitted.

The data transfer circuit 6 is an interface circuit between the card emulator 2 and the microcomputer 5 for debugging, and the RAM 7 includes, for example, a RAM (Ra)
It comprises a volatile memory such as an ND (Access Memory), and temporarily stores data such as a user program.

The flash memory 5a stores a user program to be debugged, and the processor 8 manages all controls in the debugging microcomputer 5. The bus state controller 9 outputs a control signal based on the status information output from the processor 8 and controls a part instead of the processor 8.

The bus state controller 9 comprises an emulation address register (address storage unit) 11, an address decoder (select signal generation unit) 12, and an address conversion circuit (address conversion unit) 13, as shown in FIG. Have been.

Emulation address register 11
Stores the address of the program area to be replaced set by the user by the host computer 4. The address decoder 12 decodes the input address,
A select signal S is generated when an address of a program area to be replaced is input.

The address conversion circuit 13 has a ROM select signal RO for selecting the flash memory 5a based on the select signal S output from the address decoder 12.
S or a RAM select signal (memory select signal) RAS for selecting the RAM 7,
The address input via the address bus of 0
The signal is converted into an address signal assigned to 7 and output.

Next, the operation of the present embodiment will be described.

Here, in the user program stored in the flash memory 5a, the 0225C shown in FIG.
A case where an address of an address is set as a break point will be described.

First, in the user program stored in the flash memory 5a, an arbitrary program area including an area for setting a break instruction, for example, a program area from addresses 02000 to 02FFF shown in FIG. Is copied to the RAM 7 using.

At this time, the processor 8 stores the address of the program area stored in the RAM 7 in the emulation address register 11. The address stored in the emulation address register 11 is the address of the program stored in the flash memory 5a.

Then, the user operates the host computer 4
From among the programs stored in the RAM 7, the break instruction is set at the address of address 0225C in FIG. This means that it is only necessary to overwrite the program stored in the RAM 7 with the break instruction.

After that, the user program of the flash memory 5a is executed with the execution of the RAM emulation enabled. In this case, the address conversion circuit 13
Means that the flash memory 5a is accessed
The select signal ROS is output.

This user program is executed, and in the program of the flash memory 5a, the address 020 is read.
When addresses 00 to 02FFF are accessed,
The program stored in the RAM 7 will be used.

The operation of bus state controller 9 when a program at address 02000 is accessed, for example, will be described.

When an address of address 02000 is input via the address bus of the bus 10, the address decoder 12 generates a select signal S and generates an address conversion circuit 13
Output to

When the select signal S is input to the address conversion circuit 13, a RAM select signal RAS is output from the address conversion circuit 13 to select and activate the RAM 7.

At the same time, when the address conversion circuit 13 detects that the address stored in the emulation address register 11 matches the address input to the address conversion circuit 13 via the address bus, the input address Is converted and output so that the program stored in the RAM 7 is accessed.

When the program is shifted from the program in the flash memory 5a to the program in the RAM 7, and the program is executed, the program stops at the set break point (address 0225C).

Thus, in the present embodiment, it is not necessary to transfer a program to the card emulator 2 when setting a break instruction, so that the time for setting a break instruction can be greatly reduced.

Since an arbitrary program area for setting a break instruction is stored in the RAM 7 and a break point is set in the program of the RAM 7, erasing and writing operations of the program by the flash memory 5a can be omitted. The setting time of the break instruction can be further reduced, and the limitation on the number of executions of the software break due to the limitation on the number of erasures of the flash memory can be released.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in this embodiment, the flash microcomputer is provided in the debugging microcomputer. However, the memory for storing the user program may be other than the flash memory.
risky Erasable and Progr
amble Read Only Memory)
For example, a general nonvolatile memory such as a non-volatile memory may be used.

[0044]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, since a break instruction can be set in a part of the user program stored in the second semiconductor memory, it is not necessary to transfer the program to the card emulator of the on-chip debugger. Therefore, the time for setting a break instruction can be greatly reduced.

(2) Further, according to the present invention, since the erasing and writing operations of the program in the first semiconductor memory are not required, the setting time of the break instruction can be further reduced, and the software break due to the limitation of the number of erasures of the flash memory can be achieved. The restriction on the number of executions can be removed.

(3) Further, in the present invention, according to the above (1) and (2), the user program can be debugged efficiently and in a short time.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an on-chip debugger according to an embodiment of the present invention.

FIG. 2 is a block diagram of a debugging microcomputer according to one embodiment of the present invention.

FIG. 3 is a block diagram of a bus state controller provided in the debugging microcomputer according to the embodiment of the present invention;

FIG. 4 is an explanatory diagram showing an example of a user program for setting a break instruction in the on-chip debugger according to one embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 on-chip debugger 2 card emulator 3 interface cable 4 host computer 5 debugging microcomputer (semiconductor integrated circuit device) 5a flash memory (first semiconductor memory) 6 data transfer circuit 7 RAM (second semiconductor memory) 8 processor 9 bus state Controller (access control means) 10 bus 11 emulation address register (address storage unit) 12 address decoder (select signal generation unit) 13 address conversion circuit (address conversion unit) PCB printed wiring board S select signal RAS RAM select signal (memory select signal) ROS ROM select signal

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) H01L 21/82 H01L 21/82 T 27/04 27/04 T 21/822 (72) Inventor Ryo Hatada Hokkaido 145 Nakajima, Nanae-cho, Kameda-gun F-term (reference) in Hitachi Hokkai Semiconductor Co., Ltd.

Claims (3)

[Claims] 1. A semiconductor integrated circuit device incorporating a circuit required for debugging used in an on-chip debugger, comprising: a first semiconductor memory for storing a user program to be debugged; and a first semiconductor memory for storing a user program to be debugged. A second semiconductor memory that stores a program in an arbitrarily designated area including a program in which a break instruction is set, among the user programs that have been set, a program in the first semiconductor memory is executed, and the user program is stored in the second semiconductor memory. A semiconductor integrated circuit device, comprising: access control means for selecting the second semiconductor memory when accessing the program area, and controlling the program to execute the program of the second semiconductor memory. 2. A semiconductor integrated circuit device incorporating a circuit necessary for debugging used in an on-chip debugger, comprising: a first semiconductor memory storing a user program to be debugged; and a first semiconductor memory storing a user program to be debugged. A second semiconductor memory for storing a program in an arbitrarily designated area including a program in which a break instruction is set among the user programs, and an address storage unit for storing an address of a program stored in the second semiconductor memory. A select signal generating unit for generating a select signal when an address for accessing a program area of the second semiconductor memory is input from an address bus, and a second semiconductor memory when the select signal of the select signal generating unit is input. A memory select signal to be selected is output, and an address of the address storage unit is output. The address is compared with an address input from the address bus, and when the address in the address storage unit matches the address in the address bus, the replaced address for accessing the program in the second semiconductor memory is converted. A semiconductor integrated circuit device comprising: 3. A semiconductor integrated circuit device incorporating a circuit required for debugging used in an on-chip debugger, comprising: a first nonvolatile semiconductor memory for storing a user program to be debugged; and the first semiconductor memory. A volatile second semiconductor memory for storing a program in an arbitrarily designated area including a program in which a break instruction is set, among the user programs stored in the second semiconductor memory; and an address of the program stored in the second semiconductor memory. An address storage unit for storing, a select signal generating unit for generating a select signal when an address for accessing a program area of the second semiconductor memory is input from an address bus, and a select signal of the select signal generating unit is input. Outputting a memory select signal for selecting the second semiconductor memory; and The address of the address storage unit is compared with the address input from the address bus. When the address of the address storage unit matches the address of the address bus, a replacement for accessing a program of the second semiconductor memory is performed. And an address conversion unit for converting and outputting the converted address.