JP2002076054A - Packaging structure of semiconductor device - Google Patents

Packaging structure of semiconductor device

Info

Publication number
JP2002076054A
JP2002076054A JP2000255731A JP2000255731A JP2002076054A JP 2002076054 A JP2002076054 A JP 2002076054A JP 2000255731 A JP2000255731 A JP 2000255731A JP 2000255731 A JP2000255731 A JP 2000255731A JP 2002076054 A JP2002076054 A JP 2002076054A
Authority
JP
Japan
Prior art keywords
semiconductor device
reinforcing member
circuit board
wiring lead
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000255731A
Other languages
Japanese (ja)
Inventor
Shinichi Fujiwara
伸一 藤原
Yuji Fujita
祐治 藤田
Tomoko Yoda
智子 依田
Takehiko Hasebe
健彦 長谷部
Toyoki Asada
豊樹 浅田
Toshihiro Hachiya
登志広 八矢
Yoshikatsu Ishida
喜勝 石田
Morio Muramatsu
盛生 村松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000255731A priority Critical patent/JP2002076054A/en
Publication of JP2002076054A publication Critical patent/JP2002076054A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PROBLEM TO BE SOLVED: To provide a packaging structure of a semiconductor device which can ensure a high reliability, when the semiconductor device is connected to a circuit board with an adhesive. SOLUTION: In the packaging structure of the semiconductor device, a bumps 13 provided on the semiconductor device 1 is electrically connected with a wiring lead 21 formed on the surface of the circuit board 2, and adhesive 3 is filled between the semiconductor device 1 and the circuit board 2. A reinforcing member 24 is provided on the rear side of a wiring lead 21 in the area including at least a position where a bump 13 is connected with the wiring lead 21.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体集積回路素子
を回路基板に接続する方式に関する。
The present invention relates to a system for connecting a semiconductor integrated circuit device to a circuit board.

【0002】[0002]

【従来の技術】半導体素子の高集積化に伴い、これを回
路基板に搭載して、小形・薄形化、高信頼化する要求が
高まっている。これに答える接続方式としては、異方導
電性接着剤を用いたFCA(Flip Chip Attach)接続があ
り、特開昭60−180132号に開示されている。これによ
り、小形・薄形化、高信頼化を損なう事なく簡便で効率
的な半導体搭載方法が確立された。しかし上記従来技術
では、図7に示すように半導体装置1を回路基板2に搭
載する際に、ICチップ11の上面からの加圧荷重(矢印
で示す)が必要となる。この荷重がバンプ13を介して
配線リード21へ加わり配線が変形すると、バンプ13
と配線リード21の間に隙間が発生し、接触面積が減少
する。このため接続抵抗が上昇し導通不良に至るという
現象が発生する。そこで、上記の問題点を解決する方法
として、特開平9−92683号に開示されている半導体装置
が提案されている。これは、回路基板の底面に補強板を
貼付け、回路基板全体の変形を抑えることで配線リード
の変形を防止する。これにより、異方導電性接着剤を用
いて回路基板へ接続する場合に、高い信頼性を確保でき
る。
2. Description of the Related Art As semiconductor devices become more highly integrated, there is an increasing demand for mounting them on a circuit board to make them smaller, thinner and more reliable. As a connection method responding to this, there is an FCA (Flip Chip Attach) connection using an anisotropic conductive adhesive, which is disclosed in JP-A-60-180132. As a result, a simple and efficient semiconductor mounting method has been established without impairing miniaturization, thinning, and high reliability. However, in the above-described conventional technique, when the semiconductor device 1 is mounted on the circuit board 2 as shown in FIG. 7, a pressing load (indicated by an arrow) from the upper surface of the IC chip 11 is required. When this load is applied to the wiring lead 21 via the bump 13 and the wiring is deformed, the bump 13
A gap is generated between the wiring lead 21 and the wiring lead 21, and the contact area is reduced. For this reason, a phenomenon occurs in which the connection resistance increases, leading to poor conduction. Therefore, as a method for solving the above problem, a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 9-92683 has been proposed. This prevents the wiring leads from being deformed by attaching a reinforcing plate to the bottom surface of the circuit board and suppressing deformation of the entire circuit board. Thereby, when connecting to a circuit board using an anisotropic conductive adhesive, high reliability can be secured.

【0003】[0003]

【発明が解決しようとする課題】上記従来技術により、
配線リードの変形を防止することで、安定した接続信頼
性を実現できる。しかし、回路基板の底面に補強板を貼
付けるので、基板の厚さや重量がともに増加する。携帯
電話など小形・軽量な装置に上記技術を適用した場合、
装置全体の厚さや重量を増やす要因となりうる。また、
接着剤を用いて補強板を回路基板に貼付けるので、補強
板の面積が大きくなるほど補強板と回路基板の間に発生
する熱ひずみが増大する。吸湿により接着剤の接着力が
低下した場合、補強板と回路基板の接着が保持できなく
なる。また、樹脂層の弾性率が低い場合や基板内層に配
線層があると、図7に示すように配線リード21の変形
は基板の内部で吸収されてしまい、基板の底面に補強板
を貼付けても配線リード21の変形を十分防止すること
ができない場合が発生する。
According to the above prior art,
By preventing the deformation of the wiring lead, stable connection reliability can be realized. However, since the reinforcing plate is attached to the bottom surface of the circuit board, the thickness and weight of the board both increase. When the above technology is applied to small and lightweight devices such as mobile phones,
This can be a factor in increasing the thickness and weight of the entire device. Also,
Since the reinforcing plate is attached to the circuit board using an adhesive, the larger the area of the reinforcing plate, the greater the thermal strain generated between the reinforcing plate and the circuit board. When the adhesive strength of the adhesive decreases due to moisture absorption, the adhesion between the reinforcing plate and the circuit board cannot be maintained. If the elasticity of the resin layer is low or if there is a wiring layer in the inner layer of the substrate, the deformation of the wiring leads 21 is absorbed inside the substrate as shown in FIG. In some cases, the deformation of the wiring lead 21 cannot be sufficiently prevented.

【0004】本発明の目的は、半導体装置を接着剤を用
いて回路基板へ接続する場合に、高い信頼性を確保でき
る半導体装置の実装構造を提供することにある。
An object of the present invention is to provide a semiconductor device mounting structure that can ensure high reliability when the semiconductor device is connected to a circuit board using an adhesive.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するた
め、請求項1記載の発明では、半導体装置に設けられた
電極と回路基板の表面に形成された配線リードとが電気
的に接続され、半導体装置と回路基板との間に接着剤を
充填した半導体装置の実装構造において、配線リードの
裏側で、電極と配線リードが接触する部位を少なくとも
含む範囲に補強部材を配置したことを特徴とするもので
ある。
According to the first aspect of the present invention, an electrode provided on a semiconductor device is electrically connected to a wiring lead formed on a surface of a circuit board. In a mounting structure of a semiconductor device in which an adhesive is filled between a semiconductor device and a circuit board, a reinforcing member is disposed on a rear side of the wiring lead, at least in a range including a portion where the electrode and the wiring lead are in contact with each other. Things.

【0006】また請求項2記載の発明では、前記請求項
1記載の半導体装置の実装構造において、補強部材の弾
性率を、補強部材を取り囲む樹脂層の弾性率よりも大き
くすることを特徴とするものである。
According to a second aspect of the present invention, in the mounting structure of the semiconductor device according to the first aspect, the elastic modulus of the reinforcing member is larger than the elastic modulus of the resin layer surrounding the reinforcing member. Things.

【0007】また請求項3記載の発明では、前記請求項
1乃至2記載の半導体装置の実装構造において、補強部
材の熱膨張率を、補強部材を取り囲む樹脂層の熱膨張率
よりも小さくすることを特徴とするものである。
According to a third aspect of the present invention, in the semiconductor device mounting structure according to the first or second aspect, the thermal expansion coefficient of the reinforcing member is made smaller than the thermal expansion coefficient of the resin layer surrounding the reinforcing member. It is characterized by the following.

【0008】上記した手段は下記のように作用する。請
求項1記載の発明によれば、半導体装置の電極と回路基
板の配線リードが接触する範囲に補強部材が設けられて
いるので、バンプを介して配線リードに荷重が加わって
も従来に比べて配線リードに生じる変形は少ない。これ
によりバンプと配線リードの接触面積が保たれるので、
半導体装置と配線間の電気的接続を確実かつ高信頼に行
うことができる。
The above-described means works as follows. According to the first aspect of the present invention, the reinforcing member is provided in an area where the electrode of the semiconductor device and the wiring lead of the circuit board are in contact with each other. There is little deformation in the wiring leads. This keeps the contact area between the bump and the wiring lead,
Electrical connection between the semiconductor device and the wiring can be performed reliably and with high reliability.

【0009】また請求項2記載の発明によれば、補強部
材の弾性率を、補強部材を取り囲む樹脂層の弾性率より
も大きくしているので、上記請求項1の作用に加えて配
線リードの変形がさらに小さくなり、高信頼な電気的接
続を確実に行うことができる。
According to the second aspect of the present invention, the elastic modulus of the reinforcing member is made larger than the elastic modulus of the resin layer surrounding the reinforcing member. Deformation is further reduced, and highly reliable electrical connection can be reliably performed.

【0010】また請求項3記載の発明によれば、補強部
材の熱膨張率は、補強部材を取り囲む樹脂層の熱膨張率
よりも小さい。半導体装置と回路基板との間に接着剤を
充填して接続する際に、接着剤の硬化が完了した後に温
度を下げると、補強部材は樹脂層に比べて熱収縮量が少
ないので、補強部材と接している配線リードと半導体装
置の電極との間には圧縮応力が発生する。よって上記請
求項1乃至2の作用に加えて、配線リードと半導体装置
の電極と接触面積をさら増やすことが可能になり、半導
体装置と回路基板との間の電気的接続をさらに確実かつ
高信頼に行うことができる。
According to the third aspect of the invention, the coefficient of thermal expansion of the reinforcing member is smaller than the coefficient of thermal expansion of the resin layer surrounding the reinforcing member. When the adhesive is filled and connected between the semiconductor device and the circuit board, if the temperature is lowered after the curing of the adhesive is completed, the amount of heat shrinkage of the reinforcing member is smaller than that of the resin layer. A compressive stress is generated between the wiring lead in contact with the electrode and the electrode of the semiconductor device. Therefore, in addition to the effects of the first and second aspects, the contact area between the wiring lead and the electrode of the semiconductor device can be further increased, and the electrical connection between the semiconductor device and the circuit board can be made more reliable and highly reliable. Can be done.

【0011】また請求項4記載の発明では、半導体装置
に設けられた電極と回路基板の表面に形成された配線リ
ードとが電気的に接続され、半導体装置と回路基板との
間に接着剤を充填した半導体装置の実装構造において、
配線リードの表側で、電極と配線リードが接触する部位
を少なくとも含む範囲に導電性の補強部材を配置したこ
とを特徴とするものである。
Further, according to the present invention, the electrodes provided on the semiconductor device are electrically connected to the wiring leads formed on the surface of the circuit board, and an adhesive is provided between the semiconductor device and the circuit board. In the mounting structure of the filled semiconductor device,
On the front side of the wiring lead, a conductive reinforcing member is disposed in a range including at least a portion where the electrode and the wiring lead are in contact with each other.

【0012】また請求項5記載の発明では、前記請求項
4記載の半導体装置の実装構造において、補強部材の弾
性率を配線リードの弾性率に等しいか、または大きくす
ることを特徴とするものである。
According to a fifth aspect of the present invention, in the semiconductor device mounting structure according to the fourth aspect, the elastic modulus of the reinforcing member is equal to or larger than the elastic modulus of the wiring lead. is there.

【0013】上記した手段は下記のように作用する。請
求項4記載の発明によれば、配線リードの表面に導電性
の補強部材が設けられているので、半導体装置の電極は
導電性の補強部材と接触する。この補強部材の表面は配
線リードに比べて変形しにくいため、これによりバンプ
と補強部材の接触面積が保たれるので、半導体装置と配
線間の電気的接続を確実かつ高信頼に行うことができ
る。
The above-described means works as follows. According to the fourth aspect of the present invention, since the conductive reinforcing member is provided on the surface of the wiring lead, the electrode of the semiconductor device comes into contact with the conductive reinforcing member. Since the surface of the reinforcing member is less likely to be deformed than the wiring lead, the contact area between the bump and the reinforcing member is maintained, so that the electrical connection between the semiconductor device and the wiring can be performed reliably and with high reliability. .

【0014】また請求項5記載の発明によれば、補強部
材の弾性率を配線リードの弾性率に等しいか、または大
きくしているので、上記請求項1の作用に加えて補強部
材の表面の変形はさらに小さくなり、高信頼な電気的接
続を確実に行うことができる。
According to the fifth aspect of the present invention, the elastic modulus of the reinforcing member is equal to or greater than the elastic modulus of the wiring lead. Deformation is further reduced, and highly reliable electrical connection can be reliably performed.

【0015】[0015]

【発明の実施の形態】以下、本発明に係る半導体装置の
実装構造の好ましい実施の形態を図1乃至図6を用いて
説明する。図1は本発明の第一実施例である半導体装置
の実装構造の要図である。本実施の形態の半導体装置1
には、ICチップ11の下面に所定の電子回路(図示せ
ず)が形成されている。回路基板2と電気的導通を得る
部位には電極パッド12が形成されている。この電極パ
ッド12上には金のワイヤバンピングにより形成したバ
ンプ13が配置されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the mounting structure of a semiconductor device according to the present invention will be described below with reference to FIGS. FIG. 1 is an essential view of a mounting structure of a semiconductor device according to a first embodiment of the present invention. Semiconductor device 1 of the present embodiment
On the lower surface of the IC chip 11, a predetermined electronic circuit (not shown) is formed. An electrode pad 12 is formed at a position where electrical conduction with the circuit board 2 is obtained. A bump 13 formed by gold wire bumping is arranged on the electrode pad 12.

【0016】バンプ13の材料は金に限定されるもので
なく、はんだ、ニッケル、銅、アルミニウム、銀、導電
性樹脂など、電気的導通の得られるものを用いればよ
い。またバンプの形成方法も限定されることはなく、印
刷、ボール転写、メッキ、スタッドバンプ法などを用い
ても良い。
The material of the bumps 13 is not limited to gold, but may be any material that can provide electrical conduction, such as solder, nickel, copper, aluminum, silver, or a conductive resin. The method for forming the bump is not limited, and printing, ball transfer, plating, a stud bump method, or the like may be used.

【0017】また、回路基板2は、銅箔を加工すること
により生成した配線リード21、樹脂層22、及び内層
配線23、さらに本実施例の要部となる補強部材24か
ら構成されている。
The circuit board 2 includes wiring leads 21 formed by processing a copper foil, a resin layer 22, an inner wiring 23, and a reinforcing member 24 which is a main part of the present embodiment.

【0018】配線リード21は、ICチップ11が回路基
板2に搭載された状態でバンプ13の直下に配置するよ
うに形成されている。なお銅箔からなる配線リード21
の表面には、金バンプとの接触抵抗を低減するためにニ
ッケルおよび金からなるメッキが施される。また、バン
プとの金属接合を行なうために、配線リード21の表面
にはんだ膜を形成してもよい。
The wiring leads 21 are formed so as to be disposed immediately below the bumps 13 with the IC chip 11 mounted on the circuit board 2. The wiring lead 21 made of copper foil
Is plated with nickel and gold to reduce the contact resistance with the gold bumps. Further, a solder film may be formed on the surface of the wiring lead 21 in order to perform metal bonding with the bump.

【0019】補強部材24は配線リード21の裏側に形
成されており、バンプ13と配線リード21が接触する
部位を少なくとも含む範囲に配置している。補強部材2
4の材料としては補強部材24を取り囲む樹脂層22よ
りも弾性率が高いこと、または熱膨張率が小さい材料で
あればよい。例えば、銀あるいは銅の導電性粒子を含有
する導電性樹脂の埋め込みや銅のメッキ法などを用い、
回路基板2の層間接続スルーホールを設けるときに補強
部材24を同時に形成すればよい。
The reinforcing member 24 is formed on the back side of the wiring lead 21 and is disposed in a range including at least a portion where the bump 13 contacts the wiring lead 21. Reinforcing member 2
The material of No. 4 may be any material having a higher elastic modulus or a lower coefficient of thermal expansion than the resin layer 22 surrounding the reinforcing member 24. For example, using a method of embedding a conductive resin containing conductive particles of silver or copper or a plating method of copper,
The reinforcing member 24 may be formed at the same time when the interlayer connection through hole of the circuit board 2 is provided.

【0020】接着剤3は、例えばエポキシ系の熱硬化性
樹脂やシリコーン系の熱可塑性樹脂からなり、樹脂の収
縮力により半導体装置1と回路基板2との間の密着力を
保つことができる。同時にバンプ13と配線リード21
との接合部の保護の役割を果たす。なお、接着剤3を構
成する部材としては上記樹脂に限らず、熱可塑性フィル
ム、熱硬化型フィルム、導電性粒子を含んだ異方導電性
ペーストや異方導電性フィルムなど、接着を行える部材
であればよい。
The adhesive 3 is made of, for example, an epoxy-based thermosetting resin or a silicone-based thermoplastic resin. The adhesive force between the semiconductor device 1 and the circuit board 2 can be maintained by the contraction force of the resin. At the same time, the bump 13 and the wiring lead 21
And play a role in protecting the joint. The member constituting the adhesive 3 is not limited to the above resin, but may be a member capable of bonding, such as a thermoplastic film, a thermosetting film, an anisotropic conductive paste or an anisotropic conductive film containing conductive particles. I just need.

【0021】続いて、本実施例における半導体装置の実
装構造において、半導体装置1を接着剤3を用いて回路
基板2に接続する工程について図2乃至図3を用いて説
明する。半導体装置1を回路基板2に接続するために、
まず回路基板2上に接着剤3を塗布する。この接着剤3
を塗布する方法としては、注射器状のディスペンサで塗
布してもよいし、スクリーン印刷法を利用しても良い。
また、フィルム状の接着剤3を回路基板2の表面に張り
付けてもよい。
Next, a process of connecting the semiconductor device 1 to the circuit board 2 using the adhesive 3 in the mounting structure of the semiconductor device according to the present embodiment will be described with reference to FIGS. In order to connect the semiconductor device 1 to the circuit board 2,
First, the adhesive 3 is applied on the circuit board 2. This adhesive 3
May be applied using a syringe-shaped dispenser, or a screen printing method may be used.
Further, a film-like adhesive 3 may be attached to the surface of the circuit board 2.

【0022】上記方法により接着剤3を塗布した後、図
2に示すように回路基板2のチップ搭載位置にICチップ
11を配置する。次いで図3に示すようにICチップ11
の上方から荷重を加えると、バンプ13と配線リード2
1の間の接着剤3が周囲に排除され、バンプ13と配線
リード21が密着することで電気的導通を得る。ここで
本実施例における半導体装置の実装構造では、バンプ1
3と接触する部位の配線リード21の直下に補強部材2
4があるため、バンプを介して配線リードに荷重が加わ
っても配線リードに生じる変形は少ない。従来は配線リ
ードが変形するためバンプと配線リード間の接触面積が
減少して接続部の導通不良が発生していたが、本発明に
より接触面積が保たれるので、半導体装置と回路基板の
電気的導通を確実に行うことができる。
After the adhesive 3 is applied by the above-described method, the IC chip 11 is arranged at the chip mounting position on the circuit board 2 as shown in FIG. Next, as shown in FIG.
When a load is applied from above the bump 13 and the wiring lead 2
The adhesive 3 is removed to the periphery, and the bumps 13 and the wiring leads 21 are brought into close contact with each other to obtain electrical continuity. Here, in the mounting structure of the semiconductor device in this embodiment, the bump 1
The reinforcing member 2 is provided immediately below the wiring lead 21 at a position where the reinforcing member
4, there is little deformation of the wiring lead even if a load is applied to the wiring lead via the bump. Conventionally, the contact area between the bump and the wiring lead was reduced due to the deformation of the wiring lead, resulting in poor conduction of the connection portion. However, the present invention maintains the contact area, and the electrical connection between the semiconductor device and the circuit board is maintained. Electrical conduction can be reliably performed.

【0023】以上の実装構造において、補強部材24の
弾性率が、補強部材を取り囲む樹脂層22の弾性率より
も大きい場合、上記作用に加えて配線リード21の変形
がさらに小さくなり、より高信頼な電気的接続を確実に
行うことができる。また、補強部材24の熱膨張率が、
補強部材を取り囲む樹脂層22の熱膨張率よりも小さい
場合、接着剤3の硬化が完了した後に温度を下げると、
補強部材24は樹脂層22に比べて熱収縮量が少ないの
で、補強部材24と接している配線リード21とバンプ
13との間には圧縮応力が発生する。よって上記作用に
加えて、配線リード21とバンプ13との接触面積がさ
ら増加し、より高信頼な電気的接続を確実に行うことが
できる。
In the above mounting structure, when the elastic modulus of the reinforcing member 24 is larger than the elastic modulus of the resin layer 22 surrounding the reinforcing member, the deformation of the wiring lead 21 is further reduced in addition to the above-described operation, and higher reliability is achieved. Electrical connection can be reliably performed. Further, the coefficient of thermal expansion of the reinforcing member 24 is
When the temperature is lower than the coefficient of thermal expansion of the resin layer 22 surrounding the reinforcing member, the temperature is lowered after the curing of the adhesive 3 is completed.
Since the reinforcing member 24 has a smaller heat shrinkage than the resin layer 22, a compressive stress is generated between the wiring lead 21 and the bump 13 in contact with the reinforcing member 24. Therefore, in addition to the above operation, the contact area between the wiring lead 21 and the bump 13 further increases, and more reliable electrical connection can be reliably performed.

【0024】続いて本発明の第二実施例について図4を
用いて説明する。ここで、図1に示した第一実施例と同
様な構成については、同一符号を記すことにより説明を
省略する。本実施例では、配線リード21を信号伝送に
用いる場合、内層配線23と電気的に独立させたい場合
の実装構造を示す。補強部材24の直下に位置する内層
配線23を形成する際に、あらかじめ配線にエッチング
やレーザー加工など方法により開口部を設けておく。次
いで内層配線23と接触しない大きさに補強部材24を
形成する。これにより、補強部材24と内層配線23は
電気的に独立とすることができ、補強部材24と接する
配線リード21を信号伝送のために用い、内層配線23
を電源およびグランド層として用いる事ができる。
Next, a second embodiment of the present invention will be described with reference to FIG. Here, the same components as those in the first embodiment shown in FIG. In this embodiment, a mounting structure is shown in a case where the wiring leads 21 are used for signal transmission and are desired to be electrically independent from the inner layer wiring 23. When forming the inner layer wiring 23 located immediately below the reinforcing member 24, an opening is previously provided in the wiring by a method such as etching or laser processing. Next, the reinforcing member 24 is formed so as not to be in contact with the inner wiring 23. Thereby, the reinforcing member 24 and the inner layer wiring 23 can be electrically independent, and the wiring lead 21 in contact with the reinforcing member 24 is used for signal transmission, and the inner layer wiring 23 is used.
Can be used as a power supply and a ground layer.

【0025】続いて本発明の第三実施例について説明す
る。図5は本発明の第三実施例である半導体装置と回路
基板の要部の断面を示すものである。
Next, a third embodiment of the present invention will be described. FIG. 5 shows a cross section of a main part of a semiconductor device and a circuit board according to a third embodiment of the present invention.

【0026】本実施例による半導体装置の実装構造は、
第一実施例のバンプ13と配線リード21をはんだ接合
したことを特徴とする。本実施例では、あらかじめ配線
リード21上においてバンプ13が接する領域にはんだ
25を形成しておく。次いで、回路基板2上に接着剤3
を塗布した後、回路基板2のチップ搭載位置にICチップ
11を配置し、ICチップ11の上方から荷重を加える。
接着剤3が周囲に排除されることでバンプ13とはんだ
25が密着した後に、はんだを溶融させてICチップ11
を回路基板2と接続する。ここで、補強部材24の熱膨
張率が、補強部材を取り囲む樹脂層22の熱膨張率より
も小さい場合、接着剤3の硬化が完了した後に温度を下
げると、補強部材24は樹脂層22に比べて熱収縮量が
少ないので、補強部材24と接している配線リード21
とバンプ13との間には圧縮応力が発生する。そのため
に、はんだ25には下方から押し上げようとする力が働
く。この圧縮応力が大きくなるほど、はんだ部に生じる
水平方向の剪断応力が緩和され、接続信頼性が向上す
る。なお本実施例において、ICチップ11を回路基板2
に搭載する際に、先にはんだ25を溶融してバンプ13
と接続し、その後接着剤3をICチップ11と回路基板2
の隙間に充填しても同様の効果を達成できる。このとき
は上記作用に加え、はんだ接続であるためにセルフアラ
イメントが可能となり、また荷重をかける必要がないた
めに配線も変形しないという利点が得られる。
The mounting structure of the semiconductor device according to this embodiment is as follows.
The first embodiment is characterized in that the bumps 13 and the wiring leads 21 are joined by soldering. In this embodiment, the solder 25 is previously formed on the wiring lead 21 in a region where the bump 13 contacts. Next, the adhesive 3 is placed on the circuit board 2.
Is applied, the IC chip 11 is arranged at the chip mounting position of the circuit board 2, and a load is applied from above the IC chip 11.
After the bumps 13 and the solder 25 come into close contact with each other due to the removal of the adhesive 3 around, the solder is melted to form the IC chip 11.
Is connected to the circuit board 2. Here, when the coefficient of thermal expansion of the reinforcing member 24 is smaller than the coefficient of thermal expansion of the resin layer 22 surrounding the reinforcing member, when the temperature is lowered after the curing of the adhesive 3 is completed, the reinforcing member 24 The amount of heat shrinkage is smaller than that of the wiring lead 21 in contact with the reinforcing member 24.
A compressive stress is generated between the bump and the bump 13. Therefore, a force is applied to the solder 25 to push it up from below. As the compressive stress increases, the horizontal shear stress generated in the solder portion is alleviated, and the connection reliability is improved. In this embodiment, the IC chip 11 is connected to the circuit board 2.
When mounting on the bumps 13, the solder 25 is first melted and
Then, the adhesive 3 is applied to the IC chip 11 and the circuit board 2.
The same effect can be achieved by filling the gap. In this case, in addition to the above-described effects, there is obtained an advantage that self-alignment is possible because of the solder connection, and that there is no need to apply a load, so that the wiring is not deformed.

【0027】また上記効果は、バンプ13の材料として
金の場合に限定されるものでなく、はんだ、ニッケル、
銅、アルミニウム、銀、導電性樹脂など、電気的導通の
得られるものを用いた場合にも達成される。
The above effect is not limited to the case where the material of the bump 13 is gold, but may be solder, nickel,
This is also achieved when using a material that can provide electrical conduction, such as copper, aluminum, silver, or a conductive resin.

【0028】続いて本発明の第四実施例について図6で
説明する。本実施例では、回路基板2の配線リード21
の表面に導電性の補強部材24を形成した構造である。
ICチップ11を回路基板2へ搭載するには、まず回路基
板2の表面に接着剤3を塗布し、回路基板2のチップ搭
載位置にICチップ11を配置する。次いでICチップ11
の上方から荷重を加えることにより、バンプ13と補強
部材24の間の接着剤3が周囲に排除され、バンプ13
と補強部材24が密着することで電気的導通を得る。こ
こで、バンプ13に加わる荷重は補強部材24が支える
ので、従来の配線変形に比べて補強部材24の変形は少
なくなり、補強部材24とバンプ13との接触面積が増
加し、より高信頼な電気的接続を行うことができる。こ
こで、バンプ13の材料は第一実施例と同様に金に限定
されるものでなく、はんだ、ニッケル、銅、アルミニウ
ム、銀、導電性樹脂など、電気的導通の得られるものを
用いればよい。
Next, a fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, the wiring leads 21 of the circuit board 2 are used.
Is a structure in which a conductive reinforcing member 24 is formed on the surface.
To mount the IC chip 11 on the circuit board 2, first, the adhesive 3 is applied to the surface of the circuit board 2, and the IC chip 11 is arranged at a chip mounting position on the circuit board 2. Then IC chip 11
By applying a load from above, the adhesive 3 between the bump 13 and the reinforcing member 24 is removed to the periphery, and the bump 13
The electrical connection is obtained by the close contact of the reinforcing member 24 with the reinforcing member 24. Here, since the load applied to the bump 13 is supported by the reinforcing member 24, the deformation of the reinforcing member 24 is reduced as compared with the conventional wiring deformation, the contact area between the reinforcing member 24 and the bump 13 is increased, and a more reliable An electrical connection can be made. Here, the material of the bump 13 is not limited to gold as in the first embodiment, but may be any material that can provide electrical conduction, such as solder, nickel, copper, aluminum, silver, or a conductive resin. .

【0029】以上の実装構造において、補強部材24の
弾性率が、配線リードの弾性率に等しいか、または大き
い場合、上記作用に加えて配線リード21の変形がさら
に小さくなり、より高信頼な電気的接続を確実に行うこ
とができる。
In the above mounting structure, when the elastic modulus of the reinforcing member 24 is equal to or greater than the elastic modulus of the wiring lead, the deformation of the wiring lead 21 is further reduced in addition to the above-described operation, and a more reliable electric Connection can be reliably performed.

【0030】なお、本発明の第一の実施形態乃至第四の
実施形態では、半導体装置1としてICチップ11にバン
プ13を形成した例を示したが、本発明はこれに限定さ
れるものではない。半導体装置1として、突起電極が形
成されたBGA(ボールグリッドアレイ)や、CSP(チップ
サイズパッケージ)などにも適用可能である。
In the first to fourth embodiments of the present invention, an example is shown in which bumps 13 are formed on an IC chip 11 as the semiconductor device 1. However, the present invention is not limited to this. Absent. The semiconductor device 1 is also applicable to a BGA (ball grid array) on which bump electrodes are formed, a CSP (chip size package), and the like.

【0031】[0031]

【発明の効果】以上に述べたように本発明によれば、回
路基板の底面に補強板を貼付けることなく、配線リード
の変形を防止することができる。これにより、携帯電話
などの小形・軽量機器の基板の厚さや重量を増加させる
ことなく、半導体装置と配線間の電気的接続を確実かつ
高信頼に行うことができる。また、回路基板の底面に接
着剤を用いる必要がないので、吸湿時の信頼性を確保で
きる。また、樹脂層の弾性率が低い場合や基板内層に配
線層がある場合でも、配線リードの変形を十分防止でき
る。さらに、曲げや衝撃などの外力や熱衝撃による熱歪
みが加わっても、バンプと配線リードの接触面積は従来
より安定しているので、本実装構造を用いることで耐衝
撃性、耐熱衝撃性に優れた情報処理装置を実現すること
ができる。
As described above, according to the present invention, the deformation of the wiring leads can be prevented without attaching a reinforcing plate to the bottom surface of the circuit board. Thus, the electrical connection between the semiconductor device and the wiring can be reliably and reliably performed without increasing the thickness and weight of the substrate of a small and lightweight device such as a mobile phone. Further, since it is not necessary to use an adhesive on the bottom surface of the circuit board, reliability during moisture absorption can be ensured. Further, even when the elastic modulus of the resin layer is low or the wiring layer is provided in the inner layer of the substrate, the deformation of the wiring lead can be sufficiently prevented. Furthermore, the contact area between the bump and the wiring lead is more stable than before even if thermal strain is applied due to external force such as bending or impact, or thermal shock. An excellent information processing device can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第一実施例である半導体装置の実装構
造の要図である。
FIG. 1 is a main view of a mounting structure of a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の第一実施例である半導体装置の実装構
造の組立て工程を示す図であり、半導体装置を加圧する
前の状態を示す図である。
FIG. 2 is a view showing an assembling process of the semiconductor device mounting structure according to the first embodiment of the present invention, showing a state before the semiconductor device is pressurized.

【図3】本発明の第一実施例である半導体装置の実装構
造の組立て工程を示す図であり、半導体装置を加圧した
後の状態を示す図である。
FIG. 3 is a view showing an assembling process of the semiconductor device mounting structure according to the first embodiment of the present invention, showing a state after the semiconductor device is pressurized.

【図4】本発明の第二実施例である半導体装置の実装構
造の要図である。
FIG. 4 is an essential view of a mounting structure of a semiconductor device according to a second embodiment of the present invention.

【図5】本発明の第三実施例である半導体装置の実装構
造の要図である。
FIG. 5 is an essential diagram of a semiconductor device mounting structure according to a third embodiment of the present invention;

【図6】本発明の第四実施例である半導体装置の実装構
造の要図である。
FIG. 6 is an essential view of a mounting structure of a semiconductor device according to a fourth embodiment of the present invention.

【図7】従来の半導体装置の一例を示すICチップと基板
の要図である。
FIG. 7 is an essential diagram of an IC chip and a substrate showing an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1…半導体装置、11…ICチップ、12…電極パッド、
13…バンプ、2…回路基板、21…配線リード、22
…樹脂層、23…内層配線、24…補強部材、25…は
んだ、3…接着剤。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... IC chip, 12 ... Electrode pad,
13: Bump, 2: Circuit board, 21: Wiring lead, 22
... resin layer, 23 ... inner wiring, 24 ... reinforcing member, 25 ... solder, 3 ... adhesive.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 依田 智子 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 長谷部 健彦 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 浅田 豊樹 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 八矢 登志広 茨城県ひたちなか市稲田1410番地 株式会 社日立製作所デジタルメディア製品事業部 内 (72)発明者 石田 喜勝 茨城県ひたちなか市稲田1410番地 株式会 社日立製作所デジタルメディア製品事業部 内 (72)発明者 村松 盛生 茨城県ひたちなか市稲田1410番地 株式会 社日立製作所デジタルメディア製品事業部 内 Fターム(参考) 5F044 KK11 KK19 LL11 5F061 AA01 BA03 CA05  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tomoko Yoda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Takehiko Hasebe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi, Ltd., Production Technology Research Laboratories (72) Inventor Toyoki Asada 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. Production Technology Research Laboratories (72) Inventor Toshihiro Yaya 1410 Inada, Hitachinaka City, Ibaraki Prefecture Address Digital Media Product Division, Hitachi, Ltd. (72) Yoshikatsu Ishida, Inventor 1410 Inada, Hitachinaka City, Ibaraki Prefecture Digital Media Product Division, Hitachi, Ltd. (72) Inventor Morio Muramatsu, Inada, Hitachinaka City, Ibaraki Prefecture 1410 Digital Media Hitachi, Ltd. Product Division F term (reference) 5F044 KK11 KK19 LL11 5F061 AA01 BA03 CA05

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置に設けられた電極と回路基板
の表面に形成された配線リードとが電気的に接続され、
半導体装置と回路基板との間に接着剤を充填した半導体
装置の実装構造において、配線リードの裏側で、電極と
配線リードが接触する部位を少なくとも含む範囲に補強
部材を配置したことを特徴とする半導体装置の実装構
造。
An electrode provided on a semiconductor device is electrically connected to a wiring lead formed on a surface of a circuit board,
In a mounting structure of a semiconductor device in which an adhesive is filled between a semiconductor device and a circuit board, a reinforcing member is disposed on a rear side of the wiring lead, at least in a range including a portion where the electrode and the wiring lead are in contact with each other. Semiconductor device mounting structure.
【請求項2】 請求項1において、補強部材の弾性率
を、補強部材を取り囲む樹脂層の弾性率よりも大きくす
ることを特徴とする半導体装置の実装構造。
2. The semiconductor device mounting structure according to claim 1, wherein an elastic modulus of the reinforcing member is larger than an elastic modulus of a resin layer surrounding the reinforcing member.
【請求項3】 請求項1乃至2において、補強部材の熱
膨張率を、補強部材を取り囲む樹脂層の熱膨張率よりも
小さくすることを特徴とする半導体装置の実装構造。
3. The mounting structure of a semiconductor device according to claim 1, wherein a coefficient of thermal expansion of the reinforcing member is smaller than a coefficient of thermal expansion of a resin layer surrounding the reinforcing member.
【請求項4】 半導体装置に設けられた電極と回路基板
の表面に形成された配線リードとが電気的に接続され、
半導体装置と回路基板との間に接着剤を充填した半導体
装置の実装構造において、配線リードの表側で、電極と
配線リードが接触する部位を少なくとも含む範囲に導電
性の補強部材を配置したことを特徴とする半導体装置の
実装構造。
4. An electrode provided on the semiconductor device is electrically connected to a wiring lead formed on a surface of the circuit board.
In the mounting structure of the semiconductor device in which the adhesive is filled between the semiconductor device and the circuit board, a conductive reinforcing member is arranged on a front side of the wiring lead, at least in a range including a portion where the electrode and the wiring lead are in contact with each other. Characteristic semiconductor device mounting structure.
【請求項5】 請求項4において、補強部材の弾性率を
配線リードの弾性率に等しいか、または大きくすること
を特徴とする半導体装置の実装構造。
5. The mounting structure of a semiconductor device according to claim 4, wherein the elastic modulus of the reinforcing member is equal to or larger than the elastic modulus of the wiring lead.
JP2000255731A 2000-08-22 2000-08-22 Packaging structure of semiconductor device Pending JP2002076054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000255731A JP2002076054A (en) 2000-08-22 2000-08-22 Packaging structure of semiconductor device

Publications (1)

Publication Number Publication Date
JP2002076054A true JP2002076054A (en) 2002-03-15

Family

ID=18744463

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2002076054A (en)

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