JP2002075779A - Ceramic electronic component - Google Patents
Ceramic electronic componentInfo
- Publication number
- JP2002075779A JP2002075779A JP2000252078A JP2000252078A JP2002075779A JP 2002075779 A JP2002075779 A JP 2002075779A JP 2000252078 A JP2000252078 A JP 2000252078A JP 2000252078 A JP2000252078 A JP 2000252078A JP 2002075779 A JP2002075779 A JP 2002075779A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electronic component
- ceramic electronic
- plating film
- outermost layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、セラミック電子部
品に係り、詳しくは、少なくとも最外層がメッキ膜から
なる外部電極が形成きれたセラミック電子部品に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic electronic component, and more particularly, to a ceramic electronic component having at least an outermost layer formed of a plating film and having external electrodes formed thereon.
【０００２】[0002]
【従来の技術】近年、積層セラミックコンデンサや積層
ＬＣ複合部品等の表面実装型積層セラミック電子部品の
小型化が急激に進められている。通常、表面実装型積層
セラミック電子部品の両端部には外部電極（外部端子）
が形成されている。この外部電極の電極層の構成は、下
地電極として焼付けにより形成する導電層、この上に、
電気メッキによりＮｉ、Ｓｎメッキの順番で導電層を形
成する。2. Description of the Related Art In recent years, surface mount type multilayer ceramic electronic components such as multilayer ceramic capacitors and multilayer LC composite components have been rapidly reduced in size. Normally, external electrodes (external terminals) are provided at both ends of the surface mount type multilayer ceramic electronic component.
Are formed. The configuration of the electrode layer of this external electrode is as follows: a conductive layer formed by baking as a base electrode;
A conductive layer is formed by electroplating in the order of Ni and Sn plating.
【０００３】それらの積層セラミック電子部品を回路基
板等に実装する場合、画像認識装置を用いてその位置や
方向性を検知しながら実装装着することが一般的に知ら
れている。[0003] When mounting these multilayer ceramic electronic components on a circuit board or the like, it is generally known to mount and mount the electronic components while detecting the position and directionality of the components using an image recognition device.
【０００４】ところで、積層セラミック電子部品の両端
部の外部電極形成方法は、バレルに多数の電子部品と通
電用媒体（メディア）を入れ、メッキ液中でバレルを回
転させながら夫々のメッキを構成するものである。この
時のＳｎメッキ膜表面のグレイン形状（凹凸）が、電流
密度、メッキ液の添加剤の種類等により決定されるが、
メッキと研磨が同時進行のため外部端子の表面の平滑性
が非常に高い。図４（Ｂ）に従来の積層セラミック電子
部品の外部電極最外層のグレイン拡大写真を示す。According to a method of forming external electrodes at both ends of a multilayer ceramic electronic component, a large number of electronic components and a current-carrying medium are placed in a barrel, and each plating is performed while rotating the barrel in a plating solution. Things. At this time, the grain shape (irregularity) of the Sn plating film surface is determined by the current density, the type of the plating solution additive, and the like.
Since the plating and polishing proceed simultaneously, the surface smoothness of the external terminals is very high. FIG. 4B shows an enlarged grain photograph of the outermost layer of the external electrode of the conventional multilayer ceramic electronic component.
【０００５】[0005]
【発明が解決しようとする課題】上記したように、メッ
キ膜形成後の積層セラミック電子部品に光を照射してそ
の反射光をＣＣＤカメラで二値化して外観認識する方法
では、外部電極の光沢の状態がロットによって大きく変
動し、電子部品を構成するセラミックと外部電極のメッ
キ膜との光沢の差が極端に小さくなって、セラミックと
外部電極の区別ができなくなり、積層セラミック電子部
品を正確に認識することができなくなるという問題点が
ある。As described above, in the method of irradiating the multilayer ceramic electronic component after forming the plating film with light and binarizing the reflected light with a CCD camera and recognizing the appearance, the gloss of the external electrode is determined. Condition greatly fluctuates from lot to lot, and the difference in gloss between the ceramic constituting the electronic component and the plating film of the external electrode becomes extremely small, making it impossible to distinguish between the ceramic and the external electrode. There is a problem that it cannot be recognized.
【０００６】更に、回路パターンに積層セラミック電子
部品を実装する時、マウント機のばらつきや回路基板の
パターンばらつきにより、正規の位置に積層セラミック
電子部品がマウントされない場合があり、ずれた状態で
載置される。Further, when mounting a multilayer ceramic electronic component on a circuit pattern, the multilayer ceramic electronic component may not be mounted in a proper position due to a variation in a mounting machine or a variation in a circuit board pattern. Is done.
【０００７】図３（Ａ）は実装相手側基板上のランドパ
ターン１０の寸法及び配置の例、同図（Ｂ）は積層セラ
ミック電子部品１１のリフロー後のランドパターン１０
に対する正規位置、同図（Ｃ）は正規位置と０．１５mm
ずれたマウント状態である。FIG. 3A shows an example of the dimensions and arrangement of the land pattern 10 on the mounting partner substrate, and FIG. 3B shows the land pattern 10 of the multilayer ceramic electronic component 11 after reflow.
(C) shows the normal position and 0.15 mm
The mounting state is shifted.
【０００８】積層セラミック電子部品のマウント後、リ
フロー炉ではんだ付けされ、回路パターンと外部端子が
固着されるが、最近の電子部品の小型化に伴い固着する
ためのはんだ量も少なくなっているため、一旦図３
（Ｃ）のようにずれてマウントされた状態が修復されな
いまま固着され回路基板上で他の電子部品と接触し、シ
ョート発生の問題等がある。After mounting the multilayer ceramic electronic component, it is soldered in a reflow furnace to fix the circuit pattern and the external terminals. However, with the recent miniaturization of electronic components, the amount of solder for fixing has been reduced. , Once Figure 3
As shown in (C), the mounted state is fixed without being repaired and comes into contact with other electronic components on the circuit board, thereby causing a problem of short circuit.
【０００９】本発明は、上記問題点を解決するものであ
り、画像認識を確実に行うことが可能で、効率よく実装
を行うことができ、更に、回路パターンにずれて装着し
たものでも、リフロー炉ではんだ付けした場合、正規の
ランドに修復固着出来る外部電極表面を有するセラミッ
ク電子部品を提供することを目的とする。The present invention solves the above-mentioned problems, and can reliably perform image recognition, can be efficiently mounted, and can reflow even if it is mounted in a shifted circuit pattern. An object of the present invention is to provide a ceramic electronic component having an external electrode surface that can be fixed to a proper land when soldered in a furnace.
【００１０】本発明のその他の目的や新規な特徴は後述
の実施の形態において明らかにする。[0010] Other objects and novel features of the present invention will be clarified in embodiments described later.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、少なくとも最外層がメッキ膜からなる外
部電極が形成されたセラミック電子部品において、前記
外部電極の最外層表面のグレインが、表面粗さ（Ｒａ）
で、１．０〜４．０μｍの範囲内であることを特徴とし
ている。In order to achieve the above object, the present invention provides a ceramic electronic component having at least the outermost layer formed of a plating film and having an outer electrode formed thereon, wherein the outermost layer of the outer electrode has a grain formed on the outermost layer. , Surface roughness (Ra)
In the range of 1.0 to 4.0 μm.
【００１２】前記セラミック電子部品において、前記外
部電極が多層構造を有し、かつ、前記最外層がＳｎメッ
キ膜、又はＳｎ合金メッキ膜であるとよい。In the ceramic electronic component, it is preferable that the external electrode has a multilayer structure, and the outermost layer is a Sn plating film or a Sn alloy plating film.
【００１３】[0013]
【発明の実施の形態】以下、本発明に係るセラミック電
子部品の実施の形態を図面に従って説明する。Embodiments of a ceramic electronic component according to the present invention will be described below with reference to the drawings.
【００１４】図１及び図２は本発明に係るセラミック電
子部品の実施の形態であり、積層セラミックコンデンサ
を例にとって説明する。図１はその積層セラミックコン
デンサの正断面図、図２は積層セラミックコンデンサに
おける外部電極構成の拡大断面図である。FIGS. 1 and 2 show an embodiment of a ceramic electronic component according to the present invention, which will be described by taking a multilayer ceramic capacitor as an example. FIG. 1 is a front sectional view of the multilayer ceramic capacitor, and FIG. 2 is an enlarged sectional view of an external electrode configuration in the multilayer ceramic capacitor.
【００１５】これらの図に示すように、積層セラミック
コンデンサは、セラミック素子１中に、セラミック層２
を介して静電容量形成用の内部電極３を配置し、かつ、
セラミック素子１の両端側に、内部電極３と導通する外
部電極４を配設することにより形成されている。そし
て、外部電極４は、Ｃｕ層（焼付けＣｕ電極）４ａ、Ｎ
ｉメッキ膜層４ｂ、最外層であるＳｎメッキ膜層４ｃか
らなる三層構造を有している。As shown in these figures, a multilayer ceramic capacitor comprises a ceramic element 1 and a ceramic layer 2.
And an internal electrode 3 for forming a capacitance is disposed via
It is formed by disposing external electrodes 4 that are electrically connected to the internal electrodes 3 on both ends of the ceramic element 1. The external electrode 4 includes a Cu layer (baked Cu electrode) 4a, N
It has a three-layer structure including an i-plated film layer 4b and an outermost Sn-plated film layer 4c.
【００１６】次に、上記外部電極４の形成方法について
説明する。この実施の形態では、外部電極４を形成する
にあたって、まず、Ｃｕ粉末を導電成分とする導電ペー
スト（Ｃｕペースト）をセラミック素子１の両端部に塗
布して焼き付けることによりＣｕ層４ａを形成する。そ
れから、Ｎｉ浴（ワット浴）において、０．５Ａ／ｃｍ
２、３０分の条件でＮｉ電気メッキを行い、Ｃｕ層４ａ
上にＮｉメッキ膜層４ｂを形成する。次に、Ｓｎ浴（中
性Ｓｎ浴）において、０．１Ａ／ｃｍ２、１２０分の条
件で、Ｓｎ電気メッキを行い、Ｎｉメッキ膜層４ｂ上に
Ｓｎメッキ膜層４ｃを形成する。図２のようにそのＳｎ
メッキ膜層４ｃは表面にグレイン５を有し、そのグレイ
ンは、表面粗さ（Ｒａ）で、１．０〜４．０μｍの範囲
内にあるように設定されている。表面粗さ（Ｒａ）は日
本工業規格（Ｂ０６０１）で規定された中心線平均粗さ
である。Next, a method for forming the external electrode 4 will be described. In this embodiment, when forming the external electrode 4, first, a conductive layer (Cu paste) containing Cu powder as a conductive component is applied to both ends of the ceramic element 1 and baked to form a Cu layer 4 a. Then, in a Ni bath (Watts bath), 0.5 A / cm
2 , Ni electroplating is performed under the conditions of 30 minutes, and the Cu layer 4a is formed.
The Ni plating film layer 4b is formed thereon. Next, in an Sn bath (neutral Sn bath), Sn electroplating is performed under the conditions of 0.1 A / cm 2 and 120 minutes to form a Sn plating film layer 4c on the Ni plating film layer 4b. As shown in FIG.
The plating film layer 4c has grains 5 on the surface, and the grains are set to have a surface roughness (Ra) in the range of 1.0 to 4.0 μm. The surface roughness (Ra) is a center line average roughness defined by Japanese Industrial Standard (B0601).
【００１７】なお、この実施の形態では、Ｎｉメッキ、
Ｓｎメッキを行うにあたって、通常のバレルメッキ方法
（かご状のバレルを用いた電気メッキ）によりメッキ膜
を形成した。In this embodiment, Ni plating,
In performing Sn plating, a plating film was formed by a usual barrel plating method (electroplating using a cage barrel).
【００１８】上記のメッキ方法によれば、Ｓｎメッキ時
の電流密度により最外層のＳｎメッキ膜層４ｃ表面に所
要の粗さのグレインを形成でき、その粗さを中心線平均
粗さＲａで１．０から４．０μｍの範囲でコントロール
することが可能であり、Ｓｎメッキ膜を効率よく形成す
ることも可能になる。そして、その結果、回路基板に実
装する際に、セルフアライメント性（位置が修復される
性質）の良い電子部品を製造することが可能になる。図
４（Ａ）に本実施の形態の場合における外部電極最外層
のグレイン拡大写真を示す。図４（Ｂ）の従来の場合に
比してグレインが大きく、つまり粗い表面となっている
ことが判る。According to the above-described plating method, a grain having a required roughness can be formed on the surface of the outermost Sn plating film layer 4c by the current density at the time of Sn plating, and the roughness is defined as a center line average roughness Ra of 1%. It is possible to control the thickness within a range of from 0.0 to 4.0 μm, and it is also possible to efficiently form a Sn plating film. As a result, when mounted on a circuit board, it is possible to manufacture an electronic component having a good self-alignment property (the property of correcting the position). FIG. 4A shows an enlarged grain photograph of the outermost layer of the external electrode in the case of the present embodiment. It can be seen that the grain is larger than that of the conventional case shown in FIG.
【００１９】なお、上記の方法で製造した、外部電極４
の最外層のグレインが表面粗さでＲａ＝１．０から４．
０μｍの間である本発明の実施形態にかかる積層セラミ
ックコンデンサと、バレルメッキ方法の電流密度を変更
してメッキを行って外部電極の最外層を形成した、従来
例、比較例の積層セラミックコンデンサを回路基板に図
３（Ｃ）のようにそれぞれ０．１５mmずらして実装し、
リフロー炉に通炉後の位置ずれの発生割合及び蒸気エー
ジング試験の結果を以下の表１に示す。ここで、蒸気エ
ージング試験は日本工業規格（Ｃ００５０）に定められ
たはんだ付け試験方法の一種であり、試料を水蒸気にさ
らす試験であり、表１では４時間水蒸気にさらした場合
を示す。The external electrode 4 manufactured by the above method is used.
The outermost layer has a surface roughness of Ra = 1.0 to 4.
The multilayer ceramic capacitor according to the embodiment of the present invention, which is between 0 μm and the multilayer ceramic capacitor of the conventional example and the comparative example, in which the outermost layer of the external electrode is formed by plating while changing the current density of the barrel plating method. As shown in FIG. 3 (C), each of them is shifted by 0.15 mm on a circuit board and mounted.
Table 1 below shows the ratio of occurrence of displacement after passing through the reflow furnace and the results of the steam aging test. Here, the steam aging test is a kind of soldering test method specified in Japanese Industrial Standards (C0050), and is a test in which a sample is exposed to steam. Table 1 shows a case where the sample is exposed to steam for 4 hours.
【００２０】[0020]
【表１】 表１に示すように、試料ＮＯ．１，２（従来例、比較
例）の場合、つまり表面粗さ（Ｒａ）が１μｍ未満の場
合、ずれの修復が完全にできず図３（Ｃ）のように装着
時のずれがそのまま残って固着されるものがでてくる。
ＮＯ．１ではサンプル個数ｎ＝１０００のうちの１．１
％、ＮＯ．２ではサンプル個数ｎ＝１０００のうちの
０．５％がリフロー後においてもずれが残っている。[Table 1] As shown in Table 1, the sample No. In the case of 1, 2 (conventional example, comparative example), that is, when the surface roughness (Ra) is less than 1 μm, the displacement cannot be completely repaired, and the displacement at the time of mounting remains as shown in FIG. Something sticks out.
NO. In the case of 1, 1.1 out of the number of samples n = 1000
%, NO. In the case of 2, 0.5% of the sample number n = 1000 still has a deviation even after reflow.
【００２１】また、表面粗さが（Ｒａ）が４μｍを超え
る試料ＮＯ．７（比較例）のものは、ずれの修復をする
ことはできるが蒸気エージング試験において、はんだ濡
れ性不良が発生し、良好な固着が出来ない問題が発生す
る。つまり、ＮＯ．７ではサンプル個数ｎ＝１０００の
うちの０．７％が蒸気エージング試験において不良とな
っている。Sample No. having a surface roughness (Ra) of more than 4 μm. In the case of No. 7 (Comparative Example), the displacement can be repaired, but in the steam aging test, poor solder wettability occurs and a problem that good fixation cannot be performed occurs. That is, NO. In No. 7, 0.7% of the sample number n = 1000 was defective in the steam aging test.
【００２２】これに対して、表面粗さ（Ｒａ）で、１．
０〜４．０μｍの範囲内にある試料ＮＯ．３，４，５，
６（実施の形態）のものは、リフロー後においてずれ修
復が完全になされ、蒸気エージング試験においても、は
んだ濡れ性不良の発生が無く、高精度の固着が出来た。On the other hand, in terms of surface roughness (Ra), 1.
Sample No. 0 in the range of 0 to 4.0 μm. 3,4,5
In the case of No. 6 (embodiment), the displacement was completely repaired after reflow, and even in the steam aging test, there was no occurrence of poor solder wettability, and high-precision fixation was possible.
【００２３】この実施の形態によれば、次の通りの効果
を得ることができる。According to this embodiment, the following effects can be obtained.
【００２４】(1) メッキ膜からなる外部電極４の最外
層表面のグレイン５が表面粗さでＲａ：１．０から４．
０μｍの間となるようにしているので、実装時のセルフ
アライメント性とはんだ濡れ性を満足可能である。(1) The grain 5 on the outermost layer surface of the external electrode 4 made of a plating film has a surface roughness of Ra: 1.0 to 4.0.
Since the thickness is set to be between 0 μm, the self-alignment property at the time of mounting and the solder wettability can be satisfied.
【００２５】(2) 外部電極４は、はんだ付け性等を考
慮して、Ｓｎメッキ膜やＳｎ合金メッキ膜を外部電極の
最外層とするものが多いが、その場合に、本実施の形態
を適用することにより、はんだ濡れ性を確保しつつ実装
時のセルフアライメント性を良好にできる。(2) In many cases, the outer electrode 4 is made of a Sn plating film or a Sn alloy plating film as the outermost layer of the external electrode in consideration of solderability and the like. By applying, self-alignment at the time of mounting can be improved while securing solder wettability.
【００２６】(3) 外部電極４の最外層表面のグレイン
が適切な表面粗さであり、セラミック素子１と外部電極
４のメッキ膜との光沢に差を持たせることができ、セラ
ミック素子１と外部電極４を区別して画像認識を確実に
行うことが可能で、効率よく実装を行うことができる。(3) The surface of the outermost layer of the external electrode 4 has an appropriate surface roughness, and the gloss between the ceramic element 1 and the plating film of the external electrode 4 can be made different. Image recognition can be reliably performed by distinguishing the external electrodes 4, and mounting can be performed efficiently.
【００２７】なお、上記実施の形態では、外部電極４の
最外層のグレインをバレルメッキ方法における電流密度
でコントロールしたが、メッキ液の添加剤を変更して所
要のグレインを形成することも可能であり、外部電極の
最外層の形成方法には必ずしも制約はなく、種々の方法
を用いることが可能である。In the above embodiment, the outermost layer of the external electrode 4 is controlled by the current density in the barrel plating method. However, it is also possible to change the additive of the plating solution to form the required grain. There is no particular limitation on the method of forming the outermost layer of the external electrode, and various methods can be used.
【００２８】また、上記実施の形態では、外部電極の最
外層がＳｎメッキ膜である場合について説明したが、最
外層がＳｎメッキ膜である場合に限らず、はんだメッキ
膜等の場合や、さらにその他のものである場合にも本発
明を適用することが可能である。In the above embodiment, the case where the outermost layer of the external electrode is a Sn plating film has been described. However, the present invention is not limited to the case where the outermost layer is a Sn plating film. The present invention can be applied to other cases.
【００２９】さらに、外部電極の下層がＣｕ層やＮｉメ
ッキ膜層に限られるものでないことはいうまでもない。
但し、最下層はセラミック素子への付着性の良い金属層
（Ａｇ等）、また中間層ははんだ喰われ防止機能のある
金属層であることが望ましい。Further, it goes without saying that the lower layer of the external electrode is not limited to the Cu layer or the Ni plating film layer.
However, the lowermost layer is desirably a metal layer (Ag or the like) having good adhesion to the ceramic element, and the intermediate layer is desirably a metal layer having a function of preventing solder erosion.
【００３０】また、上記実施の形態では、積層セラミッ
クコンデンサを例にとって説明したが、本発明は、積層
セラミックコンデンサに限らず、少なくとも最外層がメ
ッキ膜からなる外部電極が形成された種々のセラミック
電子部品に適用することが可能であり、その場合にも上
記実施の形態の場合と同様の効果を得ることができる。In the above embodiment, the multilayer ceramic capacitor has been described as an example. However, the present invention is not limited to the multilayer ceramic capacitor, but may be any of various ceramic electronic devices in which at least the outermost layer is formed of a plated film with external electrodes. The present invention can be applied to parts, and in that case, the same effect as in the above embodiment can be obtained.
【００３１】なお、本発明はさらにその他の点において
も上記実施の形態に限定されるものではなく、外部電極
の具体的な形状や構造等に関し、発明の要旨の範囲内に
おいて、種々の応用、変形を加えることが可能である。It should be noted that the present invention is not limited to the above-described embodiment in other respects as well, and various applications, specific shapes and structures of the external electrodes can be applied within the scope of the invention. Deformations can be made.
【００３２】[0032]
【発明の効果】以上説明したように、本発明に係るセラ
ミック電子部品によれば、少なくとも最外層が電気メッ
キ膜からなる外部電極が形成されたセラミック電子部品
において、前記外部電極の最外層表面のグレインが、表
面粗さ（Ｒａ）で、１．０〜４．０μｍの範囲内である
ようにしたので、実装時のセルフアライメント性（リフ
ロー時に位置が修正される性質）とはんだ濡れ性を満足
させ得る。As described above, according to the ceramic electronic component according to the present invention, in a ceramic electronic component in which at least the outermost layer is formed of an electroplated film, the outermost layer surface of the outer electrode is formed. Since the grain has a surface roughness (Ra) within the range of 1.0 to 4.0 μm, it satisfies the self-alignment property at the time of mounting (the property that the position is corrected at the time of reflow) and the solder wettability. I can make it.
【００３３】また、前記外部電極が多層構造を有し、か
つ、前記最外層がＳｎメッキ膜、又はＳｎ合金メッキ膜
からなる場合、Ｓｎ、Ｓｎ合金以外の最外層に比べては
んだ濡れ性をいっそう改善して、実装時のセルフアライ
メント性も良好なものとすることが可能である。When the external electrode has a multilayer structure and the outermost layer is made of a Sn plating film or a Sn alloy plating film, the solder wettability is further improved as compared with the outermost layers other than Sn and Sn alloy. It is possible to improve and improve the self-alignment property at the time of mounting.
【図１】本発明に係るセラミック電子部品の第１の実施
の形態であって、積層セラミックコンデンサを例にとっ
て示す正断面図である。FIG. 1 is a front sectional view of a first embodiment of a ceramic electronic component according to the present invention, showing a multilayer ceramic capacitor as an example.
【図２】同じく要部拡大断面図である。FIG. 2 is an enlarged sectional view of a main part of the same.
【図３】実装相手側基板上のランドパターンの寸法及び
配置及びセラミック電子部品の実装の様子を説明する平
面図である。FIG. 3 is a plan view illustrating dimensions and arrangement of land patterns on a mounting partner substrate and a state of mounting a ceramic electronic component.
【図４】本発明の実施の形態の場合及び従来の場合のグ
レインの拡大図である。FIG. 4 is an enlarged view of a grain in the case of the embodiment of the present invention and a conventional case.
１ セラミック素子 ２ セラミック層 ３ 内部電極 ４ 外部電極 ４ａ Ｃｕ層 ４ｂ Ｎｉメッキ層 ４ｃ Ｓｎメッキ層 ５ グレイン DESCRIPTION OF SYMBOLS 1 Ceramic element 2 Ceramic layer 3 Internal electrode 4 External electrode 4a Cu layer 4b Ni plating layer 4c Sn plating layer 5 Grain
Claims (2)
部電極が形成されたセラミック電子部品において、 前記外部電極の最外層表面のグレインが、表面粗さ（Ｒ
ａ）で、１．０〜４．０μｍの範囲内であることを特徴
とするセラミック電子部品。1. A ceramic electronic component having at least an outer electrode formed of a plating film and having an outer electrode formed thereon, wherein the outer electrode has a surface roughness (R)
The ceramic electronic component according to a), which is in the range of 1.0 to 4.0 μm.
前記最外層がＳｎメッキ膜、又はＳｎ合金メッキ膜から
なる請求項１記載のセラミック電子部品。2. The external electrode has a multilayer structure, and
2. The ceramic electronic component according to claim 1, wherein the outermost layer is made of a Sn plating film or a Sn alloy plating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000252078A JP2002075779A (en) | 2000-08-23 | 2000-08-23 | Ceramic electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000252078A JP2002075779A (en) | 2000-08-23 | 2000-08-23 | Ceramic electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002075779A true JP2002075779A (en) | 2002-03-15 |
Family
ID=18741387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000252078A Pending JP2002075779A (en) | 2000-08-23 | 2000-08-23 | Ceramic electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002075779A (en) |
Cited By (8)
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|---|---|---|---|---|
| EP1353343A3 (en) * | 2002-04-09 | 2006-09-27 | TDK Corporation | Electronic device with external terminals and method of production of the same |
| US7379288B2 (en) | 2004-02-27 | 2008-05-27 | Murata Manufacturing Co., Ltd. | Monolithic ceramic electronic component and method for manufacturing the same |
| DE102006060432A1 (en) * | 2006-12-20 | 2008-06-26 | Epcos Ag | Electrical component and external contact of an electrical component |
| CN103000372A (en) * | 2011-09-07 | 2013-03-27 | Tdk株式会社 | Electronic component |
| CN103928232A (en) * | 2014-03-26 | 2014-07-16 | 海门市曼博莱电子发展有限公司 | Laminating ceramic capacitor |
| CN110024065A (en) * | 2016-12-01 | 2019-07-16 | 株式会社村田制作所 | Chip-type electronic component |
| CN112289585A (en) * | 2019-07-22 | 2021-01-29 | Tdk株式会社 | Ceramic electronic component |
| CN115762995A (en) * | 2022-11-04 | 2023-03-07 | 广东泛瑞新材料有限公司 | Ceramic magnetic core and preparation method and application thereof |
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|---|---|---|---|---|
| EP1353343A3 (en) * | 2002-04-09 | 2006-09-27 | TDK Corporation | Electronic device with external terminals and method of production of the same |
| EP2085983A1 (en) * | 2002-04-09 | 2009-08-05 | TDK Corporation | Electronic device with external terminals and method of production of the same |
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| CN103928232A (en) * | 2014-03-26 | 2014-07-16 | 海门市曼博莱电子发展有限公司 | Laminating ceramic capacitor |
| CN110024065A (en) * | 2016-12-01 | 2019-07-16 | 株式会社村田制作所 | Chip-type electronic component |
| CN112289585A (en) * | 2019-07-22 | 2021-01-29 | Tdk株式会社 | Ceramic electronic component |
| JP2021019123A (en) * | 2019-07-22 | 2021-02-15 | Tdk株式会社 | Ceramic electronic component |
| CN112289585B (en) * | 2019-07-22 | 2022-02-15 | Tdk株式会社 | Ceramic electronic component |
| JP7379899B2 (en) | 2019-07-22 | 2023-11-15 | Tdk株式会社 | ceramic electronic components |
| CN115762995A (en) * | 2022-11-04 | 2023-03-07 | 广东泛瑞新材料有限公司 | Ceramic magnetic core and preparation method and application thereof |
| CN115762995B (en) * | 2022-11-04 | 2023-08-08 | 广东泛瑞新材料有限公司 | Ceramic magnetic core and preparation method and application thereof |
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