JP2002073413A - Memory access device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory access device that solves speed buffering problems of a high cost to use a two port memory and the infeasibility of a high-speed access caused by using a one port memory that requires a selective circuit to discriminate between the access from a host and the access from peripheral circuits and also needs to inserts the dynamic weight for the access intervention to the one port memory. SOLUTION: The memory access device has an answer holding part 7 that holds a present value and a lookahead resister 10 that holds a lookahead value at a host side. When the access of the host side occurs, is updates an address counter 5 and reads in advance the next data responding to the host and holds the present value in the answer holding part 7. The device reads an address into a buffer memory 8 to give priority an update timing of the address counter 5 for a priority of the lookahead and holds the read out value in the lookahead holding part 10. When the lookahead process and the next access occur concurrently and if holding timings of the lookahead holding part 10 and the answer holding part 7 become the same, the device holds a memory output in the answer holding part 7 by means of a selector 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device suitable for use when a one-port memory is used as a buffer for absorbing a data transfer speed difference between a microcomputer and a peripheral circuit.

[0002]

2. Description of the Related Art An apparatus using a flash memory card or the like requires an interface circuit for transferring data between the card and a microcomputer. In general, a memory card having a small bus width and a low transfer speed often has a high-speed microcomputer that also executes an application. The interface circuit is usually provided with a buffer to absorb the difference in transfer speed, so that the transfer of data to / from a low-speed memory card does not cause a drop in the performance of the entire device. It is desirable to be able to respond to the access of the side fastest.

First, a conventional buffer configuration will be described. FIG. 4 is a block diagram showing a memory access device using a two-port memory as a buffer memory. In FIG. 4, a system bus (system bus) 1 is an external bus of a host microcomputer (not shown) including addresses, data, read / write signals, and the like.
C) 2 is a circuit for decoding the address value of the system bus 1, a timing circuit (Timing) 3 is a circuit for generating a control pulse for accessing the memory according to the address designation, and an input / output circuit (I / O) 4 Is a circuit for inputting / outputting data to / from the data bus of the system bus 1, an address counter 5 is an address counter for generating an address of a buffer memory, and a buffer memory 6 is a 2-port buffer which is a buffer for speed difference absorption. Memory.

FIG. 5 shows the timing when the host microcomputer accesses the buffer in the above configuration.
The memory in this example is a synchronous memory in which data is output one clock after the address, and is mapped from the host microcomputer as a FIFO (First In First Out) configuration.

First, in synchronization with a read pulse RE falling by a buffer read of the host microcomputer, the timing circuit 3 permits the output of the input / output circuit 4 and outputs the data read from the memory to the data bus of the system bus 1. The host microcomputer reads the read pulse RE at the same time
To end the read cycle. In response to the rise of the read pulse RE, the timing circuit 3 outputs an increment pulse to the address counter 5 to update the memory address. Thus, one access is completed. At the time of the next microcomputer access, the address has been updated, so that the preparation for reading the memory has been completed.

In the buffer configuration using a two-port memory as described above, access from two paths can be basically performed at the same time and asynchronously, so that the access on the host microcomputer side becomes the access on the peripheral circuit side. Independent without any distractions. Therefore, in the timing example of FIG. 6, data can be read and written even in an access cycle of a minimum of two clocks.

[0007]

However, there is a problem that the two-port memory causes a high cost. Since the buffer is originally a buffer for absorbing the speed difference, it is effective to access between either of the low-frequency and high-frequency (high-priority) accesses. If a memory is used, the cost can be reduced.

However, since the host microcomputer and the peripheral circuit are accessed completely asynchronously, even if the access priority on the host microcomputer side is increased, in the case of the one-port memory, for example, the host microcomputer is accessed during the access on the peripheral circuit side. It is necessary to insert a wait state corresponding to the access arbitration time into the host microcomputer when there is an access request from the host microcomputer.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention does not require any wait insertion for accesses on the higher priority side while using a low-cost one-port memory. It is another object of the present invention to provide a memory access device which does not require any unnecessary increase in access cycles.

[0010]

SUMMARY OF THE INVENTION In order to solve this problem, a memory access device according to the present invention temporarily stores data output from a memory (one-port memory) for reading data on the side where access is prioritized. Reading data holding means for holding, address updating means for updating a memory address to an address to be read in the next access at the time of reading on the priority side, and access for reading an updated address from the memory immediately after the address is updated with priority An arbitration unit and a prefetch data holding unit that temporarily holds prefetch data, which is data of an update address that has been preferentially read, perform a prefetch operation, and the data holding timing of the read data holding unit is set to the priority side. The prefetch data at the time of the immediately preceding read has already been held in the prefetch data holding means. In the case of the read timing, the output data of the pre-read data holding means is selected, and the data holding timing to the read data holding means is the timing at which the pre-read data at the time of the immediately preceding read on the priority side is held by the pre-read data holding means. And selecting means for selecting the output data of the memory when they overlap.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a buffer control using a one-port memory for absorbing a data transmission / reception speed difference between two peripheral devices. Read data holding means for temporarily holding data to be read, address updating means for updating the address of the memory at the time of reading on the priority side to an address to be read at the next access, and priority for the memory immediately after the address is updated Access arbitration means for reading out data of an update address from the memory, read-ahead data holding means for temporarily holding read-ahead data which is data of an update address which has been read with priority, and data holding timing to the read data holding means, The pre-read data at the time of the immediately preceding read is already held in the pre-read data holding means In the case of the read timing, the output data of the pre-read data holding unit is selected, and the data holding timing to the read data holding unit is such that the pre-read data at the time of the immediately preceding reading on the priority side is sent to the pre-read data holding unit. Selecting means for selecting the output data of the one-port memory when the timing for holding the data overlaps, and the read data holding means holds the output of the selecting means and makes a read response.

In addition to the above-mentioned invention, the present invention provides an access arbitration means for supplying an address of a priority side to a memory when neither of the two access systems has an access request, and a prefetch data holding means for supplying a priority to the memory. The side address is supplied to the memory and the read data is always taken in and held.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment) FIG. 1 is a block diagram showing a configuration of a memory access device according to an embodiment of the present invention. Note that components having the same configuration as the conventional example (FIG. 4) are denoted by the same reference numerals and description thereof is omitted.

In FIG. 1, a holding circuit 7 holds a read data holding unit and a buffer memory (hereinafter simply referred to as memory) for holding data to be output in response to reading from a host microcomputer (not shown). Reference numeral 8 denotes a one-port memory which is a buffer body, a selection circuit 9 switches a switch for accessing the memory 8 between a host microcomputer and a peripheral circuit (not shown) of another system, and a holding circuit 10 stores an address read by the host microcomputer. A pre-read data holding unit for holding data, a selection circuit 11 is a switch for switching data to be held in the holding circuit 7 between data of the holding circuit 10 and an output of the memory 8, and a timing circuit 12 is for reading operation from the host microcomputer. Accordingly, the counter 5 is updated while generating a data holding pulse to the holding circuit 7 to determine the read data. It generates the next address, performs prefetching access by switching the selection circuit 9 in accordance with the address update preferentially to the host microcomputer side, a timing management circuit which generates a timing pulse for holding the pre-read data to the holding circuit 10.

The access from the host microcomputer having the above configuration will be described with reference to the timing chart of FIG. First, in synchronization with the fall of the read pulse RE of the host microcomputer, the timing circuit 12 counts up the address counter 5 and holds the holding pulse (in
c). As a result, the read data output to the host microcomputer is determined by the holding circuit 7. At the same time, the address value is updated to the next accessed address. Next, the timing circuit 12 switches the supply address to the memory 8 to the output of the address counter 5 that has just been updated by generating an address switching pulse at the timing immediately after the address is updated and controlling the selection circuit 9. As a result, the update address data is output from the memory 8 one clock later, so that the timing circuit 12 generates a holding pulse to the holding circuit 10 in accordance with the timing, and holds the read data in the holding circuit 10. Let it.

With the above operation, while the data previously read in response to the reading by the host microcomputer is output, the prefetch operation of the next data is performed behind the data.
Therefore, at the time of reading by the next host microcomputer, the holding pulse (in
According to c), the data of the holding circuit 10 previously prefetched is taken into the holding circuit and the output is determined, whereby the host microcomputer can be responded to at the highest speed.

As described above, the response speed is maximized by promptly replying the pre-read data to the host microcomputer. Further, when the access cycle of the host microcomputer is shortened and the holding pulse (inc) to the holding circuit 7 and the holding pulse to the holding circuit 10 have the same timing as shown in FIG. 2, the selection circuit 11 is controlled. The memory 8 is also provided in the holding circuit 7 in the same manner as the holding circuit 10.
Hold the output directly. This allows the host microcomputer to normally respond even in the access cycle of the memory response limit.

As shown in FIG. 2, the memory access of the host microcomputer having a higher priority is only one clock during one access cycle of the host microcomputer. No RAM data timing is used. During this period (that is, other than immediately after the address is updated), the peripheral circuit accesses the memory 8 so that an appropriate buffer can be configured even with a one-port memory.

In order to hold the correct pre-read data in the holding circuit 10 even in the initial state of the circuit and to return the correct pre-read data even in the first access of the host microcomputer, as shown in FIG. If there is no access request (req-A) on the side of the peripheral circuit and no access request (req-B) on the side of the peripheral circuit having a low priority, the address of the high priority side is supplied to the memory 8, and the memory in such a case is supplied. By holding the output in the holding circuit 10, even if the counter 5 is in the initial state, the data at that address is stored in the pre-read data holding circuit 1.
0 can be reliably captured.

In this way, a buffer for speed absorption capable of providing the fastest response corresponding to the response limit of the memory can be constructed without inserting a wait state into the host microcomputer even though it is a one-port memory.

[0022]

As described above, according to the present invention, even in a one-port memory, the memory can be preemptively read at an appropriate timing to respond at the fastest speed to the host microcomputer without inserting a wait state. A normal response can be achieved even in an access cycle corresponding to the response limit of the memory without adding a fixed state for use. Thus, the same performance as that of the two-port memory can be obtained with a very simple configuration, and the effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory access device according to an embodiment of the present invention;

FIG. 2 is an access timing chart of the memory access device.

FIG. 3 is an access arbitration timing chart of the memory access device.

FIG. 4 is a block diagram showing a configuration of a conventional memory access device.

FIG. 5 is an access timing diagram of a conventional memory access device.

[Explanation of symbols]

 Reference Signs List 1 system bus 2 address decoder 3 timing circuit 4 input / output circuit 5 address counter 6 memory (2 ports) 7 holding circuit 8 memory (1 port) 9 selecting circuit 10 holding circuit 11 selecting circuit 12 timing circuit

Claims (2)

[Claims] In a buffer control using a one-port memory for absorbing a difference in data transmission / reception speed between two peripheral devices, data to be output is temporarily stored in response to data reading on a side where access is prioritized. Holding means for holding read data; address updating means for updating an address of the memory at the time of reading on the priority side with an address to be read in the next access; reading data of an updated address from the memory with priority given immediately after the address is updated Access arbitration means for performing prefetch data, prefetch data holding means for temporarily holding prefetch data, which is data of an update address which has been preferentially read, and a data holding timing to the read data holding means, which is one time before the priority side. When the pre-read data at the time of reading has already been held in the pre-read data holding means, In the case of reading, the output data of the prefetch data holding unit is selected, and the data holding timing to the read data holding unit causes the prefetch data holding unit to hold the prefetch data at the time of the immediately preceding reading on the priority side. Selecting means for selecting output data of the one-port memory when the timing overlaps, wherein the read data holding means holds the output of the selecting means and responds to reading. 2. An access arbitration unit supplies a priority address to a memory when neither of the two access systems has an access request, and a prefetch data holding unit supplies a priority address to the memory. 2. The memory access device according to claim 1, wherein the data read and read is always captured and held.