JP2002071718A - Semiconductor inspecting instrument and production method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To incorporate a circuit for inspection contained in a semiconductor chip to be inspected into a contactor of a probe card. SOLUTION: A contactor 7 is constituted of an Si board having a probe 15, an LSI chip 17 having a semiconductor inspection circuit and an Si tray 18 to match the joint position with the LSI chip 17 with a tapered mechanism 22. The Si board 16 is connected electrically and mechanically to the LSI chip 17 with a bump electrode 20, thereby enabling giving or taking of an electrical signal between the contactor 7 and the outside thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor inspection apparatus and a semiconductor device manufacturing technique, and more particularly, to an efficient inspection of electrical characteristics of a semiconductor element in a semiconductor manufacturing process such as a probing inspection and a burn-in inspection performed in a wafer state. The present invention relates to a semiconductor inspection apparatus to be used and a technique which is effective when applied to inspection of a semiconductor device using the semiconductor inspection apparatus.

[0002]

2. Description of the Related Art In a semiconductor device such as an LSI, a pre-process until an integrated circuit is formed on a surface of a semiconductor wafer, and a semiconductor wafer having an integrated circuit formed on the surface are divided into individual semiconductor chips. It is roughly divided into a post-process until sealing with resin or ceramic.

At a predetermined stage in the pre-process, an electrical characteristic test of each circuit formed on the surface of the semiconductor wafer is performed, and a non-defective or defective product is determined for each semiconductor chip. The electrical characteristics inspection is divided into probing inspection, which determines the continuity between each circuit and the quality of the element, and burn-in inspection, which applies thermal stress and electrical stress to the circuit in a high-temperature atmosphere and accelerates and determines defects. Is done.

In these probing inspections and burn-in inspections, the inspection is performed by bringing a probe into contact with a pad of a semiconductor chip. In this type of inspection, a special connection device (semiconductor inspection device) is used because the pads are extremely fine. For example, a probe card and a W that is obliquely (cantilever-shaped) from the probe card
(Tungsten) This is a connection device composed of a probe made of a needle. In the inspection by this connecting device, the above-mentioned pad is rubbed with a contact pressure by using a contact pressure utilizing the deflection of a probe, and the electrical characteristics thereof are inspected.

However, in manufacturing the above-described probe card, high processing accuracy is required in a horizontal position and a height at which the probe is mounted. Therefore, when the probe is mounted with a narrow pitch or a large number of pins, there is a problem that a high technology is required for the mounting. In addition, the demand for advanced technology has led to an increase in the manufacturing cost of the probe card.

In the case of a test in a high-temperature atmosphere such as a burn-in test, a material of the probe card which has a small amount of deformation with respect to a temperature change or a material having a thermal expansion coefficient close to that of the semiconductor chip is selected. Needed.

However, when a probe card having a narrow pitch or a large number of pins is used in the above-described inspection in a high-temperature atmosphere, a contact failure due to the bend of the probe card occurs, and the inspection yield is reduced. There was a case.

Further, in a WLBI (Wafer Level Burn-In) technique for performing a burn-in inspection collectively in a state of a semiconductor wafer before being divided into individual semiconductor chips, a multi-pin probe and a semiconductor wafer to be inspected are used. The pads are electrically connected. Therefore, a pressure mechanism (pneumatic pressure) for absorbing the difference in thermal expansion between the probe card and the semiconductor wafer and for uniformly pressing the probe over the entire surface of the semiconductor wafer.
Was needed. Furthermore, in the probe card, in order to make an electrical connection with the multi-pin probe,
It was necessary to form lead wires in multiple layers. Moreover,
In order to electrically connect the lead wiring to the LSI tester, it is necessary to form a pad on the probe card, and it is necessary to provide a region for forming the pad.

The following is an outline of the prior art studied by the present inventors to solve the above-mentioned problems.

That is, a technique using a probe composed of three layers of a multilayer wiring board, an anisotropic conductive rubber, and a polyimide substrate with bumps; a technique using a probe formed by VLS growth of Si (silicon); This is a technique that uses a probe card that is configured and has a contactor formed using a micromachining technique.

[0011] Techniques using a probe card having a contactor made of a Si material include, for example, (a) WO00 / 1610, (b) JP-A-7-283280, and (c) JP-A-10-239348. There is a description. In the above documents (a) to (c), BIST (Built In Sel) which is a semiconductor chip to be inspected is described.
f Test) ALPG (Algorith
There is also disclosed a technology for reducing the size of a semiconductor chip to be inspected by incorporating an inspection circuit such as an mic pattern generator (algorithmic pattern generator) into the above-mentioned contactor.

[0012]

SUMMARY OF THE INVENTION However, the present inventors have found that the above-mentioned prior art has the following problems.

That is, in the technique using a probe composed of three layers of a multilayer wiring board, an anisotropic conductive rubber, and a polyimide board with bumps, it is necessary to devise a method for collecting the lead-out wirings increased with the increase in the number of pins. Problem.

In the technique using a probe formed by VLS growth of Si, the load applied to the semiconductor chip to be inspected is restricted because the probe is perpendicular to the semiconductor chip to be measured. For this reason, there has been a problem that the application of the probe card is limited only when the pad of the semiconductor chip to be contacted with the probe is gold.

Further, the above-mentioned WO 00/1610, JP-A-7-283280, and JP-A-10-108
Japanese Patent Application Laid-Open No. 239348 discloses a technique for reducing the size of a semiconductor chip to be inspected by incorporating an inspection circuit incorporated in a BIST chip into a contactor made of a Si material. It does not disclose the circuit and its manufacturing method.
Since the test circuit and the contactor have different manufacturing methods, it has been difficult to manufacture a contactor incorporating the test circuit.

An object of the present invention is to provide a technique which enables stable WLBI in an electrical characteristic test of a semiconductor device.

Another object of the present invention is to provide a technique for incorporating an inspection circuit included in a semiconductor chip to be inspected into a contactor of a probe card, a socket or a card type socket.

Another object of the present invention is to provide a technique for incorporating a part or all of a circuit of a conventional expensive semiconductor inspection apparatus (LSI tester) into a probe card, a socket or a card-type socket contactor. is there.

Another object of the present invention is to provide a technique for increasing the number of electric signal pins of a conventional semiconductor inspection apparatus by n times using a probe card, a socket or a card type socket contactor.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0021]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the present invention, the electrical characteristics of (a) a first substrate formed of silicon, and (b) a semiconductor wafer or a semiconductor chip having semiconductor elements, wirings and electrode pads formed on a main surface thereof are determined. A second substrate having a first circuit to be inspected, and (c) a third substrate for determining a bonding position between the first substrate and the second substrate, wherein a third substrate is provided at one or more locations on the first substrate. A probe is formed in one region, and a first wiring electrically connected to the first circuit is formed on a surface of the probe and a surface or inside of the first substrate, and the first substrate and the second substrate are formed. Is electrically and mechanically connected by a first electrode formed on the second substrate.

Further, the present invention provides (a) a first substrate formed of silicon, and (b) a semiconductor element, wiring,
A second substrate having a first circuit for inspecting electrical characteristics of a semiconductor wafer or a semiconductor chip on which electrode pads, rewiring and bump electrodes are formed; and (c) a bonding position between the first substrate and the second substrate. A probe is formed in a first region provided at one or more locations on the first substrate, and the first circuit is provided on a surface of the probe and a surface of or inside the first substrate. A first wiring electrically connected to the first substrate is formed, and the first substrate and the second substrate are
It is electrically and mechanically connected by a first electrode formed on the second substrate.

Further, the present invention provides a method for measuring the electrical characteristics of (a) a first substrate formed of silicon, and (b) a semiconductor wafer or a semiconductor chip having semiconductor elements, wirings and electrode pads formed on a main surface thereof. A second substrate having a first circuit to be inspected, and (c) a third substrate for determining a bonding position between the first substrate and the second substrate, wherein a third substrate is provided at one or more locations on the first substrate. A probe is formed in one region, and a first wiring electrically connected to the first circuit is formed on a surface of the probe and a surface or inside of the first substrate, and the first substrate and the second substrate are formed. Is electrically and mechanically connected by a first electrode formed on the second substrate, and the first substrate, the second substrate, and the third substrate are each They can be exchanged individually.

According to the present invention, (a) a first substrate formed of silicon and provided with a first region including a probe, and (b) a semiconductor element, wiring and electrode pads are formed on a main surface. A semiconductor inspection apparatus having a second substrate having a first circuit for inspecting electrical characteristics of a semiconductor wafer or a semiconductor chip and (c) a first wiring for electrically connecting the probe and the first circuit is used. Preparing the semiconductor wafer or the semiconductor chip, and electrically contacting the probe and the electrode pad by pressure due to the deformation of the first region,
The method includes a step of transmitting and receiving an electric signal between the electrode pad and the first circuit, and a step of inspecting an electric characteristic of the semiconductor wafer or the semiconductor chip by the first circuit.

Also, the present invention provides (a) a first substrate formed of silicon and having a first region including a probe, and (b) a semiconductor element, wiring, electrode pad, rewiring on a main surface. A second substrate having a first circuit for inspecting electrical characteristics of a semiconductor wafer or a semiconductor chip on which bump electrodes are formed, and (c) a first wiring for electrically connecting the probe and the first circuit. A step of preparing the semiconductor wafer or the semiconductor chip, and a step of electrically contacting the probe and the electrode pad with a pressure due to the deformation of the first region, A step of transmitting and receiving an electric signal between the electrode pad and the first circuit; and a step of inspecting an electric characteristic of the semiconductor wafer or the semiconductor chip by the first circuit. It is intended.

According to the present invention, the first circuit for inspecting the electrical characteristics of the semiconductor chip to be inspected is transferred from the semiconductor chip to be inspected to the second substrate of the semiconductor inspection apparatus. Can be realized.

Further, according to the present invention, the electrical contact between the probe and the electrode pad of the semiconductor wafer or the semiconductor chip to be inspected is good due to the pressure due to the deformation of the first region where the probe is formed. Therefore, it is not necessary to provide a pressurizing mechanism such as an air pressure in the first region itself.

According to the present invention, the first substrate including the probe and the second substrate having the first circuit for inspecting the electrical characteristics of the semiconductor chip to be inspected are manufactured separately. It is possible to prevent the second substrate from being contaminated by an aqueous solution of potassium hydroxide used in manufacturing one substrate.

Further, according to the present invention described above, a semiconductor inspection apparatus is constructed, and a second circuit having a first circuit for inspecting electrical characteristics of a first substrate including a probe, a semiconductor wafer to be inspected or a semiconductor chip to be inspected is provided. Since the substrate and the third substrate that determines the bonding position between the first substrate and the second substrate are individually manufactured, the first substrate, the second substrate, and the third substrate are formed as compared with the case where the first substrate, the second substrate, and the third substrate are integrally formed. It is possible to simplify the manufacturing process of each of the first substrate, the second substrate, and the third substrate.

Further, according to the present invention, a semiconductor inspection apparatus is configured, and a second circuit having a first circuit for inspecting electrical characteristics of a first substrate including a probe, a semiconductor wafer to be inspected or a semiconductor chip to be inspected is provided. The substrate and the third substrate that determines the bonding position between the first substrate and the second substrate are individually manufactured, and the type of the semiconductor wafer or the semiconductor chip to be inspected and the inspection performed on the semiconductor wafer or the semiconductor chip to be inspected Since various first circuits are formed on the second substrate in accordance with the type of the semiconductor device, it is possible to manufacture the semiconductor inspection apparatus corresponding to various types of semiconductor wafers or semiconductor chips to be inspected.

Further, according to the present invention, the first substrate,
Since the second substrate and the third substrate can be individually replaced as needed, the semiconductor substrate to be inspected or the substrate to be inspected can be replaced by replacing the second substrate with a second substrate having another first circuit. Inspection of other electrical characteristics can be performed on the inspection semiconductor chip.

Further, according to the present invention, the first substrate,
Since the second substrate and the third substrate can be individually replaced as needed, maintenance of the semiconductor inspection apparatus can be facilitated.

Further, according to the present invention, the first substrate,
Since the second substrate and the third substrate can be individually exchanged as needed, the first substrate, the second substrate, and the third substrate are individually exchanged even in a semiconductor inspection device manufactured in the past. Thus, a new function can be added to the semiconductor inspection device. That is, a semiconductor inspection device manufactured in the past can be reused.

Further, according to the present invention, the semiconductor inspection apparatus can be manufactured corresponding to various kinds of semiconductor wafers or semiconductor chips to be inspected, so that the application range of the inspection performed by the semiconductor inspection apparatus is limited. It becomes possible to spread.

Further, according to the present invention, a semiconductor inspection apparatus is constructed, and a second circuit having a first circuit for inspecting electrical characteristics of a first substrate including a probe, a semiconductor wafer to be inspected or a semiconductor chip to be inspected is provided. Since the manufacturing steps of the substrate and the third substrate for determining the bonding position between the first substrate and the second substrate can be simplified, the manufacturing cost of the semiconductor inspection device can be reduced.

Further, according to the present invention, a semiconductor inspection apparatus is constructed, and a second circuit having a first circuit for inspecting electrical characteristics of a first substrate including a probe, a semiconductor wafer to be inspected or a semiconductor chip to be inspected is provided. Since the substrate and the third substrate for determining the bonding position between the first substrate and the second substrate are formed of the same material as the semiconductor wafer or the semiconductor chip to be inspected, a probing inspection or a burn-in inspection in a high-temperature atmosphere To prevent the probe from being distorted due to the difference in thermal expansion between the semiconductor wafer or the semiconductor chip to be inspected, the first substrate, the second substrate, and the third substrate, and to prevent the probe from bending due to thermal expansion. It becomes possible.

Further, according to the present invention, in a probing inspection or a burn-in inspection in a high-temperature atmosphere, a semiconductor wafer to be inspected or a semiconductor chip to be inspected is
A first substrate including a probe, constituting a semiconductor inspection device;
It is caused by a difference in thermal expansion between a second substrate having a first circuit for inspecting electrical characteristics of a semiconductor wafer or a semiconductor chip to be inspected and a third substrate which determines a bonding position between the first substrate and the second substrate. As a result, it is possible to prevent the probe from being distorted and to prevent the probe from bending due to thermal expansion, so that it is possible to prevent contact failure between the probe and the semiconductor wafer or the semiconductor chip to be inspected.

[0039]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

The ASIC (Application Specif) shown in FIG.
The IC 1 is an example (block diagram) of a semiconductor chip whose electrical characteristics are inspected by the semiconductor inspection apparatus of the present embodiment, and is a DRAM (Dynamic Random Acc.).
ess Memory) 2 and a logic circuit 3. The DRAM 2 and the logic circuit 3 are ASIC
1 is electrically connected to a semiconductor inspection circuit (first circuit) 4 formed outside the semiconductor chip on which the semiconductor bus 1 is formed, via a DRAM bus 5, a tester bus 6, and the like.

The above-described semiconductor inspection circuit 4 corresponds to FIGS.
The probe card is formed inside a probe card described later with reference to FIG. 4, a socket with a test function described later with reference to FIG. 4, and a socket with a card type test function described later with reference to FIG.
Therefore, it is not necessary to form the semiconductor inspection circuit 4 inside the semiconductor chip on which the ASIC 1 is formed.
The size of the semiconductor chip on which the SIC 1 is formed can be reduced.

According to experiments conducted by the present inventors, ASI
When the semiconductor test circuit 4 is formed outside the semiconductor chip on which C1 is formed, the size of the semiconductor chip is reduced by about 1 in comparison with the case where the semiconductor test circuit 4 is formed inside the semiconductor chip. % To about 10%. In addition, it was found that the manufacturing cost of the semiconductor chip can be reduced by about 10% or more by forming the semiconductor inspection circuit 4 outside the semiconductor chip on which the ASIC 1 is formed.

Next, an example of a probe card (semiconductor inspection apparatus) to which the present invention is applied is shown in FIG.

The probe card shown in FIG. 2 has a contactor 7 formed by processing a Si material using a micromachining technique, a substrate 8 having a multilayer wiring formed therein, a connector pin 9, a holding plate. 10 and a reinforcing plate 11. The connector pin 9 is
The contactor 7 and the substrate 8 are electrically connected, for example, by a spring probe. The holding plate 10 and the reinforcing plate 11 can be formed of, for example, stainless steel, aluminum, an Invar alloy, or the like.

At the interface between the contactor 7 and the holding plate 10 and at the interface between the substrate 8 and the holding plate 10, a low elasticity sheet 12 made of Si rubber or the like is inserted. Further, the contactor 7 and the holding plate 10 are bonded by a low elastic adhesive 13 made of, for example, a Si adhesive. The Si substrate 16 and the Si tray 18 described later with reference to FIG.
Are also adhered by the low elasticity adhesive 13. The contactor 7, the holding plate 10, and the reinforcing plate 11 are fixed by screws 14.

Next, the above-mentioned contactor 7 will be described with reference to FIG.
It is shown enlarged. FIG. 3B is an enlarged view of the vicinity of the probe 15 shown in FIG.

As shown in FIG. 3A, the contactor 7
Is a Si substrate (first substrate) 16 having a probe 15
, LSI chip (second substrate) 17 and LSI chip 1
And a Si tray (third substrate) 18 on which the 7 is mounted. The wiring (first wiring) 19 made of metal is formed on the surface of the Si substrate 16 including the probe 15. Also, the Si substrate 16 and the LSI chip 17
They are electrically and mechanically connected by bump electrodes (first electrodes) 20 formed on the substrate 16 or the LSI chip 17. The wiring 19 is electrically connected to the bump electrode 20, and the contactor 7 exchanges an electric signal with the outside via the wiring 19 and the bump electrode 20. Wiring 19 is provided on the surface of Si substrate 16 including probe 15.
Forming the wiring 19 outside the Si substrate 16
Can be made shorter than in the case of forming. Further, since the wiring 19 can be shortened,
The probe card of the present embodiment can be reduced in size.

The LSI chip 17 has the semiconductor inspection circuit 4 described above with reference to FIG. 1. Various semiconductor inspection circuits 4 will be specifically described later with reference to FIGS.

Although FIG. 3A shows that one LSI chip 17 is provided in the contactor 7, two or more LSI chips 17 may be provided as necessary.
May be provided. Thus, for example, when testing the electrical characteristics of ASIC 1 described with reference to FIG. 1, it is possible to simultaneously test the electrical characteristics of DRAM 2 and logic circuit 3. According to the experiment performed by the present inventors, the electrical characteristics of the DRAM 2 and the logic circuit 3 can be inspected at the same time.
It has been found that the inspection process of the electrical characteristics of the SIC 1 can be reduced by about ３ to 、 compared to the case where the electrical characteristics of the DRAM 2 and the logic circuit 3 are individually measured. Further, the inspection process of the electrical characteristics of the ASIC 1 is performed by DR
As compared with the case where the electrical characteristics of the AM 2 and the logic circuit 3 are individually measured, the time required for testing the electrical characteristics of the ASIC 1 can be reduced by about 30% or more because the electrical characteristics can be reduced by about 1/3 to 1/2. I understood. further,
The inspection process of the electrical characteristics of the ASIC 1 can be reduced by about ３ to 比 べ compared to the case where the electrical characteristics of the DRAM 2 and the logic circuit 3 are individually measured. Since the time can be reduced by about 30% or more, it has been found that the cost for inspecting the electrical characteristics of the ASIC 1 can be reduced by about 30% or more.

The above-mentioned Si substrate 16 and LSI chip 17
The Si tray 18 and the Si tray 18 are individually manufactured using a semiconductor element forming technique and a multilayer wiring forming technique.
Thereafter, the manufactured Si substrate 16, LSI chip 17 and Si tray 18 are joined by the low-elasticity adhesive 13 and the bump electrode 20 to be integrated. Further, when the Si substrate 16, the LSI chip 17 and the Si tray 18 are joined, the joining positions can be adjusted by the positioning mechanism 21. Further, the Si tray 18 is provided with a taper mechanism 22 for mounting the LSI chip 17 at a predetermined position using an automatic mounting machine.

Here, FIG.
As shown in (b), the probe 15 is formed on a beam (first region) 23 of the Si substrate 16. As the structure of the beam 23, either a cantilever beam or a doubly supported beam may be used. On the main surface of the semiconductor wafer 24 to be inspected, semiconductor elements, multi-layered wiring, electrode pads, rewiring for rearranging the electrode pads, and bump electrodes (not shown) are formed.

The beam 23 can be easily deformed, and the probe 15
The electrical contact between the probe 15 and the bump electrode formed on the semiconductor wafer 24 to be inspected can be satisfactorily performed by the pressure due to the deformation of the beam 23 when the probe 15 contacts the bump electrode of the semiconductor wafer 24 to be inspected. Therefore, beam 23
It is not necessary to provide a pressurizing mechanism such as an air pressure in itself. The probe 15 can be processed into a quadrangular pyramid or a needle-like projection by dry etching or wet etching using a KOH (potassium hydroxide) aqueous solution. Note that the positioning mechanism 21 can also be formed in the same step as the step of forming the probe 15. In the present embodiment, the case where one beam 23 is formed on the Si substrate 16 and one probe 15 is formed on the beam 23 has been described as an example, but it is formed from the semiconductor wafer 24 to be inspected. As many beams 23 and probes 15 as necessary to simultaneously contact a plurality or all of the semiconductor chips may be formed. Thus, the inspection of the electrical characteristics of the semiconductor wafer 24 to be inspected can be performed at the semiconductor wafer level.

When the LSI chip 17 is formed, in order to prevent the LSI chip 17 from being contaminated by a KOH aqueous solution, a wet etching method using a KOH aqueous solution is not used in the manufacturing process. In the present embodiment, the Si substrate 16 and the LSI chip 17
Is manufactured individually, so that the LSI chip 17 can be prevented from being contaminated by the KOH aqueous solution used in manufacturing the Si substrate 16.

In the present embodiment, the Si substrate 16, the LSI chip 17, and the Si tray 18 are individually manufactured. Therefore, the number of masks to be used can be reduced as compared with the case where the contactor 7 is formed as an integral type, so that the manufacturing process of each of the Si substrate 16, the LSI chip 17, and the Si tray 18 is facilitated and the number of processes is reduced. be able to. Therefore, the contactor 7
Can be reduced in manufacturing cost. According to an experiment conducted by the present inventors, when the Si substrate 16, the LSI chip 17, and the Si tray 18 are individually manufactured, the manufacturing is more difficult than when the contactor 7 is integrally formed. It was found that the cost could be reduced to about half.

Further, since the manufacturing process of each of the Si substrate 16, the LSI chip 17, and the Si tray 18 can be facilitated, the manufacturing yield of the contactor 7 can be improved.

When the probe card of the present embodiment shown in FIG. 2 is used for a probing test at about 90 ° C. or more or a burn-in test at about 120 ° C. or more, for example, the probe card is 24
Since the contactor 7 is made of the same Si material as above, it is possible to prevent the probe 15 from being distorted due to a difference in thermal expansion between the semiconductor wafer 24 to be inspected and the contactor 7. Therefore, it is possible to prevent contact failure between the probe 15 and the semiconductor wafer 24 to be inspected due to the distortion of the probe 15. In addition, since a contact failure between the probe 15 and the semiconductor wafer 24 to be inspected can be prevented, it is possible to prevent a decrease in the inspection yield of the probe card of the present embodiment.

In this embodiment, as described with reference to FIG. 3, the probe 15 is formed by a wet etching technique or a dry etching technique. Therefore, in the case where the probe 15 is formed by the wet etching technique or the dry etching technique, the processing accuracy is reduced with less variation in the horizontal position and the height as compared with the case of setting up a cantilever-shaped probe made of W by hand. be able to. That is,
Since the processing accuracy can be reduced with less variation in the horizontal position and the height, the probe card of the present embodiment can be easily manufactured even when the probe 15 has a narrow pitch or a large number of pins. Therefore, the manufacturing cost of the probe card according to the present embodiment can be reduced. According to experiments performed by the present inventors, 8
When a probe card having a probe 15 having 00 pins or more is formed by using the above-described wet etching technique or dry etching technique, the manufacturing cost is reduced.
It was found that the size of the probe can be reduced to about one tenth as compared with the case of setting up a cantilever-shaped probe made of W by hand.

Further, when the probe 15 is formed by a wet etching technique or a dry etching technique, the processing accuracy can be reduced with less variation in the horizontal position and the height, so that the probe 15 is used for, for example, a burn-in inspection performed at a semiconductor wafer level. It is possible to manufacture a probe card having the probe 15 having about 10,000 pins or more with high accuracy. That is, when the probe card according to the present embodiment is used, it is possible to inspect the electrical characteristics at the semiconductor wafer level.

In the present embodiment, the Si substrate 16, the LSI chip 17, and the Si tray 18 are manufactured individually. Further, the semiconductor wafer 2 to be inspected
Various types of semiconductor inspection circuits 4 are formed on the LSI chip 17 in accordance with the type of the semiconductor device 24 or the type of inspection performed on the semiconductor wafer 24 to be inspected. Therefore, it becomes possible to manufacture the probe card of the present embodiment in correspondence with various kinds of semiconductor wafers 24 to be inspected. That is, it is possible to expand the application range of the inspection performed by the probe card of the present embodiment. Further, when manufacturing the probe card of the present embodiment, if the existing LSI chip 17 can be used, it is not necessary to manufacture a new LSI chip 17. That is, in manufacturing the probe card of the present embodiment, when the existing LSI chip 17 can be used, the manufacturing cost can be reduced.

In the present embodiment, the Si substrate 16, the LSI chip 17, and the Si tray 18 can be individually replaced as needed. Therefore, LS
LSI having another semiconductor inspection circuit 4 as I chip 17
By replacing the chip 17 with another, the inspection of other electrical characteristics of the semiconductor wafer 24 to be inspected can be performed.

Further, the Si substrate 16 and the LSI chip 17
The Si tray 18 and the Si tray 18 can be individually replaced as needed, so that maintenance of the probe card of the present embodiment can be facilitated.

Further, since the Si substrate 16, the LSI chip 17, and the Si tray 18 can be individually exchanged as needed, the Si substrate 16, the probe card of the present embodiment manufactured in the past, can be used. A new function can be added to the probe card by replacing each of the LSI chip 17, the LSI chip 17, and the Si tray 18 individually. That is, the probe card of the present embodiment manufactured in the past can be reused.

Next, an example of a socket with a test function (semiconductor test apparatus) to which the present invention is applied is shown in FIG.

The socket with the inspection function shown in FIG.
An SI chip 31, a Si tray 32, and a Si substrate 33 having a multi-layered wiring formed therein are housed in a housing 34 made of resin or metal. The housing 34 has a structure in which it is opened up and down with the spring-loaded fixing pin 35 as a fulcrum, and is closed when the semiconductor chip 36 to be inspected made of Si material is inspected.
7 fixed so as not to open. Further, the Si substrate 33 has a structure in which electrical connection with the outside is established through the connector pins 38.

The interface between the Si tray 32 and the housing 34 and the interface between the semiconductor chip 36 to be inspected and the housing 34 are
A low elastic sheet 39 made of i-rubber or the like is inserted.
The Si tray 32 and the LSI chip 31 are connected to the housing 3 by a low elastic adhesive 40 made of, for example, Si adhesive.
4 is adhered.

The Si tray 32 and the Si substrate 33 are
The joining position can be adjusted by a positioning mechanism 41 similar to the positioning mechanism 21 described above. Further, the Si tray 32 is formed with a taper mechanism 42 for mounting the semiconductor chip 36 to be inspected at a predetermined position by using an automatic mounting machine.

The surface of the LSI chip 31 or the Si substrate 3
On the surface of No. 3, bump electrodes 43 and 44 are formed, respectively. The LSI chip 31 and the Si substrate 33 are joined by the bump electrodes 43. The bump electrode 4
4 is a pad portion of the semiconductor chip 36 to be inspected (not shown).
In this case, the semiconductor chip 36 to be inspected can be fixed.

On the surface and inside of the Si substrate 33, a wiring 45 for electrically connecting the bump electrode 43 and the bump electrode 44 described above is formed. That is, the LSI chip 31 and the semiconductor chip 3 to be inspected are electrically connected to the bump electrode 43 and the bump electrode 44.
6 can be electrically connected.

The LSI chip 31 has a semiconductor inspection circuit 4 in the same manner as the LSI chip 17 described above with reference to FIG. 3, and various semiconductor inspection circuits 4 are shown in FIGS.
This will be described in detail later. As mentioned above, LSI
Since the chip 31 and the semiconductor chip 36 to be inspected can be electrically connected, various inspections can be performed on the semiconductor chip 36 using the semiconductor inspection circuit 4 included in the LSI chip 31. In FIG. 4, one L is attached to the socket with the inspection function of the present embodiment.
This shows that the SI chip 31 is provided,
If necessary, two or more LSI chips 31 may be provided. Thus, for example, the ASI described with reference to FIG.
When inspecting the electrical characteristics of C1, a DRAM
2 and the electrical characteristics of the logic circuit 3 can be inspected simultaneously.

In the socket with the inspection function of the present embodiment, the LSI chips 31 are manufactured individually. Also,
According to the type of the semiconductor chip 36 to be inspected or the type of inspection to be performed on the semiconductor chip 36 to be inspected, the LSI chip 31
Various semiconductor inspection circuits 4 are formed. Therefore, the socket with an inspection function according to the present embodiment can be manufactured in correspondence with various kinds of semiconductor chips 36 to be inspected. That is, it is possible to expand the application range of the inspection performed by the socket with an inspection function according to the present embodiment.

Next, an example of a socket (semiconductor inspection apparatus) with a card type inspection function to which the present invention is applied is shown in FIG.
As a socket with this card type inspection function, for example,
A PC card used in a personal computer can be exemplified.

In the socket with a card type inspection function shown in FIG. 5, a Si tray 52 and a Si substrate 53 having a multilayer wiring formed therein are housed in a housing 54 made of resin or metal. It is configured. Also, S
The i-substrate 53 has a structure in which electrical connection with the outside is established via the connector substrate 55.
3 and the connector board 55 are electrically connected by a metal wire 56 made of Au, Al (aluminum), an alloy thereof, or the like. Also, the Si tray 52
A low elastic sheet 58 made of Si rubber or the like is inserted at an interface between the semiconductor chip 57 and the housing 54 and an interface between the semiconductor chip 57 to be inspected and the housing 54. Although FIG. 5 illustrates an example in which two semiconductor chips 57 to be inspected are incorporated in the housing 54, the number is not limited to two and one or more semiconductor chips can be incorporated.

The Si tray 52 and the Si substrate 53 are the same as those shown in FIG.
The joining position can be adjusted by a positioning mechanism 61 similar to the positioning mechanism 21 described above. Further, the Si tray 52 is formed with a taper mechanism 62 for mounting the semiconductor chip 57 to be inspected at a predetermined position using an automatic mounting machine.

A bump electrode 63 made of Au or solder is formed on the surface of the Si substrate 53. The semiconductor chip 57 to be inspected can be fixed by incorporating the bump electrode 63 into a pad portion (not shown) of the semiconductor chip 57 to be inspected.

On the surface and inside of the Si substrate 53, wirings 64 for electrically connecting the bump electrodes 63 described above are formed. That is, the bump electrode 6
The plurality of semiconductor chips 57 to be inspected can be electrically connected to each other by electrically connecting the three semiconductor chips 57 to each other. In addition, the bump electrode 63 is formed of Au or solder.

FIG. 5 showing a semiconductor inspection apparatus according to the present embodiment.
In the socket with the card type inspection function shown in (1), for example, the housing 54 is actually incorporated into a personal computer or the like, and the operation as a PC card described above is confirmed.
Inspection target semiconductor chip 57 incorporated in housing 54
Can be inspected. In addition, in the inspection, when no defect is found in the electrical characteristics of the semiconductor chip 57 to be inspected, the socket with the card type inspection function of the present embodiment can be commercialized as a PC card. .

One of the plurality of semiconductor chips 57 to be inspected incorporated in the housing 54 is the same as the LSI chip 17 described with reference to FIG. 3 and the LSI chip 31 described with reference to FIG. LSI chip of
In the socket itself with the card type inspection function of the present embodiment,
It may be configured to have a function of inspecting the electrical characteristics of the semiconductor chip 57 to be inspected.

Next, the semiconductor test circuit 4 included in the LSI chips 17 and 31 described with reference to FIG. 1 and FIGS. 3 to 5 will be specifically described with reference to FIGS.

The circuit (block diagram) shown in FIG. 6 is a BOST (Built Out Out) which is an example of the semiconductor inspection circuit 4 described above.
Self Test) circuit. This BOST circuit is obtained by replacing the BIST circuit incorporated in the semiconductor wafer or the semiconductor chip to be inspected with the LSI chips 17 and 3 described above.
It has been relocated to 1. Therefore, the size of the semiconductor chip to be inspected can be reduced by the size of the BIST circuit compared to the semiconductor chip to be inspected in which the BIST circuit is formed.

Further, the BOST circuit can perform a test without receiving a large amount of test patterns from the outside (tester) by generating a pseudo-random number for the test and compressing the data.

As shown in FIG. 6, the BOS of this embodiment
The T circuit includes, for example, an interface circuit 71, a pattern memory 72, a register 73, a calculator 74 for performing address and data calculations, a sequencer 75, and an output controller 7.
6 and a determination circuit 77.
The above-described generation of the pseudo-random number for inspection is performed in the pattern memory 7.
2. Performed by the register 73 and the arithmetic unit 74, and the data compression is performed by the output controller 76.
After outputting the signal 78 to the semiconductor chip to be inspected, the data 79 returned from the semiconductor chip to be inspected is inspected by the judgment circuit 77, so that the presence or absence of a defect in the electrical characteristics of the semiconductor chip to be inspected can be determined. .

The above-mentioned B is placed inside the semiconductor chip to be inspected.
In forming the IST circuit, a BIS including a data latch circuit 80, a control CPU 81, a test program storage ROM 82, and the like as shown in FIG.
The T control circuit may be provided in the semiconductor chip to be inspected. By providing the BIST control circuit, it is possible to generate a different pseudo-random number for inspection for each circuit block formed in the semiconductor chip to be inspected and perform data compression. That is, it is possible to apply an optimum test pattern according to each circuit block. As a result, each circuit block can be tested independently and simultaneously,
It is possible to reduce the time for inspecting the semiconductor chip to be inspected.

In the present embodiment, for example, a BIST circuit having the same configuration as the BOST circuit shown in FIG. 6 is left in the semiconductor chip to be inspected, and the above-mentioned BIST control circuit is changed from the semiconductor chip to be inspected to the aforementioned LSI chip. Transfer to 17 and 31. Therefore, the size of the semiconductor chip to be inspected can be made smaller by the BIST control circuit than the semiconductor chip to be inspected in which the BIST control circuit is formed.

The circuit (block diagram) shown in FIG. 8 is an example of the semiconductor test circuit 4 described above, and is an ALPG circuit which is a type of the BOST circuit described above with reference to FIG. This ALPG circuit can be composed of, for example, a clock generator 91, a sequence controller 92, an address generator 93, a microprogram memory 94, and a data generator 95. Note that the clock generator 91 is the same as that of FIG.
It may be provided outside the LSI chips 17 and 31 described above with reference to FIGS.

The above-described ALPG circuit writes data to a memory cell such as a DRAM, for example, according to the input rate 96, and then reads data from the memory cell to check whether the memory cell operates properly. I do. The inspection includes, for example, an inspection of a decoder section and an inspection of interference between memory cells.
In these inspections, the control signal pattern 9
7, by generating a data pattern 98 and an address pattern 99. The generation of the constant operation and control signal pattern 97, data pattern 98 and address pattern 99 is performed by the clock generator 91, sequence controller 92, and address generator 9 described above.
3. Performed by microprogram memory 94 and data generator 95.

In the ALPG circuit, control signal pattern 97, data pattern 98 and address pattern 9
Since 9 can be generated by calculation, it is possible to simplify a program for the above-described inspection.

The ASIC 1 shown in FIG.
For example, when testing a system LSI in which a memory unit such as a DRAM and a logic circuit coexist, a memory tester is used for testing the memory unit, and a logic tester is used for testing the logic circuit unit. It was common to use the test. In addition, when the function of a memory tester and the function of a logic tester are incorporated into one tester for the purpose of reducing the test process of the electrical characteristics of the system LSI, a new tester may be introduced. The cost of the tester has become high. Therefore, the LSI chip 17 included in the probe card described with reference to FIGS. 2 and 3 and the LSI chip 31 included in the socket with a test function described with reference to FIG.
Then, various semiconductor inspection circuits such as the above-described ALPG circuit are incorporated. That is, by incorporating various semiconductor inspection circuits such as the above-described ALPG circuit into the LSI chip 17 and the LSI chip 31, the probe card described in FIGS. 2 and 3 can be used without introducing a new tester. 4 can be used. That is, when the probe card or the socket with the inspection function of the present embodiment is used, the number of steps for inspecting the electrical characteristics of the system LSI can be reduced without increasing the cost of the tester.

The circuit (block diagram) shown in FIG. 9 is a memory test pattern circuit as an example of the semiconductor test circuit 4 described above, and is an N-system test pattern circuit which is a type of the BOST circuit described above with reference to FIG. . The N-system test pattern circuit includes, for example, a test clock generator 101, a pattern program memory 102, a program counter 10
3. It can be composed of an address counter 104 and a data generator (determiner) 105.

The basic operation of the above-described N-system test pattern circuit is to write all the words in the memory section to be inspected and then sequentially read out all the bits. Therefore, in the N-system test pattern circuit, the number of test patterns applied to the memory unit in the inspection of the electrical characteristics of the memory unit of the system LSI is proportional to the number N of words in the memory unit. Further, since the number of test patterns applied to the memory unit is proportional to the number N of words in the memory unit, the number of test patterns does not increase exponentially even if the memory capacity of the inspection target increases. That is, the N-system test pattern circuit can be easily applied to inspection of electrical characteristics of a large-capacity memory.

The circuit (block diagram) shown in FIG.
Memory test pattern circuit as an example of the completed semiconductor test circuit 4
This is a kind of the BOST circuit described above with reference to FIG.
N ^TwoThis is a system test pattern circuit. This N^TwoSystem test pass
The turn circuit includes, for example, a test clock generator 111,
Loop counter 112, program counter 113,
Turn program ROM 114, address counter 11
5. Data generator (determiner) 116, base register 1
17 and a switch 118.

The above-described N ² -system test pattern circuit is basically based on checking a combination of all the other words with the word to be tested in the memory section of the system LSI. It is proportional to the square of the number N of words in the inspection memory unit. for that reason,
The N ² system test pattern circuit is the same as the N 2
Compared with the system test pattern circuit, the ability to detect various electrical defects in the inspection of the electrical characteristics of the memory portion of the system LSI can be improved.

The circuit (block diagram) shown in FIG.
Is a pin multiplexer circuit which is an example of the semiconductor inspection circuit 4 described above and is a kind of the BOST circuit described above with reference to FIG. In the pin multiplexer circuit, an electronic circuit including, for example, a flip-flop 122, an address decoder 123, an inverter, and a relay as shown in FIG.

The above-described pin multiplexer circuit can multiplex a plurality of signals in one channel. Therefore, it is possible to sequentially switch and output the input signal, or to temporarily store the input signal and select and output one of the input signals later. For example, a semiconductor inspection apparatus having a 16-pin probe can inspect electrical characteristics of 32 semiconductor chips, which is twice the number of pins of the probe.

[0094] FIGS. 6 11 BOST circuit described with reference to, BIST control circuit, ALPG circuit, N type test pattern circuit, of the N ² type test pattern circuit and pin multiplexer circuit, a semiconductor which is a combination of all or some The test circuit may be incorporated in the LSI chip 17 of the probe card described with reference to FIGS. 2 and 3 and the LSI chip 31 of the socket with a test function described with reference to FIG. In addition, the above-described BOST circuit, BIST control circuit, ALPG
Circuit, N type test pattern circuit, the N ² system test pattern circuit and pin multiplexer circuit may be incorporated into the LSI chip 17 and the LSI chip 31 alone as described above.

Next, a method of manufacturing a semiconductor device using the semiconductor inspection device of the present embodiment will be described with reference to the flowchart shown in FIG.

First, in step P1, an element isolation region is defined for each semiconductor chip formation region on a semiconductor wafer made of, for example, a Si material. Subsequently, a film forming process,
By forming a gate electrode and a source / drain region by a diffusion step, a photolithography step, an etching step, etc., a MOSFET (Metal OxideSem) is formed.
iconductor Field Effect Transistor) is completed. Subsequently, an insulating film and the above-described MOSFE are formed on the main surface of the semiconductor wafer by repeating, for example, a film forming process, a photolithography process, and an etching process.
Wirings electrically connected to T are formed in multiple layers.

Next, in step P2, the threshold voltage (V _th ) of the MOSFET formed in step P1 is measured to confirm whether the threshold voltage has a predetermined value.

Next, in step P3, a probe test (burn-in test) is performed on the above-described semiconductor wafer.
At this time, for example, the probe card of the present embodiment described with reference to FIGS. 2 and 3 is used. The probe card is a contactor 7 made of the same Si material as the semiconductor wafer.
Therefore, it is possible to prevent the probe 15 from being distorted due to a difference in thermal expansion between the semiconductor wafer and the contactor 7. Therefore, it is possible to prevent the inspection yield of the probe card according to the present embodiment from being lowered due to the contact failure between the probe 15 and the semiconductor wafer.

Next, in step P4, the semiconductor wafer on which the MOSFET and the multilayer wiring are formed for each semiconductor chip forming region is cut into individual semiconductor chips by, for example, dicing. Subsequently, for example, the cut-out semiconductor chip is die-bonded to a lead frame and subsequently wire-bonded, thereby electrically connecting an electric circuit formed on the semiconductor chip and a lead of the package.

Subsequently, after the semiconductor chip is sealed with a resin or the like, the leads outside the package are plated, and the leads are formed into a final shape.

Next, in a process P5, various final inspections are performed on the above-described package to manufacture the semiconductor device of the present embodiment.

Incidentally, between the steps P4 and P5, a burn-in inspection may be performed on the semiconductor chip. In this case, for example, the probe card described with reference to FIGS. 2 and 3, the socket with a test function described with reference to FIG. 4, or the socket with a card-type test function described with reference to FIG. 5 can be used.

Although the invention made by the present inventors has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and may be made without departing from the scope of the invention. It goes without saying that various changes can be made.

For example, in the above-described embodiment, a case has been described in which the wiring is formed on the surface of the Si substrate including the probe constituting the contactor.

Further, the semiconductor inspection device of the present invention
The present invention is not limited to inspection of electrical characteristics of an ASIC in which M and logic circuits are mixed, but can be used for inspection of electrical characteristics of all LSIs.

[0106]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) According to the present invention, the semiconductor inspection circuit is transferred from the semiconductor chip to be inspected to the LSI chip of the semiconductor inspection apparatus, so that the semiconductor chip to be inspected can be downsized. (2) According to the present invention, electrical contact between the probe and the electrode pad of the semiconductor chip to be inspected or the semiconductor wafer to be inspected can be satisfactorily performed by the pressure due to the deformation of the beam on which the probe is formed. It is not necessary to provide a pressurizing mechanism such as air pressure on the beam itself. (3) According to the present invention, since the LSI chip constituting the contactor of the probe card and the Si substrate including the probe are manufactured separately, the LSI chip is contaminated by the KOH aqueous solution used in manufacturing the Si substrate. Can be prevented. (4) According to the present invention, the LSI chip constituting the contactor of the probe card, the Si substrate including the probe, and the Si tray are individually manufactured, so that the LSI chip is formed as compared with the case where the contactor is formed integrally. , S
The manufacturing process of each of the i-substrate and the Si tray can be simplified. (5) According to the present invention, the LSI chip constituting the contactor of the probe card, the Si substrate including the probe and the Si tray are individually manufactured, and the type of the semiconductor wafer to be inspected or the semiconductor chip to be inspected and the semiconductor wafer to be inspected Alternatively, since various semiconductor inspection circuits are formed on the LSI chip in accordance with the type of inspection to be performed on the semiconductor chip to be inspected, a probe card is manufactured corresponding to various semiconductor wafers or semiconductor chips to be inspected. be able to. (6) According to the present invention, the LSI chip constituting the contactor of the probe card, the Si substrate including the probe, and the Si tray can be individually replaced as necessary, so that the LSI chip can be replaced with another semiconductor. By replacing the LSI chip with an inspection circuit with another LSI chip, inspection of other electrical characteristics of the semiconductor wafer to be inspected or the semiconductor chip to be inspected can be performed. (7) According to the present invention, the LSI chip constituting the contactor of the probe card, the Si substrate including the probe, and the Si tray can be individually replaced as necessary, so that maintenance of the probe card is facilitated. It is possible to do. (8) According to the present invention, the LSI chip constituting the contactor of the probe card, the Si substrate including the probe, and the Si tray can be individually replaced as needed, so that the probe card manufactured in the past can be replaced. Also S
A new function can be added to the probe card by individually replacing the i-substrate, the LSI chip, and the Si tray. That is, the probe card manufactured in the past can be reused. (9) According to the present invention, since the probe card can be manufactured in correspondence with various kinds of semiconductor wafers or semiconductor chips to be inspected, the application range of the inspection performed by the probe card can be expanded. (10) According to the present invention, the manufacturing process of each of the LSI chip, the probe-containing Si substrate, and the Si tray constituting the contactor of the probe card can be simplified, so that the manufacturing cost of the contactor can be reduced. . (11) According to the present invention, since the contactor of the probe card is formed of the same material as the semiconductor wafer or the semiconductor chip to be inspected, the semiconductor wafer to be inspected or the burn-in inspection in a high-temperature atmosphere can be used. It is possible to prevent the probe from being distorted due to the difference in thermal expansion between the semiconductor chip to be inspected and the contactor and preventing the probe from being bent due to thermal expansion. (12) According to the present invention, in a probing inspection or a burn-in inspection in a high-temperature atmosphere, a probe may be distorted due to a difference in thermal expansion between a semiconductor wafer or a semiconductor chip to be inspected and a contactor of a probe card.
Since the probe can be prevented from bending due to thermal expansion, it is possible to prevent a contact failure between the probe and the semiconductor wafer or the semiconductor chip to be inspected.

[Brief description of the drawings]

FIG. 1 is a block diagram of an ASIC whose electrical characteristics are inspected according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part of a semiconductor inspection device according to an embodiment of the present invention;

3A is a cross-sectional view of a main part of a contactor included in the semiconductor inspection apparatus shown in FIG. 2, and FIG. 3B is a cross-sectional view of a main part in which the vicinity of a probe shown in FIG. It is.

FIG. 4 is a sectional view of a main part of a semiconductor inspection apparatus according to an embodiment of the present invention;

FIG. 5 is a sectional view of a main part of a semiconductor inspection apparatus according to an embodiment of the present invention;

FIG. 6 is a block diagram illustrating an example of a semiconductor inspection circuit incorporated in the semiconductor inspection device according to one embodiment of the present invention;

FIG. 7 is a block diagram illustrating an example of a semiconductor inspection circuit incorporated in the semiconductor inspection device according to one embodiment of the present invention;

FIG. 8 is a block diagram showing an example of a semiconductor inspection circuit incorporated in the semiconductor inspection device according to one embodiment of the present invention.

FIG. 9 is a block diagram illustrating an example of a semiconductor inspection circuit incorporated in the semiconductor inspection device according to one embodiment of the present invention;

FIG. 10 is a block diagram illustrating an example of a semiconductor inspection circuit incorporated in the semiconductor inspection device according to one embodiment of the present invention;

FIG. 11 is a block diagram showing an example of a semiconductor inspection circuit incorporated in the semiconductor inspection device according to one embodiment of the present invention.

FIG. 12 is an explanatory diagram showing a manufacturing flow of the semiconductor device according to one embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 ASIC 2 DRAM 3 Logic circuit 4 Semiconductor inspection circuit (first circuit) 5 DRAM bus 6 Tester bus 7 Contactor 8 Substrate 9 Connector pin 10 Holding plate 11 Reinforcement plate 12 Low elastic sheet 13 Low elastic adhesive 14 Screw 15 Probe 16 Si substrate (First substrate) 17 LSI chip (second substrate) 18 Si tray (third substrate) 19 wiring (first wiring) 20 bump electrode (first electrode) 21 positioning mechanism 22 taper mechanism 23 beam (first region) 24 Semiconductor wafer to be inspected 31 LSI chip 32 Si tray 33 Si substrate 34 Housing 35 Fixed pin with spring 36 Semiconductor chip to be inspected 37 Lock mechanism 38 Connector pin 39 Low elastic sheet 40 Low elastic adhesive 41 Positioning mechanism 42 Taper mechanism 43 Bump electrode 44 Bump electrode 45 Wiring 5 Si tray 53 Si substrate 54 Housing 55 Connector substrate 56 Metal wire 57 Semiconductor chip to be inspected 58 Low elasticity sheet 61 Positioning mechanism 62 Taper mechanism 63 Bump electrode 64 Wiring 71 Interface circuit 72 Pattern memory 73 Register 74 Computing unit 75 Sequencer 76 Output control Device 77 decision circuit 78 signal 79 data 80 data latch circuit 81 control CPU 82 test program storage ROM 91 clock generator 92 sequence controller 93 address generator 94 microprogram memory 95 data generator 96 rate 97 control signal pattern 98 data pattern 99 address pattern 101 test clock generator 102 pattern program memory 103 program counter 104 address counter Reference Signs List 105 data generator (determiner) 111 test clock generator 112 loop counter 113 program counter 114 pattern program ROM 115 address counter 116 data generator (determiner) 117 base register 118 switch 121 multi-pin unit 122 flip-flop 123 address decoder P1 to P5 process

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuo Takamura 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. No. 20-1 F term in Hitachi Semiconductor Group, Ltd. (Reference) 2G003 AA10 AC01 AD01 AG04 AG12 AH04 AH05 2G011 AA17 AA21 AC11 AC14 AE03 AF07 2G032 AA01 AB02 AC04 AF01 AF10 AG05 AK11 4M106 AA01 AA02 CA13 CA56 DD09 DD10 DD11 DJ33

Claims (5)

[Claims] 1. A second substrate having a first substrate formed of silicon and a first circuit for inspecting electrical characteristics of a semiconductor wafer or a semiconductor chip on which a semiconductor element, wiring and electrode pads are formed on a main surface. And a third substrate that determines a bonding position between the first substrate and the second substrate. A probe is formed in a first region provided at one or more locations on the first substrate, and a surface of the probe is provided. A first wiring electrically connected to the first circuit is formed on a surface or inside of the first substrate, and the first substrate and the second substrate are connected to the first substrate or the second substrate. A semiconductor inspection device characterized by being electrically and mechanically connected by a first electrode formed thereon. 2. A second substrate having a first substrate formed of silicon and a first circuit for inspecting electrical characteristics of a semiconductor wafer or a semiconductor chip having a semiconductor element, wiring and electrode pads formed on a main surface. And a third substrate that determines a bonding position between the first substrate and the second substrate. A probe is formed in a first region provided at one or more locations on the first substrate, and a surface of the probe is provided. A first wiring electrically connected to the first circuit is formed on a surface or inside of the first substrate, and the first substrate and the second substrate are connected to the first substrate or the second substrate. A semiconductor inspection device electrically and mechanically connected by a first electrode formed thereon, wherein the first substrate, the second substrate, and the third substrate are each formed by a separate process, The first electrode and adhesive A semiconductor inspection apparatus characterized by being joined by: 3. A second substrate having a first substrate formed of silicon and a first circuit for inspecting electrical characteristics of a semiconductor wafer or a semiconductor chip on which a semiconductor element, wiring and electrode pads are formed on a main surface. And a third substrate that determines a bonding position between the first substrate and the second substrate. A probe is formed in a first region provided at one or more locations on the first substrate, and a surface of the probe is provided. A first wiring electrically connected to the first circuit is formed on a surface or inside of the first substrate, and the first substrate and the second substrate are connected to the first substrate or the second substrate. A semiconductor inspection device electrically and mechanically connected by a first electrode formed thereon, wherein the first substrate, the second substrate, and the third substrate are each formed by a separate process, The first electrode and adhesive And the first circuit is
A semiconductor inspection apparatus characterized in that an inspection pattern is created by generating a pseudorandom number for inspection, and an inspection is executed by performing data compression. 4. The electrical characteristics of a first substrate formed of silicon and provided with a first region including a probe, and a semiconductor wafer or a semiconductor chip having a semiconductor element, wiring and electrode pads formed on a main surface. A method for manufacturing a semiconductor device, comprising: an inspection process using a semiconductor inspection device having a second substrate having a first circuit to be inspected and a first wiring for electrically connecting the probe and the first circuit. ,
(A) a step of preparing the semiconductor wafer or the semiconductor chip, (b) the probe and the electrode pad,
(C) transmitting and receiving an electric signal between the electrode pad and the first circuit, and (d) transmitting and receiving an electric signal between the electrode pad and the first circuit. Inspecting the electrical characteristics of the semiconductor chip. 5. A first substrate formed of silicon and provided with a plurality of first regions including probes, and a semiconductor wafer or a plurality of semiconductors on a main surface of which a semiconductor element, wiring, and a plurality of electrode pads are formed. A semiconductor device including an inspection process using a semiconductor inspection device having a second substrate having a first circuit for inspecting an electrical characteristic of a chip and a first wiring for electrically connecting the probe and the first circuit. (A) a step of preparing the semiconductor wafer or the semiconductor chip; and (b) simultaneously electrically connecting the plurality of probes and the plurality of electrode pads by pressure due to deformation of the first region. (C) transmitting and receiving an electric signal between the electrode pad and the first circuit, and (d) the semiconductor wafer or the semiconductor chip by the first circuit. Inspecting the electrical characteristics of the semiconductor device.