JP2002057945A - Variable gain cmos analog front end architecture for digital camera and camcorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog front end circuit that can be in operation in a CCD mode and a video mode. SOLUTION: This invention discloses an image processing unit for a charge coupled device(CCD) for a digital camera or a digital camcorder applying optical black and offset correction to a CCD input and an image processing unit for a video input. A sampling circuit including a correlation double sampling(CDS) 402 and a programmable gain amplifier (450) samples an image input signal and a video input signal. The CDS (402) includes a signal ended type amplifier (404) and a differential amplifier (406). The single ended type amplifier (404) is operated only for a CCD signal input period, and only the differential amplifier (406) samples the video signal by bypassing the single ended type amplifier (404) for other periods.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention provides image processing, more specifically, digital optical black and offset correction for CCD inputs, and uses the same channel for both CCD and video signal inputs. It relates to an analog front-end circuit that can be used.

[0002]

BACKGROUND OF THE INVENTION Advances in the design and manufacture of integrated circuits have allowed low cost, highly integrated, high performance image processing products, including digital electronic cameras and camcorders. A typical camera includes an image sensor, typically an array of charge coupled devices (CCD),
It has an analog front end (AFE) and a digital image processor. A CCD is a two-dimensional array of sensors where each sensor generates a charge as a function of the amount of photons it has absorbed. After the CCD is exposed to the image, the pixels are shifted vertically to a line charge register, which shifts the pixels horizontally to the output. Most CCDs have on-chip amplifiers,
This is usually a source follower, which converts the charge into a voltage output. Most analog front-end circuits with optical black and offset calibration integrate the error signal into a capacitor during the optical black period and feed back the generated voltage to the input during the image period to provide an offset or offset. It has a method of canceling out optical black values. As is known, an analog image signal from an image processing device is subjected to a feedback clamp circuit to generate a video signal before being processed in various ways including, for example, linear masking, gamma correction and knee correction. Can be supplied. Applicant's pending application shown in FIG. 1, serial number 09 / 353,919, provides a CCD signal processing method that performs optical black offset correction using a moving average filter scheme. The target black pixels are averaged at the beginning of each line, and offset DACs 114 and 116 are updated to offset the offset. Specifically, this embodiment is a digital scheme that corrects offset and optical black values in the analog domain using coarse and fine adjustment modes. Digital optical black correction circuit 100 determines the amount needed to adjust the analog image signal. DACs 114 and 116 generate offsets in coarse and fine adjustment modes, respectively. This highly programmable design 100 can be used in both discrete and continuous time schemes, and does not require any off-chip components.

[0003] Analog front end (AFE) 10
A 0 converts the output signal of the CCD (not shown) to digital data so that subsequent digital signal processing can be performed. At the input of AFE 100, CC
The DC level of the D output signal is clamped to the input dynamic range. For better noise performance and dynamic range, correlated double sampling is applied to the clamped input signal. Correlated double sampler (CDS)
The output of 102 is amplified by a programmable gain amplifier 106 that varies exponentially with linear control. Thereafter, the amplified analog signal is converted to digital data. Optical black values and channel offsets are corrected to maximize the dynamic range. In operation, the CCD image line is shifted vertically into the line register, and then the pixels on this line are shifted horizontally to the output pins. This embodiment cancels out the optical black level received by the image signal.
However, line noise may be present in the optical black correction. Even when the correction DAC updates are averaged across a fixed number of user-programmable lines, there may be noticeable bands in the image. In addition, this average varies from line to line because certain optical black pixels may be bad, i.e., hot and cold optical black pixels. A hot pixel is a defective pixel that generates too much charge, and a cold pixel is a pixel that does not generate any charge. Pending application 60/15 shown in FIGS.
2,439 is a CCD that eliminates this line noise with hot and cold pixels without banding in the image.
A moving average filter method for optical black correction is disclosed. It has a direct moving average filter, including a simplified version, which can be used to save a considerable amount of registers and complex digital circuits. However, this design is still frustrated in that it only operates to receive image signals in CCD mode. However, in many applications, there is a need to process video input signals with the ability to process CCD signals. Therefore, there is a need to operate in both CCD mode and video mode.

[0004]

SUMMARY OF THE INVENTION In order to address the above-mentioned drawbacks of the moving average filter scheme for optical black correction of a CCD, the present invention provides two modes of operation: CC mode.
An analog front-end circuit having a first mode for a D image signal and a second mode for a video image signal is taught. The analog front-end circuit includes a sampling circuit and an analog-to-digital converter, but is operable to sample and amplify the analog image signal and convert it to a digital image signal. A sampling circuit is coupled to the programmable gain amplifier (PGA) and uses a correlated double sampler composed of a single-ended amplifier and a differential amplifier to produce a CCD.
The input signal or the video input signal is sampled. single·
The ended amplifier operates so as to be operable only during the CCD signal input. Otherwise, single
Ended amplifiers are bypassed and the video signal is sampled only by the differential amplifier. A single-ended amplifier samples the reference level of the pixel and holds it during the video period. The differential amplifier is
Both the output of the single-ended amplifier and the video level of the same pixel are sampled. Overall, CDS
Subtracts these levels and converts the difference to a difference output to improve signal to noise performance and dynamic range.
An analog-to-digital converter converts the sampled signal and provides the digital samples to a digital correction circuit, which corrects the optical black level,
Removes hot and cold pixels and line noise. Nevertheless, a digital error correction circuit is connected to the analog front-end circuit to remove the optical black pixel level from the image signal, and the sum of the channel offset and the optical black level is reduced to a predetermined number of lines and optical per line. The channel is digitally calibrated to obtain the ADC output as programmed by the user corresponding to the average. In a second embodiment, the error correction circuit removes hot and cold pixels and filters out line noise. In addition, a digital filter is used to achieve noiseless optical black correction with a digitally programmable bandwidth. The advantages of this design include, but are not limited to, C
An image processing apparatus that can operate in a CD mode and a video mode. This circuit has an improved dynamic range for image processing compared to other schemes. For that reason,
This highly programmable design can be used for both discrete and continuous time schemes and does not require any off-chip components. Thus, this design meets the goal of extracting the largest possible analog dynamic range from the image sensor without adding any noise in subsequent circuitry. For a more complete understanding of the invention and its advantages, reference is now made to the accompanying drawings. Like reference numerals in the drawings represent like parts.

[0005]

DETAILED DESCRIPTION OF THE INVENTION In the present invention, the image processing apparatus shown in FIGS. 2-5 allows the use of the same channel for both CCD and video signal inputs to provide noiseless optical black and offset correction. Can be achieved.
Accordingly, the invention will be described with reference to all of FIGS. FIG. 2 shows an image processing apparatus or an analog front end (AF) including a sampling circuit for sampling an incoming image signal.
E) Circuit 200 is shown. The sampling circuit is a correlated double sampler (CDS) 202, a programmable gain amplifier (PG).
A) 206 and analog-to-digital converter (ADC)
210. Detection circuit 212 detects the optical black level. In addition, the detection circuit 212 includes a first filter for filtering out hot and cold pixels before averaging the optical black pixels. Calibration logic 214
Include the circuit 300 shown in FIG. Circuit 300 includes a digital averager 302 that averages the optical black pixel at the beginning of each line of the image signal. A line noise filter constructed using elements 304-316 receives the averaged optical black signal and further removes line noise from the optical black signal. Digital comparator 318 receives the reference signal and the optical black signal and compares the optical black signal with the reference signal. The difference is received by the calibration logic 214 and the digital comparator 318 feeds back the determined difference to correct the optical black level, which is used by the DAC 22 to compensate for the difference.
8 and 230 to be applied to the analog image signal. DACs 228 and 230 make coarse and fine adjustments, respectively, to the analog image signal.

FIG. 4 shows a portion 400 of an analog front end (AFE) with optical black and offset correction, wherein the analog front end (AFE) comprises:
The CCD output signal is converted into digital data so that digital signal processing can be performed thereafter. FIG.
The form shown in FIG. 1 illustrates the CCD mode of the image processing apparatus according to the present invention. As shown, AFE input 401
The DC level of the CCD output signal is
Is clamped to the input dynamic range.
To further improve noise performance and dynamic range, a correlated double sampler (CDS) 402 applies correlated double sampling to the clamped input signal. CDS
The output of 402 is amplified by a programmable gain amplifier (PGA) 450 that varies in an exponential fashion with linear control. Analog-to-digital converter (ADC) 2
10 converts the analog signal to digital data.
As mentioned earlier, the optical black values and channel offsets are corrected to maximize the dynamic range. During the CCD mode, two clock signals (SR
1, SV 1) is used for CDS 402 and 1
The two clock signals (CLK) are ADC 210 and PG
Used for A450 timing. As can be seen from the time diagram shown in FIG. 6, during the δ ₁ period, the single-ended amplifier 404 samples the CCD reference signal. During the δ ₂ period, the differential amplifier 406 samples the video signal and the output from the single-ended amplifier 404. Finally, during the δ ₃ period, CDS 402 subtracts these levels and converts them to a difference output to improve signal to noise performance and dynamic range. PGA
450 samples the output of the differential amplifier 406. CCD
The DC level at input 401 is typically CDS 402
Is larger than 8V, which exceeds the input dynamic range of
It is capacitively coupled to DS 402. The CCD input 401
It is also clamped to set the correct DC level. As previously mentioned, the output of CDS 402 is amplified by a programmable gain amplifier 450 that varies exponentially with linear control. The PGA disclosed in pending application serial number 09 / 354,461, which is incorporated herein by reference, is suitable for this configuration. The disclosed PGA uses only CMOS components to achieve an exponential gain characteristic using a linear control signal. The exponential function gain characteristic is approximately configured using a function of G (X) = (1 + X) / (1-X). Another embodiment uses a known switching scheme, uses fewer components, and reduces the bandwidth requirements on the operational amplifier, G (X) = 1 + 2
^* X / (1-X) is realized. By using unit capacitors to achieve these functions, gain control relies heavily on capacitor balance. With appropriate capacitor types, both positive and negative gain (attenuation) functions are feasible. By using a capacitor, the arrangement is small, and due to its inherent holding function,
It makes it easier to "pipeline" several stages with a larger overall gain range without the demanding performance requirements of an operational amplifier.

The PGA 450 of one embodiment has an exponential gain change of 0 to 36 dB, which is 1 to 6 dB.
4 corresponds to a gain within the range of 4. CDS 402 has a gain of 0 or 6 dB, and each of the two coarse gain stages (not shown) within PGA 450 has 0, 6, 12
It has a gain of dB. The fine gain stage has a gain of 0 to 6 dB in 64 steps in 0.09 dB increments. Because of this,
There are 6 ranges of 64 steps each, and a total of 384 steps
The gain range is 36 dB. All three stages in PGA 450 are switching capacitor stages. In order to realize the exponential gain change of the fine gain stage, an approximation of In ((a + x) / (ax)) = 〜2x / a│x│ <a (1) is used. Where x is a linear gain control code and a is a constant that determines the number of gain stages. The switching capacitor stage implements the gain (a + x) / (ax). Since (a + x) = (ax) + 2x, the feedback capacitor that also samples the input is (ax)
And the sampling capacitor is 2 ×. Each of the pipeline ADCs 210 is a 4-bit flash AD.
It has three stages with C (not shown). Comparator 3
Use digital error correction so that the required precision of 18 is 4 bits instead of 10. The choice of the step resolution is based on power consumption considerations. The main power consumption in ADC 210 is due to the operational amplifier. It is preferable to use as few operational amplifiers as possible. However, the more bits per stage, the higher the gain of the residue amplifier, and therefore the more operational amplifiers that require higher open loop gain and bandwidth. In a 4-bit architecture per stage,
2 with 90 dB gain and 800 MHz bandwidth
Uses a stage operational amplifier. Typical power consumption of an ADC is 40 mW at 30 M samples and 3 V.

[0008] As is known, a CCD sensor (not shown in the figure) can be used even when it is not exposed to any light.
Generate output. This output is the optical black level (OBL)
Also known by the name. To increase the dynamic range, OBL and channel offset are canceled in the analog domain. The black pixels are averaged at the beginning of each line, and two DAs, one before and after the PGA 450
Update C 230 and 228 to achieve the desired light level. However, the optical black level for each line can be noisy, which can cause line noise in the image. A digital scheme utilizing programmable filter parameters is used to eliminate high frequency optical black level noise and still compensate for slowly changing offsets. Moving average filter 30
2 is approximated using a simplified function Y (n) = w ^* X (n) + (1-w) ^* Y (n-1) (2) requiring only a small number of registers. Where Y (n) is the new DAC value, X (n) is the error signal (the difference between the desired optical black level value and the actual OBL value when the correction DAC is set to zero), Y (N-1) is the value of the previous DAC and w is a user programmable weight. If w is 1, the correction is fast, but the high-frequency line noise is not removed by the filtering action. Smaller w results in slower correction, but the line noise is filtered out. The cutoff frequency of the optical black level low-pass filter can be digitally programmed according to the response time of the correction and the high frequency components due to bad optical black pixels and CCD noise. AFE can be manufactured by a 0.6 μ CMOS process. The measurement results are shown in the table below.

FIGS. 9 and 10 show the measured INL and DNL of the entire channel. DNL is defined as the difference between the "width" of the analog input range of each signal and the ideal range. INL is the analog transfer from the ideal transfer function.
The deviation of the actual transfer function of the front end. FIG.
Indicates the gain measured for the digital gain code. It will be appreciated that the gain control is very linear on an exponential scale, and thus the approximation of equation (1) has been verified. CDS-AMP2 406 during video mode
To sample the input signal. CDS 402
And that the remaining channels use the same clock signal (CLK). Different pins are used for video and CCD inputs. The multiplexer for the CCD and video inputs is the CDS-AMP shown in FIG.
2 406 sampling switches. FIG.
As shown in a period [delta] _4, the video signal input is sampled. This video signal is capacitively coupled to the input. Use the automatic clamp or manual clamp to set the correct DC level 8
06 can be set. As shown in FIG. 8, the model for the automatic clamp 800 has an intentional leakage current 8
08 is an ideal diode 804. But,
The automatic clamp 800 is clamped to the most negative point of the video signal. By the negative spike of the video input,
If the clamp becomes inaccurate, the leakage current will reduce the DC level. The single-ended amplifier 404 is effectively bypassed and only serves to maintain the pixel's reference level during this video period. During the period [delta] _5, PGA
450 samples the output of the differential amplifier 406. Although the clamp voltage is fixed, any DC offset can be corrected using the correction DACs 228 and 230 used for optical black correction in the CCD mode. These DACs 228 and 230 also allow the minimum digital output of ADC 210 to be programmed on the back porch instead of the sync tip. Thus, the dynamic range for the video input can be significantly improved to 1/5 or 1/4 of the entire range.
However, for automatic gain calculation, it is necessary to sense and digitize the difference between the synchronization tip and the back porch. This value can be sensed by intentionally using a constant analog offset during the sync tip period.
This analog offset is stored in offset register 2
22 and 223.

The advantages of the image processing apparatus include, but are not limited to, an image processing circuit that receives a CCD and video input and is operable in a CCD mode and a video mode. This circuit has an improved dynamic range for image processing compared to other schemes. Thus, this highly programmable design can be used for both discrete and continuous time schemes, and does not require any off-chip components. Thus, this design satisfies the goal of extracting the largest possible analog dynamic range from the image sensor without adding noise in subsequent circuits. The present invention includes a variety of industrial, medical and military sensors and imaging applications, including digital still cameras, digital video cameras, digital video processing systems, CCD signal processors and CMOS imagers. And is used in a wide variety of video systems. The present invention provides significant advantages over conventional architectures, including digital programming capabilities, fine resolution, and compatibility for both continuous-time and discrete-time programmable gain amplifiers. Readers of this specification should refer to all documents that are filed concurrently with this specification and that are publicly available with this specification. The contents of all of these documents are incorporated herein by reference. All features described in this specification (including all claims, abstracts and drawings)
Can be replaced by alternative features serving the same, equivalent or similar purpose, unless otherwise noted. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. The terms and expressions used in this specification are used as words of description and do not limit the present invention. The use of such terms and expressions is shown in the drawings and described herein. It is to be understood that no equivalents or portions thereof are intended to be excluded and the scope of the invention is to be determined solely by the appended claims.

[0011]

[Relationship with Related Application] This invention was filed on July 15, 1999.
Serial No. 09 / 353,919 filed on Jan. 15, 2004, titled "Optical Black and Offset Correction in CCD Signal Processing", serial No. 0 filed on Jul. 15, 1999.
9 / 354,461, entitled "Capacitor-Based Exponential Function Programmable Gain Amplifier", and 199
Application No. 60 / 152,43 filed on Sep. 3, 9
9. Regarding a pending application entitled "Digital System for Noise Filtering of Optical Black and Offset Correction in CCD Processing", these applications are hereby incorporated by reference. Put in. This application is based on 35 USC §119 (e) (1)
Provisional application number 60/15 filed on September 3, 999
Claim 2,436 priorities.

[Brief description of the drawings]

FIG. 1 is a block diagram of an optical black offset correction device disclosed in pending application Ser. No. 09 / 353,919.

FIG. 2 illustrates an architecture for performing optical black and offset calibration and removing noise according to the present invention.

FIG. 3 illustrates calibration logic for performing optical black and offset calibration and removing noise in accordance with the present invention.

FIG. 4 shows an imaging device operable in a CCD mode according to the present invention.

FIG. 5 shows an imaging device operable in a video mode according to the present invention.

FIG. 6 is a time diagram of signals of an image device operable in a CCD mode according to the present invention.

FIG. 7 is a time diagram of signals of an imaging device operable in a video mode according to the present invention.

FIG. 8 is a block diagram of an automatic clamp.

FIG. 9 is a graph showing the integral non-linearity (INL) of the entire channel of the imaging device according to the present invention.

FIG. 10 is a graph showing the differential nonlinearity (DNL) of the entire channel of the imaging device according to the present invention.

FIG. 11 is a graph showing measured gain for a digital gain code.

[Explanation of symbols]

 402 Correlated double sampler (CDS) 404 Single-ended amplifier 406 Differential amplifier 450 Programmable gain amplifier

Continued on the front page (72) Inventor Gary E., Lee United States of America Texas, St. Robinson, Woodcock Drive 1202 (72) Inventor Ramesh Chandrasekalan United States of America Texas, Dallas, MacCallum Boulevard 7835, apartment number 1301 (72) ) Inventor Fen Yin United States Texas, Plano, Spring Valley Lane 8213 (72) Inventor Chin-Utsui United States Texas, Plano, Portrate Train 4613 (72) Inventor Schenwan United States Texas, Plano , Medium drive 4308 F term (reference) 5B047 AB02 BB04 BB06 DA01 DA06 DB04 DC01 5C024 CX31 GY01 GY31 HX13 HX18 JX00 5C077 LL19 MM03 MP01 PP07 PP11 PP12 PP42 PP45 PQ03 RR01 RR02

Claims (10)

[Claims] 1. An image processor having offset and optical black correction coupled to receive an image input signal from a charge coupled device and a video input signal from a video device. A sampling circuit for sampling the CCD and video input signals; an analog-to-digital converter coupled to the sampling circuit for converting the sampled signal to a digital signal; A digital correction circuit for correcting an optical black level by feeding back a difference between the reference level and a black reference level so that the difference is added to or subtracted from an analog image and a video input signal. Is coupled to receive a sampled signal from the correlated double sampler and amplify the sampled signal. A correlated double sampler including a single-ended amplifier and a differential amplifier coupled to the single-ended amplifier, wherein the single-ended amplifier is an imager in CCD mode. An image processing apparatus operable to pass an input signal and configured to bypass a single-ended amplifier in a video mode so that the video input signal is sampled only by a differential amplifier. . 2. The image processing apparatus according to claim 1, wherein
An image processing apparatus wherein the programmable gain amplifier has an exponential function gain characteristic represented by the following function G (x) = 1 + 2x / (1-x). 3. The image processing apparatus according to claim 2, wherein
The image processing apparatus further comprising the sampling circuit including a register coupled to the programmable gain amplifier for customizing the gain value. 4. The image processing apparatus according to claim 1, wherein
An image processing device, wherein the digital averaging includes a first filter for removing hot and cold pixels from the image signal. 5. The image processing apparatus according to claim 1, wherein
The line noise filter applies the following function to the image signal: Y (n) = α ^* X (n) + (1−α) ^* Y (n−1), where Y (n) is digital The new value of the analog converter, where X (n) is the desired value at the output of the analog-to-digital converter and the actual optical black level if the digital-to-analog converter for correction is zero An image processing device wherein Y (n-1) is the previous value of the digital-to-analog converter and α is a user programmable weight. 6. The image processing apparatus according to claim 1, wherein
An image processing apparatus, wherein the correction circuit includes a first digital-to-analog converter coupled to an adder for applying the difference to an analog image signal. 7. The image processing apparatus according to claim 6, wherein
Further, the correction circuit includes a second digital-to-analog converter coupled to the sampling circuit to apply the difference to the amplified analog image signal, wherein fine adjustments are made to the amplified analog image signal. The first digital-to-analog converter is enabled in a coarse mode in which the analog image signal is coarsely adjusted before the second digital-to-analog converter is enabled in a fine mode. Image processing device. 8. The image processing apparatus according to claim 7, wherein:
An image processing apparatus, wherein the correction circuit further includes first and second offset registers coupled to first and second digital-to-analog converters for customizing an offset value for the image signal. 9. An image signal is obtained by photoelectrically converting a signal of light reflected from an object, a predetermined reference voltage is generated, and the image signal is clamped to the predetermined reference voltage. Amplifying a signal using a plurality of differential amplifiers following a single-ended amplifier, and amplifying the signal using the plurality of differential amplifiers when in a video mode; The black pixels are filtered out and the optical black level of the clamped image signal is detected. The line noise is filtered out and the difference between the detected optical black level and the expected optical black level is determined. Generated by switching between coarse mode and fine mode, applying coarse and fine adjustments respectively, and feeding back the difference to the clamped image signal to produce an optical black level. An image processing method comprising the step of correcting. 10. The image processing method according to claim 9, wherein the step of removing the line noise by a filtering action comprises:
Apply the following function to the image signal: Y (n) = α ^* X (n) + (1−α) ^* Y (n−1), where Y (n) is the new digital-to-analog converter X (n) is the difference between the desired value at the output of the analog-to-digital converter and the actual optical black level if the digital-to-analog converter for correction is zero. Yes, where Y (n-1) is the previous value of the digital-to-analog converter and α is a user programmable weight.