JP2002057198A - Method for producing semiconductor device and semiconductor producing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain improvement in the specification accuracy and analysis throughput of a defective spot in the defect analysis of a semiconductor chip. SOLUTION: A substrate 4 for detection is prepared while providing the matrix array of plural detecting elements 3 capable of amplifying a current by detecting light, heat and infrared rays generated from the defective spot of the semiconductor chip and after the semiconductor wafer of an examination target having the semiconductor chip is located on the substrate 4 for detection, the probe examination of the semiconductor chip is performed. In this probe examination, the current inside the detecting element 3 is amplified and latched up by detecting the medium such as light, heat or infrared rays generated from the defect spot by means of the detecting element and corresponding to the positions of the detecting elements 3 in the matrix array recognized by this latch-up, the position of the defective spot on the semiconductor chip is detected as coordinates so that the specification accuracy of the defective spot can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly, to a technique which is effective when applied to the improvement of the accuracy and processing capacity of failure analysis of LSI (Large Scale Integration).

[0002]

2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

[0003] In the semiconductor manufacturing process, when analyzing a defect such as a short circuit generated randomly in an LSI,
First, the position of the defective part must be accurately specified. Further, when the defective portion is successfully specified, FIB (Focused Ion Beam) processing or polishing analysis is performed on the specified portion to directly observe the appearance of the defective portion.

After that, the result of analysis of the defect is fed back to the person in charge of the process design in the preceding process, and a countermeasure against the defect is taken.

[0005] Therefore, it is of the utmost importance in the failure analysis to accurately narrow down the position of the defective portion.

[0006] Typical analysis methods used for identifying the defective portion include: 1. a heat generation analysis method for detecting infrared rays from a short-circuit portion, 2. an emission analysis method for detecting light emission due to hot electrons, and 3. a liquid crystal. There are a liquid crystal method to detect the phase transformation of the, and an analysis method to detect the change of the wiring resistance due to the laser irradiation. At the time of analysis, these methods are used depending on the phenomenon of the defective part.

The LSI failure analysis apparatus and analysis method are described in, for example, JP-A-7-14898.

[0008]

However, in the analysis method of the above-described technique, the accuracy of the specific processing and the efficiency of the specific processing are reduced.
There are the following problems.

1. In the case of a short-circuit failure, when the wiring is short-circuited, an electric field is concentrated on the short-circuited portion, whereby heat is generated according to the short-circuit resistance value, the temperature of the short-circuited portion is increased, and infrared rays according to the temperature are transferred to the LSI. Radiates out.

In the heat generation analysis method, infrared rays generated at this time are detected, but heat generated at the same time cannot be detected. In the liquid crystal method, heat is detected, but infrared light cannot be detected. Further, the method of detecting a change in the wiring resistance has a problem that a wiring formed below a wide wiring cannot be evaluated.

2. In a leak failure, when the element leaks, holes / electrons are separated by the generation of hot electrons, and the energy excited when returning to the ground state by combining again is emitted as light. Further, the leak element at this time is heated by the leaking current as compared with the normal element, and as a result, emits infrared rays.

In the light emission analysis method, light generated at this time is detected, but heat and infrared rays cannot be detected.

That is, a method such as a heat generation analysis method, a liquid crystal method, or an analysis method for detecting a change in wiring resistance detects only one of various media generated from a defective portion and cannot detect other media. If the noise at the normal part becomes large (or the amount of medium generated from the defective part is small), it becomes difficult to distinguish between abnormal and normal, and as a result, there is a problem that the position of the defective part cannot be specified.

An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor manufacturing apparatus for improving the accuracy of specifying a defective portion and improving the analysis processing capability in a defect analysis.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the method of manufacturing a semiconductor device of the present invention, a detection substrate provided with a plurality of detection elements capable of detecting current and amplifying light by detecting light and heat generated from a defective portion of a semiconductor chip is provided. Arranging the semiconductor chip or a semiconductor wafer having the same on a detection substrate,
Electrically inspecting the semiconductor chip, wherein the light and the heat generated from the defective portion in the inspection are detected by the detection element to amplify a current in the detection element, The position of the defective portion of the semiconductor chip is detected in accordance with the position of the detection element recognized by the method.

Further, according to the method of manufacturing a semiconductor device of the present invention, there is provided a detection substrate provided with a plurality of detection elements capable of detecting light, heat and infrared rays generated from a defective portion of a semiconductor chip and amplifying the current, in a matrix arrangement. Preparing, the step of arranging the semiconductor chip or a semiconductor wafer having the same on the detection substrate, and a step of performing a probe inspection of the semiconductor chip, the light generated from the defective portion in the inspection, The heat and the infrared rays are detected by the detection element, the current in the detection element is amplified and latched up, and the semiconductor chip of the semiconductor chip is associated with the position of the detection element in the matrix arrangement recognized by the latchup. The position of the defective portion is detected as coordinates.

According to the present invention, it is possible to simultaneously detect light, heat and infrared rays generated from a defective portion of a semiconductor chip. Therefore, the detection elements are arranged in a matrix arrangement in the vicinity of a semiconductor chip or a semiconductor wafer having the same. And an electrical inspection of the semiconductor chip, light, heat and infrared rays from a defective portion of the semiconductor chip can be detected, and the detection result can be represented as coordinates.

As a result, the accuracy of specifying a defective portion can be improved.

Further, the semiconductor manufacturing apparatus of the present invention is provided with a plurality of detecting elements capable of detecting current and amplifying light by detecting light and heat generated from a defective portion of the semiconductor chip, and the semiconductor chip or the semiconductor wafer having the same. A detection substrate capable of supporting the semiconductor chip, the light and the heat generated from the defective portion of the semiconductor chip are detected by the detection element to amplify the current in the detection element, and the current is amplified by the current amplification. The position of the defective portion of the semiconductor chip can be detected corresponding to the position of the detection element.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a diagram showing an example of the principle of detection of a detection element provided on a detection substrate used in a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein (a) is a schematic circuit diagram,
2B is an equivalent circuit diagram of FIG. 2A, FIG. 2C is a latch-up flow diagram, FIG. 2 is a conceptual diagram showing an example of an internal configuration of the detection device shown in FIG. 1, and FIG. 3 is a detection device shown in FIG. FIG. 4 is a conceptual diagram showing an example of a circuit configuration of a detection substrate provided with a plurality of substrates in a matrix arrangement, and FIG. 4 is a P detection apparatus which is an example of a semiconductor manufacturing apparatus of the present embodiment using the detection substrate shown in FIG. FIG. 5 is a flow chart showing an example of a P-test procedure and a flow of a P-test analysis program in the method of manufacturing a semiconductor device according to the present embodiment using the P-test apparatus shown in FIG. 6, FIG. 6 is a conceptual diagram showing an example of a latch-up state of the detection element when performing P detection based on the P detection flow shown in FIG. 5, and FIG. 7 shows the P detection device of the present embodiment shown in FIG. An example of the detection sensitivity when a defective part is detected with the inspection device of the comparative example. A diagram showing a detection sensitivity of (a) the detection sensitivity of the P detection apparatus of this embodiment, (b) the inspection device of the comparative example.

The method of manufacturing a semiconductor device according to the present embodiment
For example, the semiconductor chip 1 may be a semiconductor chip 1 on which a CMOS (Metal Oxide Semiconductor) device is formed (the semiconductor chip 1 may be a single chip after dicing, or
In the semiconductor chip 1 formed on the semiconductor wafer 1g before dicing shown in FIG. 4, a defect such as a wiring short 1d or an element leak 1e occurring in the wiring 1b or the element 1c shown in FIG. 6 is detected. Lever position (defective part)
And the light emitted from the defective portion, heat, and infrared light among the three media 2 to detect at least light and heat to detect the position of the defective portion,
It is possible to specify a defective portion of a defective chip in a state where a pattern is applied to the integrated circuit of the semiconductor chip 1.

Here, the structure of the detection board 4 for detecting the position of a defective portion used in the failure analysis in the method of manufacturing a semiconductor device according to the present embodiment, the structure of the detecting element 3 provided thereon, and the inspection principle thereof Will be described.

First, the detection element 3 shown in FIGS.
Are capable or easy to cause a latch-up phenomenon or an equivalent phenomenon. The latch-up phenomenon is a phenomenon in which when a specific surge is applied from the outside in a CMOS device or the like, an overcurrent flows between the power supply and GND, and this state is maintained unless the power supply voltage is turned off once. , And exhibiting characteristics similar to those of the thyristor, it is also called the thyristor effect.

As shown in FIG. 1, the detecting element 3 includes, for example, a P-type impurity semiconductor 3a and an N-type impurity semiconductor 3.
PNP transistor 3c consisting of a PNP junction by b
And a NPN transistor 3d formed of an NPN junction are connected as shown in FIG.
A voltage of 1 V is applied to the VDD 3e side and a voltage of 0 V is applied to the VSS 3f side between e (power supply side) and VSS 3f (ground side).

In this state, as shown in FIG. 1A, a medium 2 such as heat / light / infrared is generated (step S1 shown in FIG. 1C), and the medium 2 irradiates the PNP transistor 3c. Then, a first current (current) 3g is generated between the PNP junctions, and the first current 3g increases (Step S).
2). At this time, as shown in FIG. 1B, the first resistor 3r
Is provided, the base potential (the first current 3g × the first resistor 3r) increases (step S3), and a part of the first current 3g becomes the first trigger current 3i and flows between the NPN junctions. Then, the NPN transistor 3d is turned on (step S4).

As a result, the second current (current) 3h increases between the NPN junctions (step S5). At this time, since the second resistor 3s is provided, the base potential of the PNP transistor 3c increases, and Part of the second current 3h becomes the second trigger current 3j and flows between the PNP junctions, and P
Turn on the NP transistor 3c (step S
6).

As a result, the first current 3g increases.

Therefore, if this process continues, VD
The current between D3e and VSS3f transiently increases, and this phenomenon is called a latch-up (step S7) phenomenon.

FIG. 2 shows the detecting element 3 having the characteristics shown in FIG. 1 and the hierarchical structure of the connection state. A PNPN junction is provided in the element forming region 3t, and each of them has a contact. The first wiring 3k is connected to the first wiring 3k by a hole 3m, and a high potential (VDD3e)
On the side, a second wiring 31 is formed via a through hole 3n, and a low potential (VSS3f) is formed under the second wiring 3l.
The first wiring 3k on the side is disposed.

As described above, since the medium 2 such as heat / light / infrared is transmitted to the PNPN junction of the element forming region 3t, an increase in current is obtained. Therefore, at the time of layout, the upper part of the PNPN junction is connected to the first wiring 3k or the like. It should not be covered by the second wiring 31 or the like.

Note that the detection sensitivity (easiness of latch-up) of the detection element 3 is controlled by the amount of impurity implantation when the detection element 3 is formed.

As described above, by using the detecting element 3 shown in FIGS. 1 and 2, heat / light / infrared rays can be detected simultaneously.

Next, the detection substrate 4 shown in FIG. 3 using the detection element 3 shown in FIGS. 1 and 2 will be described.

The detection substrate 4 has a structure in which a plurality of detection elements 3 are spread over a base substrate made of, for example, silicon. In the detection substrate 4 shown in FIG. 3, the plurality of detection elements 3 are arranged in a matrix. The detection elements 3 are connected in parallel between VDD 3e and VSS 3f.

Further, each of the lead-out wirings 3u of VSS3f and VDD3e (either DC or AC) has
Each of the ammeters 5 is connected. The ammeter 5 monitors (monitors) the current flowing through the detecting element 3 and assigns addresses so as to correspond to the coordinates (X coordinate 6 and Y coordinate 7) of the matrix. Have been.

That is, by arranging the detection elements 3 in a matrix, the detection elements 3 (FIG.
Can be immediately output as coordinates using the X coordinate 6 and the Y coordinate 7 (in FIG. 3, the detection element 3 shown in white is not latched up). Non-latch-up element 3q).

The installation pitch of the detection elements 3 is, for example, about 1 to 3 μm. However, since the detection elements 3 correspond to the resolution at the time of detecting a defective portion, they are preferably installed at the smallest possible pitch.

Next, a schematic configuration of a P detection apparatus 11 shown in FIG. 4, which is an example of a semiconductor manufacturing apparatus used in the present embodiment, will be described.

The P inspection apparatus 11 performs P inspection (probe inspection) of the semiconductor chip 1 and the like based on the P inspection flow shown in FIG. 5, and detects a position of a defective portion found during the inspection while the pattern is being applied. Here, a plurality of detecting elements 3 capable of detecting currents 2, such as light, heat, and infrared rays, generated from a defective portion of the semiconductor chip 1 and amplifying the current are provided. A detection substrate 4 capable of supporting the semiconductor wafer 1g to be inspected is provided, the medium 2 generated from the defective portion is detected by the detection element 3, and the current in the detection element 3 is amplified and latched up. The semiconductor chip 1 corresponding to the position of the detection element 3 recognized by current amplification (latch-up)
The position of the defective portion is detected.

Therefore, the P inspection device 11 performs a plurality of inspection probes 8 to be brought into contact with the surface electrodes of the semiconductor chip 1 at the time of the probe inspection, the probe inspection, and detects the position of the defective portion in a pattern applied state. An inspection unit 9 and a chuck 10 in which the detection substrate 4 is embedded and which supports the semiconductor wafer 1g to be P-detected are provided.

As a result, when a defect such as the wiring short 1d or the element leak 1e shown in FIG.
The coordinates of the defective portion can be specified by the detection substrate 4 while maintaining the voltage application condition.

It should be noted that the inspection probe 8 and the detection substrate 4 in the chuck 10 are interlocked, and therefore, during the P inspection, the inspection probe 8 and the detection substrate 4 Are in contact with each other.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described.

The method of manufacturing the semiconductor device is shown in FIG.
The P inspection and the failure analysis are performed using the P inspection device 11 shown in FIG.

The procedure of the P inspection will be described. First, a semiconductor wafer 1g to be inspected is placed on the chuck 10, and then the semiconductor wafer 1g is
Hold.

Thereafter, the inspection probe 8 is brought into contact with the front surface electrode (or the test electrode of the semiconductor wafer 1g) of the main surface 1a of the semiconductor chip 1 of the semiconductor wafer 1g to make the inspection probe 8 and the semiconductor chip 1 conductive. To perform a probe test.

In the probe inspection, as shown in FIG. 5, first, the contact check shown in step S11 is performed to check the continuity between the inspection probe 8 and the semiconductor chip 1.

Subsequently, a signal pin check shown in step S12 is performed to check whether the signal input is properly performed.

Further, the power supply short check shown in step S13 is performed to check whether or not the voltage application is properly performed.

Then, the leak current of the static circuit is detected by performing the IDDQ test shown in step S14.

Further, the FUNC test shown in step S15, the RAM test shown in step S16, etc. are performed, and the inspections in steps S11 to S16 are passed to be non-defective products shown in step S17.

Therefore, in the P inspection apparatus 11 of the present embodiment, for example, when a failure such as a wiring short 1d is found in the power short check in step S13, the P inspection program is immediately terminated after determining that the chip is defective. Then, the P detection analysis program is loaded (executed), and thereby, the short-circuited portion shown in step S18 which is a failure analysis is specified.

Similarly, the IDDQ of step S14
If a defect such as an element leak 1e is found in the test or the FUNC test in step S15, etc., after determining that the chip is defective, the P detection program is immediately terminated, and the P detection analysis program is loaded (executed). Abnormal spot identification shown in step S19, which is analysis, is performed.

Note that the potential setting of each probe in the P detection is maintained when the short-circuit portion is specified in step S18 or the abnormal portion is specified in step S19.

In the P detection analysis program, VDD3
A voltage of 1 V is applied between the e-VSS 3f, and the current value of the detection element 3 provided at each address of the detection substrate 4 is monitored (monitored) by the ammeter 5 (step S2).
0).

The ammeter 5 is installed in the P detector 11 and is not incorporated in the detection board 4.

Here, as shown in FIG. 6, when a defect such as a wiring short 1d or an element leak 1e occurs in the semiconductor chip 1, heat / light emission / infrared radiation occurs at the defective portion and heat / light / infrared radiation or the like occurs. Medium 2 is emitted.
These media 2 diffuse through the interlayer film 1f of the semiconductor wafer 1g toward the back surface of the semiconductor wafer.

As a result, of the plurality of detecting elements 3 provided on the detecting substrate 4, the detecting element 3 immediately below the defective portion such as the wiring short 1d or the element leak 1e detects light, heat and infrared rays and latches up. Then, the current transiently increases in this current path and becomes the latch-up element 3p.

The upper limit of the latch-up current of the detecting element 3 is set to, for example, 10 mA, and when at least one of the current paths reaches 10 mA, VDD3e-VSS
By programming so that the voltage between 3f is set to the OFF state, it is possible to specify that the portion immediately above the detection element 3 which has reached 10 mA first in the detection substrate 4 is a defective portion, and that noise or offset may occur. Displacement can be prevented.

Therefore, the P detection device 11 can automatically detect the latch-up path (step S21),
As a result, corresponding to the detection elements 3 arranged in a matrix,
During the P detection, the latch-up element 3
The position of p can be detected as coordinates by the X coordinate 6 and the Y coordinate 7 (step S22).

Thereafter, the polishing analysis can be performed by superimposing the coordinates of the defective portion detected by the P detection analysis program on the layout.

That is, after detecting a defective portion, the main surface 1a of the semiconductor chip 1 is mechanically polished from above based on the result of the detection, a desired layer is exposed, and the exposed surface is exposed to a microscope or the like. By observing, a detailed position inside the defective portion is recognized.

Then, the internal position of the recognized defective part is
The feedback is provided to the person in charge of the process element in the previous process of the semiconductor design.
Take measures against defects such as e.

As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the analysis result by the P inspection device 11 shown in FIG. 4 is fed back to the person in charge of the process element.

According to the method of manufacturing a semiconductor device of the present embodiment and the semiconductor manufacturing device (P inspection device 11) used therein, the following operational effects can be obtained.

That is, a detection substrate 4 provided with a plurality of detection elements 3 capable of detecting a medium 2 such as light, heat and infrared light generated from a defective portion of the semiconductor chip 1 and amplifying current by using a matrix arrangement is used. By performing a probe test on the semiconductor chip 1 (semiconductor wafer 1g), it is possible to simultaneously detect the medium 2, such as light, heat, and infrared light, generated from the defective portion.

Here, FIG. 7 shows an example of the respective detection sensitivities when a defective portion is detected (failure analysis) by the P inspection device 11 of this embodiment shown in FIG. 4 and the inspection device of the comparative example. 7A shows the detection sensitivity of the P detection device 11 of the present embodiment, and FIG. 7B shows the detection sensitivity of the inspection device of the comparative example.

As shown in FIG. 7, in the inspection device of the comparative example (FIG. 7B), the peak value 13
And the noise 13a are relatively small, the peak value 13 of the defective portion is smaller than the set lower limit (Q) of the detection sensitivity of the inspection apparatus, and thus it is difficult to detect the defective portion. On the other hand, the P detection device 11 of the present embodiment
In FIG. 7A, the peak value 12 (sum of light, heat, and infrared peaks) and the noise 12 of the defective portion of the detection level are shown.
a is relatively large, so the set P detection device 11
The peak value 12 of the defective portion is much larger than the lower limit (Q) of the detection sensitivity of
And it can specify with high precision.

Therefore, by providing the detection elements 3 in a matrix arrangement in the vicinity of the semiconductor chip 1 (semiconductor wafer 1 g) and performing a probe test (electrical test) of the semiconductor chip 1, the detection from the defective portion of the semiconductor chip 1 is performed. Light, heat, and infrared light can be detected, and the detection result can be represented as coordinates.

As a result, the accuracy of specifying a defective portion can be improved.

Further, since the accuracy of specifying a defective portion can be improved, accurate failure analysis can be performed, and the analysis result is fed back to a person in charge of process design, whereby the yield can be improved and the stability can be improved at an early stage. .

Further, the P detection device 11 provided with the detection substrate 4
By performing a probe test as in this embodiment as an electrical test using a (semiconductor manufacturing apparatus), a defective portion of the semiconductor chip 1 can be determined while a desired pattern is applied to an integrated circuit of the semiconductor chip 1. It becomes possible to specify.

As a result, it is possible to perform an inspection in a pattern application state, which is difficult at the conventional analysis level due to an IDDQ failure in a logic circuit of a CMOS device, etc., thereby improving the throughput (processing capacity) of analyzing a defective portion. it can.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

For example, in the above-described embodiment, a detection substrate 4 provided with a plurality of detection elements 3 is prepared, and a semiconductor wafer 1g for inspection is arranged on the detection substrate 4 to perform a probe inspection. As described in the latch-up detection method of the modification shown in FIG. 8, the detection element 3 is embedded in the silicon substrate 1i in advance to form various elements 1c on the silicon substrate 1i. A semiconductor wafer 1g may be formed, and a probe inspection including a failure analysis may be performed on the semiconductor wafer 1g.

That is, the semiconductor wafer 1g used for latch-up detection in the modification shown in FIG. 8 is of a type having a built-in detection substrate.

Regarding the formation of this semiconductor wafer 1g,
For example, SOI (Silicon On Insulator) technology is used. That is, as shown in FIG. 8, the insulating film 1h is formed on the silicon substrate 1i to such a depth that the characteristics of the device (LSI) are not lost, and the light generated from the defective portion of the semiconductor chip 1 is formed thereunder. A plurality of detecting elements 3 capable of detecting a medium 2 such as heat and infrared rays and amplifying the current by detecting the medium 2 are arranged in a matrix arrangement.

Further, various elements 1c and wirings 1b are formed on the silicon substrate 1i via an insulating film 1h.

As a result, the plurality of detection elements 3 are provided in a matrix arrangement immediately below (near) the semiconductor chip 1.

Therefore, the medium 2 such as light, heat and infrared light generated from the defective portion in the probe test is detected by the detecting element 3 immediately below the defective portion of the semiconductor chip 1 to amplify the current in the detecting element 3. Latch-up is performed, and the position of the defective portion of the semiconductor chip 1 is detected as coordinates corresponding to the position of the detection elements 3 in the matrix arrangement by the latch-up.

As a result, the medium 2 such as light, heat and infrared light generated from the defective portion of the semiconductor chip 1 can be detected by the detecting element 3 immediately below the defective portion.
As a result, the detection sensitivity of the P detection device 11 can be improved.

As a result, it is possible to further improve the accuracy of specifying the defective portion and the throughput of the analysis processing.

Further, in the above-described embodiment, the case where the latch-up phenomenon can be caused as the detecting element 3 and the latch-up phenomenon is provided in a matrix arrangement is described. A fine current amplifier circuit such as a circuit may be used.

Further, in the above embodiment, the case where the semiconductor manufacturing apparatus is the P inspection apparatus 11 and the probe inspection is used as the electrical inspection of the semiconductor chip 1 has been described. Wafer inspection (W
In this case, a function capable of performing the same failure analysis as the failure analysis of the above embodiment may be attached to the W inspection device.

As a result, it is possible to specify the coordinates of the defective portion generated in the W inspection, and to determine the TEG (Test Element).
This can be an effective means even in testing a wide area circuit for evaluation such as a Group) pattern.

Further, the semiconductor manufacturing apparatus does not conduct an electrical inspection of the semiconductor chip 1 or the semiconductor wafer 1g, but can simply detect the medium 2 such as light, heat and infrared rays generated from a defective portion and amplify the current. A detection substrate 4 as shown in FIG. 3 provided with a plurality of detection elements 3 is provided, and only the failure analysis of the semiconductor chip 1 and the semiconductor wafer 1g is performed using the detection substrate 4 in the same manner as in the above-described embodiment. May be an inspection device that performs the following.

In the above embodiment, the detecting element 3
However, the case where three media 2 of light, heat, and infrared light are detected has been described, but the condition of the detection medium 2 of the detection element 3 only needs to be able to detect at least light and heat.

In the above embodiment, the detection substrate 4
The semiconductor chip 1 by the chuck 10 in which
Although the case where the electrical inspection and the failure analysis are performed by supporting the semiconductor wafer 1g having the above-described structure has been described, the object to be subjected to the electrical inspection and the failure analysis may be a single semiconductor chip 1 after dicing. Or a semiconductor wafer 1g before dicing having the semiconductor chips 1.

Therefore, when performing the probe inspection and the failure analysis of the semiconductor chip 1 after the dicing, the individual semiconductor chips 1 after the dicing are subjected to the P inspection apparatus 1 shown in FIG.
Placed on a chuck 10 provided with one detection substrate 4,
In this state, probe inspection and failure analysis of the semiconductor chip 1 are performed.

[0093]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1). By detecting light, heat and infrared rays generated from a defective portion of the semiconductor chip and electrically inspecting the semiconductor chip using a detection substrate provided with a plurality of detection elements capable of current amplification in a matrix arrangement, Light, heat, and infrared light generated from a location can be detected simultaneously. Thus, light, heat, and infrared rays from the defective portion can be detected and the detection result can be represented as coordinates. As a result, the accuracy of specifying the defective portion can be improved.

(2). According to the above (1), accurate failure analysis becomes possible, and the analysis result is fed back to the person in charge of the process design, whereby the yield can be improved and stabilized at an early stage.

(3). By performing a probe test as an electrical test using a semiconductor manufacturing apparatus (P inspection apparatus) provided with a detection substrate, a defective portion of the semiconductor chip can be detected while a desired pattern is applied to an integrated circuit of the semiconductor chip. As a result, it is possible to perform an inspection in a pattern application state that is difficult at a conventional analysis level due to an IDDQ failure in a CMOS logic circuit or the like, and therefore, it is possible to improve the processing capability of failure analysis.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are diagrams showing an example of the principle of detection of a detection element provided on a detection substrate used in a method of manufacturing a semiconductor device according to an embodiment of the present invention; (A) is a schematic circuit diagram, (b) is an equivalent circuit diagram of (a), and (c) is a latch-up flow diagram.

FIG. 2 is a conceptual diagram showing an example of an internal configuration of a detection element shown in FIG.

FIG. 3 is a conceptual board diagram showing an example of a circuit configuration of a detection board provided with a plurality of detection elements shown in FIG. 2 in a matrix arrangement.

FIG. 4 is a conceptual diagram showing a basic structure of a P inspection apparatus which is an example of a semiconductor manufacturing apparatus of the present embodiment using the detection substrate shown in FIG.

5 is a flowchart showing an example of a procedure of a P test and a flow of a P test analysis program in the method of manufacturing a semiconductor device of the present embodiment using the P test device shown in FIG. 4;

6 is a conceptual diagram showing an example of a latch-up state of a detection element when performing P detection based on the P detection flow shown in FIG.

FIGS. 7A and 7B are diagrams showing an example of detection sensitivity when detecting a defective portion by the P inspection apparatus of the present embodiment shown in FIG. 4 and the inspection apparatus of a comparative example with respect to the P inspection apparatus. In the figure, (a) shows the detection sensitivity of the P detection device of the present embodiment, and (b) shows the detection sensitivity of the inspection device of the comparative example.

FIG. 8 is a conceptual diagram showing a latch-up state of a detection element in a latch-up detection method according to a modification of the latch-up detection method shown in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor chip 1a main surface 1b wiring 1c element 1d wiring short-circuit (defective) 1e element leak (defective) 1f interlayer film 1g semiconductor wafer 1h insulating film 1i silicon substrate 2 medium 3 detecting element 3a P-type impurity semiconductor 3b N-type impurity semiconductor 3c PNP transistor 3d NPN transistor 3e VDD 3f VSS 3g First current (current) 3h Second current (current) 3i First trigger current 3j Second trigger current 3k First wiring 3l Second wiring 3m Contact hole 3n Through hole 3p Latch-up Element 3q Non-latch-up element 3r First resistor 3s Second resistor 3t Element formation area 3u Lead-out wiring 4 Detection board 5 Ammeter 6 X coordinate (coordinate) 7 Y coordinate (coordinate) 8 Inspection probe 9 Inspection unit 10 Chuck 11 P inspection equipment (semiconductor manufacturing equipment) 12 Over click value 12a noise 13 peak 13a noise

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G01R 31/26 G01R 31/26 G Z 31/302 31/28 LF term (reference) 2G003 AA02 AA07 AA10 AB01 AB16 AB18 AF06 AH01 AH04 AH10 2G011 AA01 AE03 2G032 AA00 AB20 AD08 AD10 AE02 AE06 AE07 AE08 AE12 AL00 4M106 AA01 AA02 BA01 BA14 CA16 CA19 CA20 CA50 DH13 DH14

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device for detecting a defective portion of a semiconductor chip, comprising a plurality of detecting elements capable of detecting current and amplifying light by detecting light and heat generated from the defective portion of the semiconductor chip. Preparing a substrate for detection, arranging the semiconductor chip or a semiconductor wafer having the semiconductor chip on the substrate for detection, and electrically inspecting the semiconductor chip; The light and heat generated are detected by the detection element to amplify the current in the detection element, and the position of the defective portion of the semiconductor chip is determined in accordance with the position of the detection element recognized by the current amplification. A method for manufacturing a semiconductor device, comprising: detecting. 2. A method of manufacturing a semiconductor device for detecting a defective portion of a semiconductor chip, comprising a plurality of detection elements capable of detecting current, light and heat generated from the defective portion of the semiconductor chip and amplifying current. Preparing the obtained detection substrate, arranging the semiconductor chip or the semiconductor wafer having the semiconductor chip on the detection substrate, and electrically inspecting the semiconductor chip. The light generated from the location, the heat and the infrared light are detected by the detection element, the current in the detection element is amplified and latched up, and the position is detected corresponding to the position of the detection element recognized by the latchup. A method of manufacturing a semiconductor device, comprising detecting a position of the defective portion of a semiconductor chip. 3. A method for manufacturing a semiconductor device for detecting a defective portion of a semiconductor chip, comprising: a plurality of detecting elements capable of detecting current, light and heat generated from the defective portion of the semiconductor chip and capable of amplifying current. Preparing a detection substrate provided in an arrangement, arranging the semiconductor chip or a semiconductor wafer having the semiconductor chip on the detection substrate, and performing a probe inspection of the semiconductor chip; and The position of the detection element in the matrix arrangement which is detected by detecting the light, the heat and the infrared ray generated from the defective portion by the detection element, amplifying the current in the detection element and latching up, and recognizing the latch-up. Manufacturing the semiconductor device, wherein the position of the defective portion of the semiconductor chip is detected as coordinates in correspondence with Method. 4. A method of manufacturing a semiconductor device for detecting a defective portion of a semiconductor chip, wherein the semiconductor chip is formed, and light, heat and infrared rays generated from the defective portion of the semiconductor chip can be detected to amplify current. Preparing a semiconductor wafer provided with a silicon substrate provided with a plurality of detection elements in a matrix arrangement near the semiconductor chip; andprobe-testing the semiconductor chip. The matrix arrangement that detects the generated light, the heat, and the infrared ray by the detection element near the defective portion of the semiconductor chip, amplifies a current in the detection element and latches up, and recognizes the latch-up. Detecting the position of the defective portion of the semiconductor chip as coordinates in accordance with the position of the detection element. A method of manufacturing a semiconductor device. 5. A semiconductor manufacturing apparatus capable of detecting a defective portion of a semiconductor chip, comprising: a plurality of detecting elements capable of detecting light and heat generated from the defective portion of the semiconductor chip and amplifying a current; A semiconductor chip or a detection substrate capable of supporting a semiconductor wafer having the same is provided, and the light and the heat generated from the defective portion of the semiconductor chip are detected by the detection element, and a current in the detection element is detected. A semiconductor manufacturing apparatus capable of amplifying and detecting a position of the defective portion of the semiconductor chip in accordance with a position of the detection element recognized by the current amplification.