JP2002057193A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2002057193A
JP2002057193A JP2000238726A JP2000238726A JP2002057193A JP 2002057193 A JP2002057193 A JP 2002057193A JP 2000238726 A JP2000238726 A JP 2000238726A JP 2000238726 A JP2000238726 A JP 2000238726A JP 2002057193 A JP2002057193 A JP 2002057193A
Authority
JP
Japan
Prior art keywords
brazing material
support plate
external lead
semiconductor device
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000238726A
Other languages
Japanese (ja)
Other versions
JP3446829B2 (en
Inventor
Takaaki Yokoyama
隆昭 横山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP2000238726A priority Critical patent/JP3446829B2/en
Publication of JP2002057193A publication Critical patent/JP2002057193A/en
Application granted granted Critical
Publication of JP3446829B2 publication Critical patent/JP3446829B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0134—Quaternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve a problem that it is difficult for a semiconductor device for power having an external lead to satisfy all electric, thermal and mechanical characteristics. SOLUTION: Semiconductor chips 1 and 2 are fixed on a supporting board by a brazing filler metal, with which a fusing point is low but wettability is satisfactory. Internal connecting members 7 and 8 for connecting non-linked external leads 5 and 6, which are not linked to the supporting board 3, and the semiconductor chips are fixed to the non-linked external leads 5 and 6 by a brazing filler member 15, with which wettability is adverse but a fusing point is high.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ダイオード、トラ
ンジスタ、ＩＣ等の半導体チップが固着された支持板
と、支持板に連結された連結外部リードと、支持板に連
結されていない非連結外部リードと、半導体チップと非
連結外部リードとを接続する内部接続部材とを有し、半
導体チップ及び前記内部接続部材がろう材で結合されて
いる半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a support plate to which semiconductor chips such as diodes, transistors and ICs are fixed, connected external leads connected to the support plate, and unconnected external leads not connected to the support plate. And an internal connection member for connecting the semiconductor chip and the unconnected external lead, wherein the semiconductor chip and the internal connection member are connected by a brazing material.

【０００２】[0002]

【従来の技術】定格電流が小さい半導体装置において
は、半導体チップと外部リードとの間を金細線を使用し
たワイヤボンディング方法で接続することが多い。しか
し、比較的大きな電流が流れる電力系の半導体装置で
は、金が溶融する恐れがあるために、金細線のワイヤボ
ンディングを使用することができない。アルミニウム細
線を使用するワイヤボンディング方法もあるが、この場
合にはアルカリ系のエッチング液を用いた洗浄工程にお
いてアルミニウム細線が溶解するので、これを採用する
ことは不適当である。従って、従来の電力系の半導体装
置においては、例えば銅（Ｃｕ）にニッケルメッキを施
した比較的太い内部接続部材が半導体チップと外部リー
ドとに半田で結合されている。2. Description of the Related Art In a semiconductor device having a small rated current, a semiconductor chip and an external lead are often connected by a wire bonding method using a fine gold wire. However, in a power semiconductor device through which a relatively large current flows, gold may be melted, so that gold wire bonding cannot be used. There is also a wire bonding method using an aluminum thin wire, but in this case, the aluminum thin wire is dissolved in a cleaning step using an alkaline etching solution, and thus it is inappropriate to employ this method. Therefore, in a conventional power semiconductor device, for example, a relatively thick internal connection member in which copper (Cu) is plated with nickel is soldered to the semiconductor chip and the external lead.

【０００３】[0003]

【発明が解決しようとする課題】ところで、樹脂封止体
等の外囲体から導出されている外部リードを半田ディッ
プ等によって外部回路に接続する時に外部リードに熱が
加わり、半導体チップを外部リードに接続している内部
接続部材の半田が溶融し、接続不良を起こすことがあ
る。この問題を解決するために融点の高いろう材を使用
することが考えられる。しかし、融点の高いろう材は融
点の低いろう材に比較して濡れ性が悪い。半導体チップ
を支持板に固着するためのろう材として融点が高く且つ
濡れ性の悪いろう材を使用すると、気泡が残存し且つろ
う材が不均一に分布し、熱抵抗が大きくなること、又は
十分な結合強度が得られないことがある。By the way, when an external lead led out of an outer enclosure such as a resin sealing body is connected to an external circuit by solder dip or the like, heat is applied to the external lead and the semiconductor chip is connected to the external lead. In some cases, the solder of the internal connection member connected to the wire may melt and cause a connection failure. In order to solve this problem, it is conceivable to use a brazing material having a high melting point. However, a brazing filler metal having a high melting point has poor wettability compared to a brazing filler metal having a low melting point. When a brazing filler metal having a high melting point and poor wettability is used as a brazing filler metal for fixing the semiconductor chip to the support plate, bubbles remain and the brazing filler metal is unevenly distributed, and the thermal resistance increases, or High bond strength may not be obtained.

【０００４】そこで、本発明の目的は、半導体チップの
支持板に対する良好な固着と半導体チップを外部リード
に接続するための内部接続部材の外部リードに対する接
続部分の耐熱性の確保とを合理的に達成することができ
る半導体装置を提供することにある。Accordingly, it is an object of the present invention to rationally secure good fixation of a semiconductor chip to a support plate and heat resistance of a connection portion of an internal connection member for connecting the semiconductor chip to an external lead to the external lead. It is to provide a semiconductor device that can be achieved.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
の本発明は、半導体チップと、前記半導体チップが固着
された金属製支持板と、前記支持板に連結された連結外
部リードと、前記支持板に連結されていない非連結外部
リードと、前記半導体チップと前記非連結外部リードと
を電気的に接続する内部接続部材と、前記半導体チップ
と前記支持板と前記内部接続部材と前記非連結外部リー
ドの前記内部接続部材に対する接続部とを囲むように設
けられた外囲体とを備えた半導体装置であって、前記半
導体チップの裏面は第１のろう材によって前記支持板に
固着され、前記内部接続部材の一端は第２のろう材によ
って前記半導体チップの表面に固着され、前記内部接続
部材の他端は第３のろう材によって前記非連結外部リー
ドに固着され、前記第１のろう材は、前記第３のろう材
よりも融点が低く且つ前記第３のろう材よりも濡れ性が
良い材料からなる半導体装置に係わるものである。な
お、請求項２に示すように、内部接続部材を半導体チッ
プに接続するための第２のろう材を、第１のろう材と同
様に第３のろう材よりも融点が低く且つ濡れ性の良いも
のとすることが望ましく、第１のろう材と同一材料とす
ることが更に望ましい。また、請求項３に示すように、
第１のろう材はＳｎとＡｇとから成るろう材又はＳｎ−
Ａｇ−Ｃｕ系ろう材又はＳｎ−Ａｇ−Ｃｕ−Ｂｉ系ろう
材又はＳｎとＳｂとから成るろう材であり、第３のろう
材はＳｎ−Ａｇ系ろう材又はＳｎ−Ｓｂ系ろう材又はＢ
ｉ−Ｚｎ系ろう材であることが望ましい。According to the present invention, there is provided a semiconductor device comprising: a semiconductor chip; a metal support plate to which the semiconductor chip is fixed; a connecting external lead connected to the support plate; An unconnected external lead that is not connected to a support plate, an internal connection member that electrically connects the semiconductor chip and the unconnected external lead, and an unconnected external connection between the semiconductor chip, the support plate, and the internal connection member. A semiconductor device having an outer body provided so as to surround a connection portion of an external lead to the internal connection member, wherein a back surface of the semiconductor chip is fixed to the support plate by a first brazing material, One end of the internal connection member is fixed to the surface of the semiconductor chip by a second brazing material, and the other end of the internal connection member is fixed to the unconnected external lead by a third brazing material. The first brazing material are those according to the third semiconductor device comprising a material is good wetting than and said third brazing material lower melting point than the brazing material. As described in claim 2, the second brazing material for connecting the internal connection member to the semiconductor chip has a lower melting point and a lower wettability than the third brazing material like the first brazing material. It is desirable that the first brazing material be the same as the first brazing material. Also, as shown in claim 3,
The first brazing material is a brazing material composed of Sn and Ag or Sn-
Ag-Cu brazing material, Sn-Ag-Cu-Bi brazing material, or brazing material composed of Sn and Sb, and the third brazing material is Sn-Ag-based brazing material, Sn-Sb-based brazing material, or B
Desirably, it is an i-Zn-based brazing material.

【０００６】[0006]

【発明の効果】各請求項の発明によれば、非連結外部リ
ードは支持板に連結されていないので、放熱性が連結外
部リードに比べて悪いが、非連結外部リードと内部接続
部材とを接続している第３のろう材は比較的融点が高い
ので、半田ディップ等によって外部から加わった熱で第
３のろう材が溶融することがない。また、連結外部リー
ドに連結されている支持板は放熱性が良く且つ半導体チ
ップの固着位置は連結外部リード及び非連結外部リード
の外囲体との境界を基準として非連結外部リードの第３
のろう材の位置よりも遠くにある。このため、連結外部
リードと非連結外部リードに同一の熱が加わった時に半
導体チップを固着している第１のろう材の温度が非連結
外部リードの第３のろう材の温度より低くなる。従っ
て、半導体チップを第３のろう材よりも融点の低い第１
のろう材で固着しても溶融の問題は発生しない。第１の
ろう材は第３のろう材に比べて融点を下げた分だけ濡れ
性を高められている。従って、半導体チップは支持板に
対して均一且つ気泡を含まない状態に良好に固着され
る。この結果、機械的強度の大きく且つ熱抵抗の小さい
半導体チップの固着が可能になる。また、第１のろう材
の濡れ性が良いので、半導体チップの支持板に対する固
着の作業を迅速且つ円滑に進めることができる。また、
請求項２の発明によれば、内部接続部材の半導体チップ
に対する接続を良好且つ容易に達成することができる。
また、請求項３の発明によれば、第１のろう材の濡れ性
が良くなり、また第３のろう材の比較的半田付け性及び
耐熱性が比較的良くなる。また、第1及び第3のろう材に
環境に対して問題があるＰｂ(鉛)を含まないろう材を使
用することによって環境対策が容易になる。According to the present invention, the unconnected external leads are not connected to the support plate, so that the heat dissipation is lower than that of the connected external leads. Since the connected third brazing material has a relatively high melting point, the third brazing material does not melt due to heat applied from the outside by solder dip or the like. Further, the support plate connected to the connection external lead has good heat dissipation and the fixing position of the semiconductor chip is determined based on the boundary between the connection external lead and the non-connection external lead and the surrounding body.
It is farther than the position of the brazing material. For this reason, when the same heat is applied to the connected external lead and the non-connected external lead, the temperature of the first brazing material fixing the semiconductor chip becomes lower than the temperature of the third brazing material of the non-connected external lead. Therefore, the semiconductor chip is formed of the first brazing material having a lower melting point than that of the third brazing material.
Even if it is fixed with a brazing material, no melting problem occurs. The first brazing material has higher wettability than that of the third brazing material by the lower melting point. Therefore, the semiconductor chip is satisfactorily fixed to the support plate in a uniform and bubble-free state. As a result, a semiconductor chip having high mechanical strength and low thermal resistance can be fixed. In addition, since the first brazing material has good wettability, the operation of fixing the semiconductor chip to the support plate can be performed quickly and smoothly. Also,
According to the second aspect of the present invention, the connection of the internal connection member to the semiconductor chip can be satisfactorily and easily achieved.
According to the third aspect of the present invention, the wettability of the first brazing material is improved, and the solderability and heat resistance of the third brazing material are relatively improved. Further, by using a brazing material that does not contain Pb (lead), which has a problem for the environment, as the first and third brazing materials, environmental measures can be easily performed.

【０００７】[0007]

【実施形態】次に、図１及び図２を参照して本発明の実
施形態に係わる半導体装置を説明する。Next, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

【０００８】図１に示す半導体装置は、全波整流回路を
構成するためのものであって、第１及び第２のシリコン
ダイオードチップ即ち半導体チップ１、２と、金属支持
板３と、連結外部リード４と、第１及び第２の非連結外
部リード５、６と、第１及び第２の内部接続部材７、８
と、外囲体としての例えばエポキシ樹脂から成る絶縁物
封止体９とを有している。The semiconductor device shown in FIG. 1 constitutes a full-wave rectifier circuit, and includes first and second silicon diode chips, ie, semiconductor chips 1 and 2, a metal support plate 3, and a connecting external device. Lead 4, first and second unconnected external leads 5, 6, and first and second internal connection members 7, 8
And an insulator sealing body 9 made of, for example, an epoxy resin as an envelope.

【０００９】半導体チップ１、２は、図２に示すように
ＰＮ接合を有するシリコン半導体基体１０と、この基体
１０の一方の主面に形成された例えばニッケルから成る
第１の金属電極１１と、基体１０の他方の主面に形成さ
れた例えばニッケルから成る第２の金属電極１２とをそ
れぞれ有し、それぞれの第２の金属電極１２が支持板３
に第１のろう材１３によって固着されている。第１及び
第２の半導体チップ１、２の表面側の第１の金属電極１
１に、銅線にニッケルメッキ被覆が形成されたものから
成る第１及び第２のワイヤ状の内部接続部材７、８の一
端が第１のろう材１３と同一の材料から成る第２のろう
材１４によってそれぞれ固着されている。内部接続部材
７、８の他端は第１及び第２の非連結外部リード５、６
の一端部に第３のろう材１５によってそれぞれ固着され
ている。As shown in FIG. 2, the semiconductor chips 1 and 2 include a silicon semiconductor substrate 10 having a PN junction, a first metal electrode 11 made of, for example, nickel and formed on one main surface of the substrate 10. A second metal electrode 12 made of, for example, nickel, formed on the other main surface of the base 10, and each of the second metal electrodes 12 is
Is fixed by a first brazing material 13. First metal electrode 1 on the front side of first and second semiconductor chips 1 and 2
First, one end of each of first and second wire-like internal connection members 7 and 8 made of a copper wire having a nickel plating coating formed thereon is made of a second brazing material made of the same material as the first brazing material 13. Each is fixed by a member 14. The other ends of the internal connection members 7 and 8 are connected to first and second unconnected external leads 5 and 6 respectively.
Are fixed to one end of each of them by a third brazing material 15.

【００１０】支持板３と及び外部リード４、５、６はリ
ードフレームに基づいて形成されたものであり、それぞ
れが例えば銅板の表面にニッケルメッキ層を設けた金属
板から成る。支持板３は、平面的に見てチップ１、２の
面積の数倍以上、好ましくは３倍以上、より好ましくは
５倍以上の面積を有する。帯状に形成された連結外部リ
ード４は支持板３と一体に形成されており、支持板３の
一方の端面から直線的に導出されている。第１及び第２
の非連結外部リード５、６は連結外部リード４に平行に
配置され、これ等の一端部は支持板３の一方の端面に対
して所定の間隔を介して接近配置されている。第１及び
第２の非連結外部リード５、６はリードフレーム状態の
時には連結条によって連結外部リード４と一体化されて
いるが、組立終了後に分離される。連結外部リード４、
第１及び第２の非連結外部リード５、６は支持板３と同
一の厚みを有し且つ支持板３の一方の端面の幅Ｗ1 より
も大幅に狭い幅Ｗ2 を有する。The support plate 3 and the external leads 4, 5, and 6 are formed based on a lead frame, and each is made of, for example, a metal plate provided with a nickel plating layer on the surface of a copper plate. The support plate 3 has an area that is several times or more, preferably three times or more, and more preferably five times or more the area of the chips 1 and 2 in a plan view. The strip-shaped connecting external lead 4 is formed integrally with the support plate 3, and is linearly led out from one end face of the support plate 3. First and second
The unconnected external leads 5 and 6 are arranged in parallel with the connected external lead 4, and one ends of these non-connected external leads are arranged close to one end face of the support plate 3 at a predetermined distance. The first and second unconnected external leads 5 and 6 are integrated with the connected external lead 4 by connecting strips in a lead frame state, but are separated after the assembly is completed. Connecting external lead 4,
The first and second unconnected external leads 5 and 6 have the same thickness as the support plate 3 and a width W2 that is significantly smaller than the width W1 of one end face of the support plate 3.

【００１１】半導体チップ１、２を支持板３に固着して
いる第１のろう材１３は、Ｓｎ（錫）とＡｇ（銀）との
合金から成る低温半田であって、融点が２２０℃よりも
低く且つ濡れ性即ち半田付け性が良い半田から成る。こ
の第１のろう材１３はＳｎ―Ａｇ系であることが望まし
く、この好ましい組成範囲は、Ｓｎ 96.5〜98.0重量
％、Ａｇ 2.0〜3.5 重量％である。この実施形態で
は、第２のろう材１４は第１のろう材１３と同一材料か
ら成り、第１のろう材と同様に比較的良い濡れ性と比較
的低い融点を有する。なお、第１及び第２のろう材１
３、１４としては、 Ｓｎ ９６．５重量％ Ａｇ ３．５重量％ の融点が２２１℃のＳｎ―Ａｇ系ろう材又は Ｓｎ ９５．７５ 重量％ Ａｇ ３．５０ 重量％ Ｃｕ ０．７５ 重量％ の融点２１７℃のＳｎ−Ａｇ−Ｃｕ系ろう材、又は、 Ｓｎ ９４．２５ 重量％ Ａｇ ２．００ 重量％ Ｃｕ ０．７５ 重量％ Ｂｉ ３．００ 重量％ のＳｎ−Ａｇ−Ｃｕ−Ｂｉ系ろう材、又は Ｓｎ ９５．５ 重量％ Ａｇ ２．０ 重量％ Ｃｕ ０．５ 重量％ Ｂｉ ２．０ 重量％ のＳｎ−Ａｇ−Ｃｕ−Ｂｉ系ろう材を使用することがで
きる。The first brazing material 13 for fixing the semiconductor chips 1 and 2 to the support plate 3 is a low-temperature solder made of an alloy of Sn (tin) and Ag (silver), and has a melting point of 220 ° C. And low solderability and good wettability, that is, good solderability. The first brazing material 13 is desirably Sn-Ag based, and the preferred composition range is 96.5 to 98.0% by weight of Sn and 2.0 to 3.5% by weight of Ag. In this embodiment, the second brazing material 14 is made of the same material as the first brazing material 13, and has a relatively good wettability and a relatively low melting point like the first brazing material. The first and second brazing materials 1
As for Nos. 3 and 14, Sn-Ag-based brazing material having a melting point of 221 ° C. or Sn 96.5 wt% Ag 3.5 wt% or Sn 95.75 wt% Ag 3.50 wt% Cu 0.75 wt% Sn-Ag-Cu-based brazing material having a melting point of 217 ° C, or Sn-Ag-Cu-Bi-based brazing material having a Sn content of 94.25 wt% Ag 2.00 wt% Cu 0.75 wt% Bi 3.00 wt% Or Sn 95.5% by weight Ag 2.0% by weight Cu 0.5% by weight Bi 2.0% by weight Sn-Ag-Cu-Bi-based brazing material can be used.

【００１２】第３のろう材１５は第１及び第２のろう材
１３、１４に比べて濡れ性が悪く且つ融点が約２３０℃
以上の高温のろう材から成り、例えば融点が２３２℃の
Ｓｎ１００％のろう材、又は Ｓｎ ９９．２５ 重量％ Ａｇ ０．７５ 重量％ から成る融点が２２７℃のＳｎ−Ａｇ系ろう材、又は Ｓｎ ９５ 重量％ Ｓｂ ５ 重量％ から成る融点が２３５℃のＳｎ‐Ｓｂ系ろう材、又は Ｂｉ ９７．３ 重量％ Ｚｎ ２．７ 重量％ の融点が２５５℃のＢｉ−Ｚｎ系ろう材である。The third brazing material 15 has poor wettability and a melting point of about 230 ° C. as compared with the first and second brazing materials 13 and 14.
The above high-temperature brazing material, for example, a 100% Sn brazing material having a melting point of 232 ° C., or a Sn—Ag-based brazing material having a melting point of 227 ° C. and consisting of 99.25% by weight of Ag and 0.75% by weight of Sn, or Sn It is a Sn-Sb-based brazing material having a melting point of 235 ° C and a Bi-Zn-based brazing material having a melting point of 255 ° C and a melting point of Bi 97.3% by weight of 2.7% by weight composed of 95% by weight and 5% by weight of Sb.

【００１３】絶縁物封止体９は第１及び第２の半導体チ
ップ１、２と支持板３と内部接続部材７、８と連結外部
リード４の支持板寄り部分と第１及び第２の非連結外部
リード５、６の支持板寄り端部とを覆うように例えばト
ランスファモールド法で形成されている。なお、第１、
第２及び第３のろう材１３、１４、１５も絶縁物封止体
９の内部に配置されている。The insulator sealing body 9 includes first and second semiconductor chips 1 and 2, a support plate 3, internal connection members 7 and 8, a portion of the connection external lead 4 near the support plate, and first and second non-conductive portions. The connection external leads 5 and 6 are formed by, for example, a transfer molding method so as to cover the end portions near the support plate. The first,
The second and third brazing materials 13, 14 and 15 are also arranged inside the insulator sealing body 9.

【００１４】外部リ−ド４、５、６の例えばプリント回
路基板等に対する接続を容易にするために、外部リ−ド
４、５、６の封止体９から露出している部分の表面に半
田ディップ法で半田被覆層を形成することがある。この
半田被覆層を形成する時には、外部リ−ド４、５、６を
溶融半田に接触させる。半田ディップ工程で外部リード
４、５、６が高温の溶融半田に接触すると、半田の熱が
連結外部リード４を介して第１及び第２のろう材１３、
１４に及び、また非連結外部リード５、６を介して第３
のろう材１５に及ぶ。非連結外部リード５、６は支持板
３に連結されておらず、放熱表面積が小さいので、これ
自体及び第３のろう材１５の温度が比較的高くなる。し
かし、第３のろう材１５の融点は例えば２３２℃のよう
に比較的高いので、半田ディップ時の熱によって溶融
し、接続不良を発生する恐れはない。半導体チップ１、
２の下面の第１のろう材１３及び上面の第２のろう材１
４は第３のろう材１５よりも低い融点を有するが、半田
ディップ時のこれ等の部分の温度上昇は第３のろう材１
５の温度上昇よりは低い。即ち、支持板３は大きな放熱
表面積を有するので、連結外部リード４から支持板３に
伝導した熱は速やかに放散され、第１及び第２のろう材
１３、１４の温度がさほど高くならず、第１及び第２の
ろう材１３、１４の溶融による接続不良が発生しない。
半導体装置をプリント回路基板に半田ディップ法で固着
する時にも、外部リ−ド４、５、６に熱が加わるが、第
１〜第３のろう材１３、１４、１５は前述の半田被覆層
の形成時と同様に接続不良状態にならない。In order to facilitate the connection of the external leads 4, 5, 6 to, for example, a printed circuit board or the like, the surfaces of the portions of the external leads 4, 5, 6 exposed from the sealing body 9 are provided. The solder coating layer may be formed by a solder dipping method. When forming the solder coating layer, the external leads 4, 5, and 6 are brought into contact with the molten solder. When the external leads 4, 5, and 6 come into contact with the high-temperature molten solder in the solder dipping process, the heat of the solder is transferred to the first and second brazing materials 13,
14 and the third via unconnected external leads 5,6
The brazing material 15. Since the unconnected external leads 5 and 6 are not connected to the support plate 3 and have a small heat radiation surface area, the temperature of themselves and the third brazing material 15 becomes relatively high. However, since the melting point of the third brazing material 15 is relatively high, for example, 232 ° C., there is no possibility that the third brazing material 15 will be melted by the heat during the solder dip and a connection failure will occur. Semiconductor chip 1,
2 the first brazing material 13 on the lower surface and the second brazing material 1 on the upper surface
4 has a lower melting point than the third brazing material 15, but the temperature rise of these portions during the solder dip is less than the third brazing material 1.
5 lower than the temperature rise. That is, since the support plate 3 has a large heat radiation surface area, the heat conducted from the connection external lead 4 to the support plate 3 is quickly dissipated, and the temperatures of the first and second brazing materials 13 and 14 do not increase so much. The connection failure due to the melting of the first and second brazing materials 13 and 14 does not occur.
When the semiconductor device is fixed to the printed circuit board by the solder dip method, heat is applied to the external leads 4, 5, and 6, but the first to third brazing materials 13, 14, and 15 are not covered with the above-mentioned solder coating layer. As in the case of the formation, the connection failure does not occur.

【００１５】本実施形態は次の効果を有する。 （１） 半導体チップ１、２を支持板３に固着するため
の第１のろう材１３は、濡れ性が良いものから成るの
で、ろう材の広がりが良く且つ気泡が少なくなり、第１
のろう材１３による半導体チップ１、２の固着を良好に
達成することができる。即ち、接着強度が大きく且つ電
気抵抗及び熱抵抗の小さい半導体チップ１、２の固着が
可能になる。また半導体チップ１、２の固着を作業性良
く達成することができる。要するに、第１、第２及び第
３のろう材１３、１４、１５の全てを第３のろう材１５
と同一の高温半田で構成する場合に比べて本実施例によ
れば、半導体チップ１、２の固着部の電気的、熱的及び
機械的特性が良く成る。 （２） 第２のろう材１４は第３のろう材１５よりも濡
れ性において優れているので、半導体チップ１、２に対
して内部接続部材７、８を良好且つ作業性良く接続する
ことができる。 （３） Ｐｂ(鉛)を含まないろう材を使用するので、環
境対策が容易になる。This embodiment has the following effects. (1) Since the first brazing material 13 for fixing the semiconductor chips 1 and 2 to the support plate 3 is made of a material having good wettability, the spread of the brazing material is good and the number of bubbles is reduced.
The semiconductor chips 1 and 2 can be satisfactorily fixed by the brazing material 13. That is, the semiconductor chips 1 and 2 having high adhesive strength and low electrical resistance and thermal resistance can be fixed. Further, the fixation of the semiconductor chips 1 and 2 can be achieved with good workability. In short, all of the first, second and third brazing materials 13, 14 and 15 are replaced with the third brazing material 15.
According to the present embodiment, the electrical, thermal and mechanical properties of the fixing portions of the semiconductor chips 1 and 2 are improved as compared with the case where the same high temperature solder is used. (2) Since the second brazing material 14 is superior to the third brazing material 15 in wettability, it is possible to connect the internal connection members 7 and 8 to the semiconductor chips 1 and 2 with good workability. it can. (3) Since a brazing material that does not contain Pb (lead) is used, environmental measures are facilitated.

【００１６】[0016]

【変形例】本発明は上述の実施形態に限定されるもので
なく、例えば次の変形が可能なものである。 （１） 絶縁物封止体９を金属容器による封止体（カン
封止体）、又はセラミック容器による封止体としてもよ
い。また、支持板３の一部を露出するように封止体９形
成することができる。 （２） 非連結外部リード５、６の内の一方を省くこと
ができる。また、非連結外部リード及び連結外部リード
を増やすことができる。 （３） 半導体チップ１、２をダイオードチップ以外の
トランジスタ、サイリスタ、ＩＣチップ等とすることが
できる。支持板３に１つのトランジスタチップを配置す
る場合には第１及び第２の内部接続部材７、８をエミッ
タ、ベースの接続に利用する。 （４） 第２のろう材１４は、第１のろう材１３とは別
の材料とすることができる。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The insulator sealed body 9 may be a sealed body (can sealed body) using a metal container or a sealed body using a ceramic container. Moreover, the sealing body 9 can be formed so that a part of the support plate 3 is exposed. (2) One of the unconnected external leads 5 and 6 can be omitted. Further, the number of unconnected external leads and connected external leads can be increased. (3) The semiconductor chips 1 and 2 can be transistors, thyristors, IC chips, etc. other than diode chips. When one transistor chip is arranged on the support plate 3, the first and second internal connection members 7, 8 are used for connecting the emitter and the base. (4) The second brazing material 14 can be a different material from the first brazing material 13.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形態に従う半導体装置を封止体を
省いた状態で示す平面図である。FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention with a sealing body omitted.

【図２】図１の半導体装置の左側面図である。FIG. 2 is a left side view of the semiconductor device of FIG. 1;

【符号の説明】[Explanation of symbols]

１、２ 半導体チップ ３ 支持板 ４ 連結外部リード ５、６ 非連結外部リード ７、８ 内部接続部材 ９ 絶縁封止体 １３ 第１のろう材 １４ 第２のろう材 １５ 第３のろう材 DESCRIPTION OF SYMBOLS 1, 2 Semiconductor chip 3 Support plate 4 Connecting external lead 5, 6 Non-connecting external lead 7, 8 Internal connecting member 9 Insulation sealing body 13 First brazing material 14 Second brazing material 15 Third brazing material

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｃ２２Ｃ 13/02 Ｃ２２Ｃ 13/02 Ｈ０１Ｌ 21/52 Ｈ０１Ｌ 21/52 Ａ // Ｂ２３Ｋ 101:40 Ｂ２３Ｋ 101:40 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) C22C 13/02 C22C 13/02 H01L 21/52 H01L 21/52 A // B23K 101: 40 B23K 101: 40

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップと、前記半導体チップが固
着された金属製支持板と、前記支持板に連結された連結
外部リードと、前記支持板に連結されていない非連結外
部リードと、前記半導体チップと前記非連結外部リード
とを電気的に接続する内部接続部材と、前記半導体チッ
プと前記支持板と前記内部接続部材と前記非連結外部リ
ードの前記内部接続部材に対する接続部とを囲むように
設けられた外囲体とを備えた半導体装置であって、 前記半導体チップの裏面は第１のろう材によって前記支
持板に固着され、 前記内部接続部材の一端は第２のろう材によって前記半
導体チップの表面に固着され、 前記内部接続部材の他端は第３のろう材によって前記非
連結外部リードに固着され、 前記第１のろう材は、前記第３のろう材よりも融点が低
く且つ前記第３のろう材よりも濡れ性が良い材料からな
ることを特徴とする半導体装置。A semiconductor chip; a metal support plate to which the semiconductor chip is fixed; a connection external lead connected to the support plate; a non-connection external lead not connected to the support plate; An internal connection member that electrically connects the chip and the unconnected external lead; and a semiconductor chip, the support plate, the internal connection member, and a connection portion of the unconnected external lead to the internal connection member. A semiconductor device provided with an outer enclosure provided, wherein a back surface of the semiconductor chip is fixed to the support plate by a first brazing material, and one end of the internal connection member is formed by a second brazing material in the semiconductor. The other end of the internal connection member is fixed to the unconnected external lead by a third brazing material, and the first brazing material has a melting point higher than that of the third brazing material. A semiconductor device, comprising the Ku and the third material is good wetting than the brazing material. 【請求項２】 前記第２のろう材は、前記第３のろう材
よりも濡れ性が良く且つ前記第３のろう材よりも融点が
低い材料から成ることを特徴とする請求項１記載の半導
体装置。2. The method according to claim 1, wherein the second brazing material is made of a material having better wettability than the third brazing material and having a lower melting point than the third brazing material. Semiconductor device. 【請求項３】 前記第１のろう材は、ＳｎとＡｇとから
成るろう材又はＳｎとＡｇとＣｕとから成るろう材又は
ＳｎとＡｇとＣｕとＢｉとから成るろう材であり、前記
第３のろう材は、Ｓｎから成るろう材又はＳｎとＡｇと
から成るろう材又はＳｎとＳｂとから成るろう材又はＢ
ｉとＺｎとから成るろう材であることを特徴とする請求
項１又は２記載の半導体装置。3. The first brazing material is a brazing material composed of Sn and Ag, a brazing material composed of Sn, Ag and Cu, or a brazing material composed of Sn, Ag, Cu and Bi. The brazing material No. 3 is a brazing material consisting of Sn, a brazing material consisting of Sn and Ag, a brazing material consisting of Sn and Sb, or B
The semiconductor device according to claim 1, wherein the semiconductor device is a brazing material made of i and Zn.
JP2000238726A 2000-08-07 2000-08-07 Semiconductor device Expired - Fee Related JP3446829B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000238726A JP3446829B2 (en) 2000-08-07 2000-08-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000238726A JP3446829B2 (en) 2000-08-07 2000-08-07 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2002057193A true JP2002057193A (en) 2002-02-22
JP3446829B2 JP3446829B2 (en) 2003-09-16

Family

ID=18730383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000238726A Expired - Fee Related JP3446829B2 (en) 2000-08-07 2000-08-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3446829B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009542A (en) * 2009-06-26 2011-01-13 Senju Metal Ind Co Ltd Solder-coated lid
JP2012254470A (en) * 2011-06-09 2012-12-27 Sumitomo Metal Mining Co Ltd SEMICONDUCTOR DEVICE USING Bi-BASED SOLDER
JP2017152581A (en) * 2016-02-25 2017-08-31 株式会社東芝 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009542A (en) * 2009-06-26 2011-01-13 Senju Metal Ind Co Ltd Solder-coated lid
JP2012254470A (en) * 2011-06-09 2012-12-27 Sumitomo Metal Mining Co Ltd SEMICONDUCTOR DEVICE USING Bi-BASED SOLDER
JP2017152581A (en) * 2016-02-25 2017-08-31 株式会社東芝 Semiconductor device

Also Published As

Publication number Publication date
JP3446829B2 (en) 2003-09-16

Similar Documents

Publication Publication Date Title
JP4788119B2 (en) Electronic device, semiconductor device and semiconductor module
JP3757881B2 (en) Solder
KR100867575B1 (en) Power module package improved heat radiating capability and method for manufacturing the same
US20050056918A1 (en) Power module package having improved heat dissipating capability
JP2009302564A (en) Ic chip package with directly connected leads
CN102522376A (en) Microelectronic package and heat dissipation method thereof
CN103123916B (en) Semiconductor device, electronic device and method, semi-conductor device manufacturing method
JP5214936B2 (en) Semiconductor device
CN109168320B (en) Semiconductor device with a plurality of semiconductor chips
JP2001110957A (en) Method for manufacturing power semiconductor module
WO2012060054A1 (en) Circuit device and method for manufacturing same
USRE27934E (en) Circuit structure
CN110729199A (en) Selective plating of leads of semiconductor packages
JP3685659B2 (en) Manufacturing method of semiconductor device
JP3446829B2 (en) Semiconductor device
JP2003289129A (en) Semiconductor device
JP2003297994A (en) Semiconductor device and manufacturing method thereof
JP2006041363A (en) Resin-sealed semiconductor device
JP4861200B2 (en) Power module
EP4145495A1 (en) Method of manufacturing an electrical interconnect for a semiconductor device as well as the corresponding device having the same
JP7404726B2 (en) semiconductor equipment
US20230132056A1 (en) Semiconductor device and method for manufacturing the same
JP2521624Y2 (en) Semiconductor device
JP2001358244A (en) Power semiconductor module
US20170323801A1 (en) Method of generating a power semiconductor module

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080704

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees