JP2002057121A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize manufacturing-process simplification and device-element miniaturization by forming buried-wiring which makes a silicide process and device-element wiring common in the formation of miniaturized inter-device- element wiring using the silicide process. SOLUTION: A surface of an insulating film formed on a semiconductor substrate is subjected to plasma processing in which at least oxygen and fluorine are contained. A refractory metal formed on the insulating film is subjected to a heat treatment. The salicide process for a MOSFET is commonly shared with the wiring process, and since the contacts and the wiring are composed of almost a same material, contact failure caused by electrical or chemical difference does not generate. Besides, since the contacts and the wiring are formed in a self-aligning manner, areas for source and drain can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a structure and a method of manufacturing a transistor including a silicide layer.

[0002]

2. Description of the Related Art Although the speeding up of elements has been achieved in accordance with the scaling law, the speeding up to date has been difficult due to the existence of non-scaled parameters. Increasing sheet resistance, contact resistance, and gate electrode resistance of the diffusion layer due to miniaturization have become a problem.
As a means for solving this, a salicide structure in which a silicide layer is stuck to the source, drain and gate electrodes in a self-aligned manner has been proposed. A conventional method for manufacturing a salicide structure will be described below. A gate electrode made of polysilicon is formed on a semiconductor substrate on which an element isolation region is formed. Next, after forming a first oxide film on the element region, phosphorus is ion-implanted.

Subsequently, an insulating film, for example, a nitride film is deposited,
Using a mixed gas of CF4, N2 and H2 or a mixed gas of CHF3 and CO, the gate side wall is formed on the side of the gate electrode by etching back. Next, a second oxide film is formed on the element region, and arsenic is ion-implanted using the gate electrode, the gate side wall, and the element isolation region as a mask. Subsequently, heat treatment for activating the impurities is performed to form an LDD type source and drain. Next, the salicide process is started.

After removing the oxide film on the source, the drain and the gate using a dilute HF solution, Ti is deposited, and a heat treatment is performed to silicide the contact portion between silicon and Ti. Next, unreacted Ti on the side wall and the element isolation region is selectively removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide solution. Thereafter, the NMOS transistor having a self-aligned silicide layer is completed through ordinary steps such as deposition of an interlayer insulating film, contact opening, and wiring formation.

[0005]

In the above silicide formation method, since the main diffusion species of TiSi2 is Si, the film is likely to crawl due to the movement of Si during the formation of the silicide, and the silicide is formed. As a result, there is a problem that the yield is reduced. Further, there is a problem that a deposition film adheres during the formation of the side wall, and this reacts with Ti to break the selective formation of the silicide film.

Further, in the above process, after ion implantation, the oxide film formed on the gate electrode and the source and drain regions is removed. If the removal of the oxide film is not complete, the selectivity of the formation of the TiSi2 film is reduced. Is not enough. However, the thickness of the oxide film formed on the polysilicon of the gate electrode material is larger than that on the silicon which is the diffusion layer. Therefore, it is difficult to simultaneously and completely remove the oxide film by wet processing or the like. Was. This is because if the processing time is lengthened to completely remove the oxide film on the polysilicon, the field edge portion is recessed, which causes a junction leak.

[0007] In addition, if fine inter-element wiring using the above-described silicide process is to be performed using a normal wiring technique, it is necessary to newly form a wiring material and process it. Has become a problem.

Further, as the element becomes finer, the concentration of the substrate increases in order to suppress the short channel effect. Therefore, the junction capacitance between the substrate and the high-concentration diffusion layer serving as the source and drain increases, and the device Was a major obstacle to speeding up the process.

[0009]

SUMMARY OF THE INVENTION The present invention comprises a step of forming an insulating film on a semiconductor substrate, a step of performing a plasma treatment on the surface of the insulating film at least containing oxygen and fluorine,
A method for manufacturing a semiconductor device includes a step of forming a refractory metal layer on the insulating film and a step of heat-treating the refractory metal.

According to this structure, the salicide step of the MOSFET and the wiring step can be performed simultaneously.
At the same time as the contacts (salicide portions) on the source and drain diffusion layers of the ET, a wiring connecting them can be formed.
In addition, since the contact and the wiring are made of substantially the same material, there is no occurrence of a contact failure due to an electrical or chemical difference, which is a problem when different materials are used. Further, since the wiring is directly connected to the salicide portion, this wiring is a contact on the whole surface in principle.

Further, since the current path can be formed from the line to the surface, the resistance can be reduced and the reliability of the wiring can be ensured. In addition, there is no need to form a special structure to form a wiring, and, of course, there is no step due to being embedded. Therefore, it is extremely advantageous for the subsequent deposition and planarization of the interlayer insulating film. Further, if a normal local interconnection step is further performed after this step, it is possible to achieve a multilayered local interconnection.

Further, in order to form the contact and the wiring in a self-aligned manner, the source and drain diffusion layers which had to be secured by using the conventional contact and have a large area can be reduced, and the contact is completely formed. it can. Therefore, it has an absolute advantage in reducing the size and speed of the device.

Since a shorter source / drain diffusion layer can be achieved, the capacitance between this portion and the substrate can be reduced, and the diffusion layer can be made relatively deep, so that the process margin for salicide and the like can be significantly improved, and junction leakage can be improved. Etc. can be suppressed.

This process can be applied not only to local interconnection but also to the formation of an interlayer insulating film and other electrodes for devices as a method of forming a conductive layer, a buried electrode and the like in an insulating film. Can be widely adapted.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1)
This will be described with reference to FIG. 1 taking a MOS as an example.

A 20 nm-thick thermal oxide film is formed on the semiconductor substrate 101 on which the element isolation region 102 is formed, and boron ions are implanted for controlling a threshold value and for a pante through stopper.

Next, after removing the thermal oxide film and forming an 11 nm gate oxide film 103, a 350 nm thick polysilicon is deposited, and a heat treatment is performed in POCl 3 at 850 ° C. for 30 minutes to remove the polysilicon. To N +. next,
The gate electrode 104 is formed by patterning the N + polysilicon.

Subsequently, thermal oxidation was performed at 900 ° C. for 10 minutes,
The oxide film 10 is formed in a yO2 atmosphere, and the oxide film 10
5 is formed. Next, 40 keV, 7
Ion implantation is performed under the condition of E13 cm @ -2 to form an N @-layer. Next, a nitride film is deposited to a thickness of 15 nm by LPCVD.

Further, a side wall 106 is formed on the side of the gate electrode by anisotropic etching using CHF3 gas. Next, thermal oxidation is performed at 850 ° C. in a DryO2 atmosphere.
An oxide film 107 having a thickness of about 15 nm is formed on the element region.

After that, arsenic is applied at 50 keV and 3E15 cm.
Ion implantation is performed under the condition of -2, and activation is performed in N2 at 1000 DEG C. for 20 seconds to form a source / drain region 108 (FIG. 1A). The salicide process will now begin.

After removing the thermal oxide film 105 on the source / drain region and the gate electrode with a dilute HF solution,
i and TiN films are continuously formed at 20 nm and 50 n, respectively.
m, sputtered at 750 ° C. for 30 seconds in N 2 to silicide Ti on the source / drain and gate polysilicon electrodes,
An i2 layer 109 is formed. Thereafter, unreacted Ti on the side wall and the element isolation region is completely removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide solution (FIG. 1 (b)).

At this time, Si is the main diffusion species at the time of forming TiSi 2, and it is considered that the silicide creeps up. By annealing in N 2, nitridation proceeds from the Ti surface and silicidation proceeds at the Si interface. Therefore, climbing is suppressed. In addition, T used as a cap
iN causes the T of Si to increase due to the action considered as film stress.
The diffusion in i can be suppressed, which also
The crawling as shown in (a) and (b) can be suppressed.

It has been found that, even when the above-mentioned countermeasures are taken, there is a new failure mode in which conduction between the gate and the source / drain occurs depending on the side wall forming conditions.

This phenomenon is apt to occur when the selectivity of Si to Si is increased by a gas system such as CO addition (CHF 3 / CO). The fluorocarbon film deposited on the side wall reacts with the sputtered Ti. A conductive film is formed and conduction occurs between the gate and the source / drain (FIG. 3 (a),
(b)).

As a result of repeating experiments with several gas systems, it was found that the above-described bridging (not conduction due to the creeping up of silicide) is most unlikely to occur when etching is performed only with CHF 3. This is Ti
This is a phenomenon that becomes a problem for the first time when a silicide is attached to a source / drain or a gate, and does not cause any problem in a transistor without a silicide film attached. An essential problem of this conduction is that the metal such as Ti reacts with the above-mentioned deposition film by silicidation annealing. 4 and 5 show the results of an experiment (1 wafer, 37 chips) in which conduction between the gate and the drain was examined. The measurement pattern is shown in FIG. 6, the peripheral length of the side wall is 25 mm, and the leakage between the n + poly gate and the n + diffusion layer is examined. FIG. 4 (a) shows the relationship between the leakage current and the gate voltage of the present invention, and FIG. 5 (a) shows the conventional example (CHF3 /
It is a result showing the relationship between the leak current of CO) and the gate voltage. FIGS. 4 (b) and 5 (b) show the distribution of the gate voltage required for the leakage current to reach 10 @ -9 A. FIG. The present invention (FIG. 4 (a),
In (b)), the leak current is suppressed until VG = 7V at which the tunnel current of the gate oxide film starts to flow. However, in FIGS. 5 (a) and 5 (b), bridging occurs in some chips. It is clear that When the above bridging (defective) was analyzed by μ-AES, C and Ti were detected, and it was found that a conductive film was easily formed by a reaction between the fluorocarbon film deposited on the side wall and Ti. After the end of the selective etching, the LDD-salicide NMOSFET is completed through ordinary interlayer film formation, contact opening, wiring steps, and the like. In an embodiment of the present invention, NM
The OS has been described, but even if it is a PMOS, the CMO
It may be S. Further, it may have an LDD structure, a GDD structure, or a single drain structure.

Further, in the embodiment of the present invention, the gate electrode is made of a single layer of phosphorus-diffused poly silicon. However, even if it is formed by ion implantation, an insulating film is deposited before gate patterning to form a polycide structure. Above, the gate electrode may be patterned. Further, silicide may be selectively formed only on the source / drain.

Although the nitride film is used for the side wall spacer,
An oxide film formed by LPCVD or the like, or a composite film of an oxide film and a nitride film may be used as long as it is formed by using CHF3 gas.

In the example of TiSi 2, it has been described that there is a mode in which bridging occurs even without crawling. However, when the diffusion species is a metal, for example, Ni
The present invention can be applied to selective formation of silicide such as Si. Further, a salicide structure may be realized by selective CVD (TiCl4 gas) or the like. In addition, various modifications can be made without departing from the spirit of the present invention.

(Embodiment 2) An embodiment of the present invention will be described with reference to FIGS. In this embodiment, first, P
A p-well region (not shown) is formed on the mold substrate 201.

Next, a thermal oxide film 202 is formed to a thickness of 500 angstroms by oxidizing at 950 ° C., and then a nitride film 203 and an oxide film 204 are respectively formed to 2000 angstroms and 2500 angstroms by LPCVD.
It is deposited to a thickness of Å (FIG. 7 (a)).

Next, a resist layer is formed on a region where an element is to be formed, and the oxide film 204,
An opening 205 is formed by etching the nitride film 203. Further, the resist is removed (FIG. 7B). Next, the exposed nitride film 203 in the opening 205 is immersed in, for example, a 160 ° C. hot phosphoric acid solution and selectively side-etched.

Subsequently, using the oxide film 204 and the nitride film 203 as a mask, phosphorus is implanted into the opening by, for example, a large oblique angle of θ = 45 ° by a dose of 1 × 10 14 cm 2 to form an impurity layer 206. (FIG. 8A).

Next, after the oxide film 202 in the opening 205 is removed by wet etching or RIE, the oxide film 20 is removed.
Using the mask 4 as a mask, the silicon substrate 201 is etched to a depth of, for example, 8000 Å to form a trench. Next, a P-type impurity such as B
F2 is implanted at 2.times.10@13 cm @ -2 at 50 keV. This ion implantation is performed at an angle of θ = 0 ° or 7 °, and a P-type layer 207 is selectively formed only at the lower part of the trench (FIG. 8B). At this time, before the BF2 ion implantation, a CDE process and a heat treatment process for rounding the corner of the trench may be added.

Next, an oxide film 204 is formed using an NH 4 F solution.
Is removed by etching, and thermal oxidation is further performed at 900 ° C.
A 500 angstrom thermal oxide film is formed in the trench (FIG. 9A). Next, an oxide film 2 is formed on the entire surface by LPCVD.
08 to a thickness of 8000 angstroms (FIG. 9).
(b)).

Next, the oxide film 208 is shaved by CMP (chemical mechanical polishing). At this time, the nitride film 203 serves as a good stopper, and the substrate surface has a completely flattened shape (FIG. 10A). Next, the remaining nitride film 203 is selectively removed with hot phosphoric acid (FIG. 10B). Here, the element isolation formation is completed.

Next, a thermal oxide film (not shown) is formed on the entire surface of the substrate.
Formed to a thickness of 20 angstroms and B is 65 ke
V is implanted under the condition of 5E12 cm−2. After removing this thermal oxide film with an NH4F solution, a gate oxide film 209 is formed to a thickness of 70 Å by oxidation at 800 ° C.

Subsequently, the poly silicon 210 is LPC
Deposited to a thickness of 3500 angstroms by VD method, 8
After the phosphorus diffusion step at 50 ° C. for 60 minutes, the polysilicon 210 is patterned through a photolithography step and an RIE step to form a gate electrode 210. afterwards,
A post-oxide film 211 is formed on the top and sides of the polysilicon 210 by oxidation at 900 ° C. for 10 minutes. Subsequently, phosphorus was implanted under the conditions of 40 keV and 6.times.10@12 cm @ -2,
-Forming an ion implanted layer 212; Next, SiN is deposited to a thickness of 1000 Å by LPCVD,
The side wall 213 is formed by etching back by the RIE method. Subsequently, an oxide film having a thickness of 10 nm is formed at 850 ° C.
s is implanted at 5.times.10@15 cm @ -2 at 50 keV to form an N @ + ion implanted layer 214. FIG. Next, RTA at 1000 ° C. for 20 seconds is performed to activate the impurities. Next, this substrate was immersed in a dilute HF solution (100: 2) for 4 minutes to form a gate electrode 2
10. The oxide film on the high concentration source / drain region 214 is removed.

Next, Ti is deposited on the entire surface of the substrate to a thickness of 200 Å and annealed in N 2 at 700 ° C. for 30 seconds to form TiSi 2 215 on the gate electrode 210 and on the source / drain 214.

Next, after unreacted Ti is selectively removed with a wet solution, annealing is performed at 900 ° C. for 20 seconds,
Change iSi2 to C54 structure which is a low resistance layer (FIG. 1)
1). The shape of the oxide film 208 buried in the trench is T-shaped, with the upper part being higher than the substrate surface (FIG. 10B). This is because the center of the trench is cut off by the etching process after the formation of the element isolation region, and the final trench shape of the element isolation region has a height almost equal to the substrate surface as shown in FIG. Thereafter, as in the prior art, an insulating film is deposited, a contact hole is opened, wiring is performed, and the surface is passivated to form an nMOS.
The FET is completed.

In the above process, FIG.
Is vertically etched, but can also be processed into a reverse tapered shape of about 20 °. In this case, the finished shape of the element isolation region is as shown in FIG. After the step shown in FIG. 9A, the nitride film 203 may be selectively removed with hot phosphoric acid (FIG. 13A).

Thereafter, a nitride film having a thickness of 200 angstroms is deposited on the entire surface, an oxide film 208 is deposited, and the surface is polished by a CMP method, so that the oxide film 208 is embedded in the trench. Next, the nitride film used as the stopper is removed with hot phosphoric acid (FIG. 13B). Thereafter, the MOSFET is completed in the same manner as in the above steps. In the above embodiment, n
Although the case of MOS has been described, the present invention can be applied to CMOS by adding a resist patterning step. Although the ion implantation after the formation of the cavity is performed once in the above-described embodiment, the ion implantation may be performed at two angles. Furthermore, the source / drain structure of the transistor is
It need not be an LDD, and may be a single drain. In addition, various modifications can be used without departing from the gist of the present invention.

(Embodiment 3) An embodiment of the present invention will be described with reference to FIGS. P-type substrate 30
After the element isolation region 302 is formed on the substrate 1, channel ion implantation (P type) for controlling the threshold value is performed. Next, a gate oxide film 303 is formed to a thickness of 7 nm,
04 is deposited to a thickness of 3000 Å by LPCVD. Subsequently, in POCl 3 at 850 ° C., 6
By performing a heat treatment for 0 minutes, the polysilicon 304 is doped with phosphorus. Next, the polysilicon is patterned by RIE through a photolithography process to form a gate electrode 304.

Next, post-oxidation at 900.degree. C. for rounding the corners of the patterned polysilicon is performed at 900.degree.
For a minute in a dry atmosphere. At this time, a thermal oxide film 305 of about 150 Å is formed on the source / drain formation area and about 600 Å on the gate electrode 304 (FIG. 14A).

Next, using the gate electrode 304 and the field oxide film 302 as a mask, phosphorous is
By ion implantation at 50 keV, an N @-ion implantation layer 307 is formed.

Subsequently, a nitride film is formed by LPCVD to a thickness of 150 nm.
The gate side wall 306 is formed on the side of the gate electrode 304 by depositing and etching back.
(b)). Further, thermal oxidation is performed in DryO2 at 900 ° C. for 10 minutes to form a second post-oxide film 308. Then, arsenic is applied at 50 keV and 3E15 cm using the gate electrode 304, the gate sidewall 306, and the field oxide film 302 as a mask.
By ion implantation under the condition of -2, an N @ + ion implantation layer 309 is formed. Subsequently, RTA (Rapid) at 1000 ° C. for 20 seconds
Activation of impurities is carried out by thermal annealing. As described above, the LDD source / drain 307,3
09 is formed (FIG. 15A). Next, a salicide forming step is performed.

After forming a resist pattern 310 as shown in FIG. 15B, the oxide film 308 on the source / drain 309 is removed with a diluted HF (100: 2) solution to expose the silicon substrate. At this time, in the field edge portion, the previously formed oxide film 308 is left, and an overhang portion 311 is formed. At this time, the oxide film 30 is formed on the gate electrode 304 due to the difference in the oxidation rate between the source / drain and the polysilicon containing a large amount of phosphorus.
8 are left behind.

Subsequently, the above-mentioned oxide film 308 is completely removed by CHF 3 / CO-based RIE. At this time,
C, F, O, etc. are implanted into the gate electrode 304 by RIE, and the RIE alters the film quality of the gate polysilicon film to generate a large amount of silicide formation nuclei. Next, the resist pattern 310 is removed, and a high melting point metal, for example, a Ti thin film 312 is formed by sputtering for 20 nm.
m (FIG. 16 (a)). Subsequently, RTA is performed at 750 ° C. for 30 seconds in an Ar or N 2 atmosphere, and Ti in contact with Si is reacted to form a silicide layer 313.
To form

Next, unreacted Ti is selectively removed by, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution. At this time,
The mixed solution has no effect on the field oxide film 302 and the silicide film 313 (FIG. 16B).
As described above, a silicide layer is formed on the gate and the source / drain in a self-aligned manner. After that, the MOSFET is subjected to normal processes such as an interlayer insulating film deposition process, a reflow process, a contact opening process, and a wiring process.
Is completed. In the above embodiment, the LDD type structure of the NMOS has been described as an example, but a CMOS process may of course be used. The gate electrode is n + p for nMOS.
dual-type using p + poly for poly and pMOS
A gate type structure may be used.

Further, in this embodiment, polysilicon is used for the gate electrode, but a polycide structure such as Wsix may be used. Also, after depositing polysilicon and introducing impurities, the gate electrode can be patterned after depositing an SiO2 film. At this time, the SiO2 film and the previously formed thermal oxide film can be removed by CHF3 / CO-based RIE. Further, in this embodiment, the second post-oxidation is performed after the formation of the gate side wall 306, but this step may be omitted.

Before the deposition of the refractory metal film, an acid-based treatment may be added. In addition, reverse sputtering may be used for pretreatment of sputtering. Further, in the present embodiment, Ti is taken as the high melting point metal, but metals such as Co and Ni may be used.

After the formation of the salicide structure (FIG. 16B)
), A second RTA, for example, at 900 ° C. for 20 minutes, may further stabilize the silicide layer (C54 structure). For field edge cover mask formation,
For example, the opening of the inverted mask of the element region defining mask is 1 μm.
The logical sum of a narrowed one within about m and a thickened gate electrode forming mask of about 0.3 μm can be used. In addition, without departing from the gist of the present invention,
This can be used in various modifications.

By using the present invention, the removal of the oxide film on the gate electrode is completed and the field recedes, so that the junction leakage due to the field edge, which has been a problem in the past, can be reduced. Can be prevented (FIG. 17). In addition, an increase in the leak level due to the extension of the HF time (FIG. 18) can be prevented.

Further, since the silicide formation nuclei can be increased by REI, and the silicide film on the gate electrode becomes stable, the sheet resistance, which has conventionally been a problem, can be met even in the case of thin wires (FIG. 19). Therefore, an effect of preventing an increase in sheet resistance due to agglomeration of silicide occurring in the reflow heating step is also obtained.
As described above, according to the present invention, it is possible to simultaneously realize stable film formation (low sheet resistance) on gate polysilicon and suppression of junction leakage.

Embodiment 4 Hereinafter, a fourth embodiment will be described with reference to FIG.
This will be described with reference to FIGS.

First, after forming an n-well region 402 and a p-well region 403 on a Si substrate 401, an element isolation oxide film 404 is formed through a normal element isolation step. Further, an n-well for forming a p-MOSFET
Region 402, and pw to form an n-MOSFET
Ion implantation necessary for obtaining a target threshold voltage is performed in each of the well regions 403 to adjust the impurity concentration.

After a gate insulating film having a required film thickness is further formed, polysilicon constituting a gate electrode is deposited and RIE is performed thereon to form gate electrodes 405 and 406. Further, after LDD regions 407 and 408 are formed by ion implantation, carbon 40 is formed as a side wall material by sputtering.
9 is deposited to a thickness of 1000 Å (FIG. 2)
0 (a), (b)).

Next, a resist 412 is applied, and the side wall 40 is coated.
The resist in the portion where 9 is to be left and in the region where the wiring is to be formed are selectively removed by lithography. continue,
Oxygen plasma containing fluorine, for example, oxygen flow rate: 100 s
ccm, RF power: 300 W, pressure: 40 mT
The element isolation oxide film 404 in a region where a wiring is to be formed is slightly etched by applying RIE to the carbon film 409 and simultaneously performing over-etching (FIG. 21A and FIG. 21B). Then, the remaining resist 41
2 is treated with a mixed solution of sulfuric acid and a hydrogen peroxide solution and peeled off.

Subsequently, in order to form the n + and p + lease / drain diffusion layers 410 and 411, appropriate nuclides are selectively ion-implanted by lithography, and this is implanted, for example, in nitrogen at 1000.degree. Activated with rapid heat treatment RTA for 2 seconds. In this process, the polysilicons 405 and 406 constituting the gate electrode are also activated to their respective conductivity types, and a dual-gate-LDD-CMOS structure is achieved (FIG. 22).

Next, the surface of the oxide film on the diffusion layer and the surface of the oxide film for element isolation on which a wiring is to be formed are peeled off with an etching solution containing dilute hydrofluoric acid. It is deposited by a sputtering method to a thickness of 700 angstroms, and is subjected to, for example, RTA at 750 ° C. for 30 seconds in a nitrogen atmosphere.

Here, Ti is deposited on the diffusion layers 410 and 411, on the polysilicon gates 405 and 406, and on the element isolation oxide film 40 selectively plasma-treated to form wiring.
4 selectively reacts below the surface of the portion at a depth of about 100 to 300 angstroms to form a highly conductive substance 404 '.

In FIG. 24, after actually performing such steps,
3 shows a distribution of a chemical composition of a conductive layer containing Ti formed under an oxide film for element isolation, which is examined in a depth direction from a surface of the oxide film by an AES analysis method. From this figure, it is apparent that a conductive region containing Ti is formed at a depth of 100 to 150 Å from the surface of the oxide film.

Next, the unreacted remaining Ti and TiN are selectively peeled off with, for example, a mixed solution of sulfuric acid and hydrogen peroxide. Finally, the remaining carbon film and the carbon side walls are peeled off by an oxygen asher, and a C-MOS-LDD-salicide device having a local interconnection is achieved (FIGS. 23A and 23B).

Thereafter, if necessary, a local interconnection and the like are further formed, and based on a conventional method,
An interlayer film 413, wiring metal 414, and the like are formed to complete necessary wiring, thereby completing a semiconductor device. At this time, even if no connection is formed, the electrodes such as the source and the drain are substantially extended to the element isolation oxide film, and the contact with the electrode is performed on the element isolation oxide film, so that the source and drain regions are formed. A stable contact can be formed while reducing the size (FIG. 25).

In this embodiment, the case where the method of the present invention is applied to the LDD-CMOS-salicide process has been described. In addition, various modifications may be made without departing from the gist of the present invention. it can.

As described above, the wiring step according to the present invention can be used also as the silicidation on the source and drain diffusion layers and the gate polysilicon in the salicide step, so that the wiring step can be extremely simplified.

Further, the entire contact with the source and the drain can be formed in a self-alignment manner simultaneously with the wiring. In addition, since this contact is originally made of the same material, no contact failure occurs.

Further, the current path can be freely formed two-dimensionally by using lithography, and the resistance and the like can be reduced. Furthermore, since the source and drain diffusion layers can be substantially extended on the element isolation oxide film without using for connection,
The contact margin to this electrode can be ensured while reducing the lateral width of the source / drain diffusion layers and reducing the capacitance with the substrate.

Further, by applying the salicide process using the carbon side wall, the oxygen plasma treatment and the RIE of the carbon side wall can be used simultaneously, and the process can be shortened. The carbon film remains on the peripheral element isolation oxide film, and Ti
Completely block the reaction with. In addition, this carbon film also acts as a barrier to dilute HF acid treatment as a pre-sputtering treatment of the oxide film with Ti, and prevents the oxide film in this portion from retreating.

Further, the carbon film in this portion can be easily removed by the oxygen asher simultaneously with the side wall portion, and bridging in the salicide process can be completely suppressed by removing the side wall portion. At this time, since the conductive substance is present not at the oxide film surface but at a certain depth or later, it is not affected by the asher treatment. In addition, no new components are required, and no steps are formed due to the wiring.

In addition to this method, in addition to the element isolation oxide film,
It can be applied to other insulating films (for example, interlayer insulating films), and can also be used to connect various elements, draw out electrodes,
It has a very wide range of applications, including the formation of embedded electrodes.

(Embodiment 5) A fifth embodiment will be described below with reference to the drawings. First, an element isolation region 502 is formed on a semiconductor substrate 501, and an insulating film 503 is formed over the entire surface.
Deposits to a thickness of Angstrom. Next, a gate electrode material, for example, a polysilicon film is deposited to a thickness of 2000 Å, and a gate electrode 504 is formed by a lithography process. Next, for example, As
Is implanted under the conditions of 40 keV and 7.0E13 / cm 2 to form a first low concentration diffusion layer 505 (FIG. 26).
(a)).

Next, a nitride film is deposited on the entire surface to a thickness of 1000 angstroms by LPCVD, and a gate side wall 506 is formed by RIE. Here, if a deeper diffusion layer is required, As is set to 50 keV and 7.0E1.
Ion implantation is performed under the condition of 3 / cm @ 2 to form a second low concentration diffusion layer 507 (FIG. 26B).

Next, a resist layer 510 is formed on the entire surface,
Patterning is performed by a lithography process. Using this resist pattern 510 as a mask, As is 50 keV,
Ion implantation is performed under the condition of 5.0E15/cm@2, and a high concentration diffusion layer 508 is formed outside the gate side wall and in a region of about 0.5 μm adjacent to the gate side wall (FIG. 27A).
The impurity concentration of this high concentration diffusion layer 508 is 1 × 10 20 -1.
× 10 21 / cm 2.

Next, the resist pattern 510 is removed,
For example, Ti is deposited on the entire surface and the gate electrode 504 and the low concentration diffusion layers 505 and 507 are annealed at 750 ° C.
And the high concentration diffusion layer 508 is silicided,
Two layers 509 are formed.

Finally, unreacted Ti is selectively removed with a mixed solution of sulfuric acid and hydrogen peroxide to obtain a MOS transistor having a low-resistance silicide layer on the source, drain, and gate (FIG. 10). 27 (b)).

In the structure according to the present invention, the region of the diffusion layer serving as the source / drain is partially high in concentration, but is mostly low in concentration, so that the substrate concentration increases to suppress the short channel effect. However, an increase in junction capacitance can be prevented. In addition, the resistance of the diffusion layer increases in the low-concentration region, but the simulation shows that carriers flow from the high-concentration diffusion layer into the low-resistance silicide layer on the source / drain. It is considered that there is no decrease in driving force due to the presence of. FIG. 28 is a diagram showing a carrier flow on a wafer.
Arrows indicate the flow vector of the carrier, and almost all flow into the silicide layer. From these facts, the junction capacitance can be sufficiently reduced without causing a reduction in driving force, so that a high-speed device can be realized.

[0077]

According to the present invention, the simplification of the process and the miniaturization of the device can be realized by forming the buried wiring which serves both the silicide process and the device wiring process.

[Brief description of the drawings]

FIG. 1 is a sectional view of an element for each process for explaining a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a creeping phenomenon in a silicide process.

FIG. 3 is a diagram illustrating bridging of a gate sidewall in a silicide process.

FIG. 4 is a diagram showing a leakage current characteristic and a breakdown voltage histogram between a gate and a drain according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a conventional leakage current characteristic between a gate and a drain and a breakdown voltage histogram.

FIG. 6 is a view showing a pattern and a measurement method used for bridging measurement.

FIG. 7 is a sectional view of an element in each step for explaining a second embodiment of the present invention.

FIG. 8 is a cross-sectional view of an element in each step for explaining a second example of the present invention.

FIG. 9 is a sectional view of an element in each step for explaining the second embodiment of the present invention.

FIG. 10 is a sectional view of an element in each step for explaining the second embodiment of the present invention.

FIG. 11 is a sectional view of an element for each step for explaining the second embodiment of the present invention.

FIG. 12 is a sectional view of an element according to a step for explaining a second embodiment of the present invention.

FIG. 13 is a sectional view of an element according to a step for explaining the second embodiment of the present invention.

FIG. 14 is a sectional view of an element for explaining a third embodiment of the present invention.

FIG. 15 is a sectional view of an element in each step for explaining the third embodiment of the present invention.

FIG. 16 is a sectional view of an element in each step for explaining the third example of the present invention.

FIG. 17 is a conceptual diagram showing a reverse leakage characteristic of a junction caused by field retreat.

FIG. 18 is a diagram showing a relationship between a rare HF processing time before sputtering and a leak level.

FIG. 19 is a diagram showing a relationship between a sheet resistance on polysilicon and a line width in a conventional technique.

FIG. 20 is a sectional view of an element according to a step for explaining the fourth embodiment of the present invention.

FIG. 21 is a sectional view of an element according to a step for explaining the fourth embodiment of the present invention.

FIG. 22 is a sectional view of an element for each step for explaining the fourth embodiment of the present invention.

FIG. 23 is a sectional view of an element in each step for explaining the fourth embodiment of the present invention.

FIG. 24 is a diagram showing an AES analysis result of the transistor according to the fourth embodiment of the present invention.

FIG. 25 is a diagram showing a wiring example according to a fourth embodiment of the present invention.

FIG. 26 is a sectional view of an element in each step for explaining the fifth example of the present invention.

FIG. 27 is a sectional view of an element in each step for explaining the fifth example of the present invention.

FIG. 28 is a diagram illustrating the flow of carriers in a transistor according to a fifth embodiment of the present invention.

[Explanation of symbols]

 101, 201, 301, 401, 501 Semiconductor substrate 102, 302, 404, 502 Element isolation region 103, 209, 303 Gate oxide film 104, 210, 304, 504 Gate electrode 105, 107, 202, 204, 208, 211, 308 oxide film 106, 213, 306, 409, 506 gate sidewall 108 source / drain region 109, 215, 313, 509 TiSi2 layer 203 nitride film 205 opening 206 impurity layer 207 P-type layer 212, 307 N- ion implantation layer 214,309 N + ion implantation layer 310,412,510 Resist pattern 312 Ti thin film 402 n-well region 403 p-well region 409 carbon film 413 interlayer film 414 metal for wiring 503 insulating film 505 first low concentration diffusion layer 507 Second low Degrees diffusion layer 508 high-concentration diffusion layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 H01L 27/08 321F 5F140 21/76 29/78 301P 21/768 21/76 L 21/8238 21/302 J 27/092 29/78 (72) Inventor Tatsuya Oguro 1-term, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba R & D Center (reference) 4M104 AA01 BB01 BB21 BB25 CC05 DD04 DD23 DD26 DD37 DD46 DD64 DD79 DD84 EE05 EE09 FF13 FF14 GG09 GG10 HH05 HH12 HH14 HH20 5F004 AA09 BA04 DA00 DA16 DB03 EB02 FA08 5F032 AA35 AA44 AA45 NN77 NN01 QQ13 QQ15 QQ16 QQ19 QQ37 QQ58 QQ65 QQ70 QQ73 QQ76 RR04 RR06 SS13 TT08 VV06 XX01 XX03 XX28 XX31 XX33 5F048 AA01 AA09 AC03 BA01 BB06 BB07 BB08 BB09 BB12 BB13 BB 14 BC06 BE03 BF06 BF16 BG12 BG14 BH07 DA25 DA27 DA30 5F140 AA14 AA39 AA40 AB03 BA01 BB15 BC06 BE07 BF01 BF04 BF11 BF18 BF21 BF30 BG08 BG09 BG11 BG12 BG14 BG27 BG28 BG31 B16 BG31 B32 BG31 B32 BG31 B32 BG31 BG32 BK13 BK21 BK29 BK31 BK34 BK35 BK38 BK39 CB01 CB04 CF04

Claims (1)

[Claims] A step of forming an insulating film on a semiconductor substrate, a step of performing a plasma treatment containing at least oxygen and fluorine on the surface of the insulating film, and a step of forming a high melting point metal layer on the insulating film. Applying a heat treatment to the refractory metal.