JP2002046630A - Control device of motor-driven power steering - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the controlling accuracy of a motor current by increasing the accuracy of the analog-digital conversion value of motor current. SOLUTION: A control device of a motor-driven power steering is equipped with a current sensing circuit 60 and analog-digital converter(ADC) 43 to convert into digital value the motor current flowing actually in a motor 20 to generate a steering assist force and a current controlling means to control the current flowing in the motor in accordance with the digital value of motor current converted, wherein the current sensing circuit 60 amplifies the voltage depending upon the motor current with different amplification factors using a first 61 and a second peak hold circuit 62, and the ADC makes analog-digital conversion of the two voltages amplified VP1 and VP2. In the case the motor current is small, the current controlling means uses the analog-digital converted value of the voltage VP2 amplified with the greater amplification factor to the control of the motor current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention converts the magnitude of the electric current of an electric motor for applying an assist force to the turning operation of a steering wheel into a digital quantity, and converts the current of the electric motor according to the digital quantity. The present invention relates to a control device for an electric power steering for controlling the power steering.

[0002]

2. Description of the Related Art An electric power steering control device of this kind detects a magnitude of a motor current flowing through an electric motor and detects the detected motor current value as disclosed in, for example, Japanese Patent Publication No. 6-247324. The control of the electric motor is performed according to. Since such control is generally performed by a microcomputer that handles digital quantities, the magnitude of the motor current is converted into a digital quantity by an analog-to-digital converter (hereinafter, referred to as ADC).

[0003]

However, in the above-mentioned prior art, the LSB (Least) of the ADC is converted so that the maximum value of the motor current (the maximum value of the current that can be passed to the electric motor for control) can be converted into a digital value. Significant bi
Since t) is determined, for example, near the neutral point of the steering wheel where it is necessary to finely control the motor current, the accuracy of the digital amount is insufficient, and the steering feeling is deteriorated. There's a problem.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and one of its features is that the magnitude of a motor current flowing through an electric motor that generates a steering assist force is converted into a digital amount. Analog-digital conversion means,
A current control unit that controls the motor current in accordance with the digital amount of the converted motor current, wherein the analog-to-digital conversion unit determines that the magnitude of the motor current is LSB. First converting means for converting the magnitude of the first current into a digital quantity, and converting the magnitude of the motor current into a digital quantity of a second current having an LSB smaller than the magnitude of the first current. And a second converting means.

In this case, the first conversion means includes:
The first voltage conversion means for converting an analog voltage according to the motor current into a first voltage, and an analog-digital converter connected to the first voltage conversion means, wherein the second conversion means It is preferable that the second voltage converting means for converting an analog voltage corresponding to the current into a second voltage larger than the first voltage, and an analog-digital converter connected to the second voltage converting means. It is. The "conversion" of the first and second voltage conversion means may include a case where no conversion is performed.

According to this feature, when the motor current is small, the magnitude of the motor current whose LSB is converted into a relatively small digital amount can be used for controlling the motor current. Therefore, even when an analog-to-digital converter having a large number of bits is not used, the motor current can be more finely controlled.

Further, in order to simplify the configuration of the control device, the first voltage conversion means includes a first amplifier circuit for amplifying an analog voltage corresponding to the motor current at a first amplification factor. The second voltage converting means converts an analog voltage corresponding to the motor current to a second voltage larger than the first amplification factor.
It can also be configured to include a second amplifier circuit that amplifies at an amplification factor of.

In order to simplify the configuration of the control device and to reduce the manufacturing cost of the control device,
The first voltage conversion means and the second voltage conversion means,
It may be configured to include a resistance dividing circuit that divides an analog voltage according to the motor current.

Further, in order for the current control means, which is generally comprised of a microcomputer, to be able to handle analog-to-digital conversion values of the same number of bits, an analog-to-digital converter of the first conversion means is provided. It is preferable that the number of bits of the digital value to be handled is the same as the number of bits of the digital value handled by the analog-to-digital converter of the second conversion means.

As described above, the number of bits of the digital value handled by the analog-to-digital converter of the first conversion means and the number of bits of the digital value handled by the analog-to-digital converter of the second conversion means are the same. For example, it is possible to use a single analog-to-digital converter (one chip) which constitutes a part of the first conversion means and a part of the second conversion means, thereby further reducing the cost of the apparatus. It becomes possible.

Another feature of the present invention is that in the electric power steering control device provided with the first and second converting means, a steering state detecting means for detecting a steering state of the electric power steering; There is provided a digital quantity selecting means for setting a digital quantity used for controlling the motor current to one of the digital quantities converted by the first converting means and the second converting means based on a steering state.

According to this, particularly when steering is not performed (during steering) or when steering is performed gently, a change in the steering assist force is likely to cause deterioration of the steering feeling. Can be detected by the steering state detecting means, and in such a state, the more accurate second
Since the digital amount of the conversion means can be used for controlling the motor current, it is possible to prevent the steering feeling from deteriorating.

Further, in the control apparatus for an electric power steering having any of the above-mentioned features, the first conversion means and the second conversion means use the digital amounts converted by the first conversion means and the second conversion means. It is preferable to include an abnormal state detecting means for detecting an abnormal state of the conversion means.

According to this, it is possible to detect that the digital amount used for controlling the motor current has an abnormal value, so that an abnormal measure such as suppressing a rapid change in the steering assist force is taken. Becomes possible.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically showing a system in which a control device for an electric power steering according to the present invention is applied to a vehicle. ing. The electric power steering control device includes an electric control device 10 and a DC electric motor 20.

The electric motor 20 is driven by a turning operation of a steering wheel (steering wheel) 21 to drive the front wheels FWL, FWL.
The WR steering is provided with an assist force (assist torque) for steering, and is attached to a steering shaft 23 via a speed reduction mechanism 22 so as to be capable of transmitting torque. The rack bar 24 is driven in the axial direction according to the rotation. Then, the front wheels FWL and FWR connected to the rack bar 24 via tie rods are steered. A steering torque sensor 31 is mounted on the steering shaft 23. The steering torque sensor 31 detects a steering torque acting on the steering shaft 23 and generates an analog voltage value VTM representing the torque. A vehicle speed sensor 32, an engine speed sensor 33, and a current detection sensor (not shown) for detecting a current (motor current) flowing through the motor 20 are connected to the electric control device 10 via a current detection circuit (not shown). ing. The vehicle speed sensor 32 generates pulses at shorter intervals as the vehicle speed increases, and the engine speed sensor 33 generates pulses at shorter intervals as the engine speed increases.

Next, details of the electric control device 10 shown in FIG. 1 will be described with reference to FIG. Electric control device 1
0 is the microcomputer 40 and the motor drive circuit 5
0, current detection circuit (dynamic range defining circuit) 6
0.

The microcomputer 40 includes a CPU 41
, An input interface 42, and an ADC (analog-
Digital converter) 43 and output interface 4
4 and a memory 45 including a ROM and a RAM. The input interface 42 is connected to the CPU 41 via a bus, and is connected to the vehicle speed sensor 3.
2 and the engine speed sensor 33 are connected.

The ADC 43 is connected to the CPU 41 via a bus, and is also connected to the steering torque sensor 31 and the current detection circuit 60. The ADC 43 has an analog voltage value VTM supplied from the steering torque sensor 31, And the analog voltage values VIM1 and VIM2 corresponding to the motor current supplied from the current detection circuit 60 are converted into 10-bit digital values ADTM and AD
1 and AD2, and the same digital values ADTM, AD1 and AD2 are supplied to the CPU 41.

The output interface 44 is connected to the CPU 41 via a bus, and is connected to the motor drive circuit 5.
0, and sends a command signal to the motor drive circuit 50 based on a command from the CPU 41. The output interface 44 is connected to the relay 71, and controls opening and closing of the relay 71. The memory 45 includes a ROM and a RAM, and is connected to the CPU 41 via a bus.
In addition to storing programs (routines) to be described later, which are executed by the PU 41, and control data such as maps, data necessary for executing the programs is temporarily stored.

The motor drive circuit 50 includes four switching elements 51 to 54 each composed of a MOSFET whose gate is connected to the output interface 44, two shunt resistors 55 and 56, and a capacitor 57. One end of the resistor 55 is connected to a positive electrode of a battery 70 mounted on the vehicle via a relay 71, and the other end of the resistor 55 is connected to respective drains of the switching elements 51 and 52 and grounded via a capacitor 57. Have been.
The sources of the switching elements 51 and 52 are connected to the drains of the switching elements 53 and 54, respectively, and the sources of the switching elements 53 and 54 are grounded via a resistor 56. The switching elements 51 and 53 are connected to one side of the electric motor 20, and the switching elements 52 and 54 are connected to the other side of the electric motor 20. Note that each of the switching elements 51 to 54 has a parasitic diode whose forward direction is from each source to each drain.

From the above, it is confirmed that the ignition key switching (not shown) has been changed from "off" to "on", or the engine start of the vehicle is started based on the engine speed obtained from the engine speed sensor 33. When a predetermined condition such as confirmation is satisfied, the relay 71 is turned on by a command from the microcomputer 40.
(Closed), and the motor drive circuit 50 (i.e., the electric motor 20) is ready to receive power from the battery 70. The switching elements 51 and 54 are simultaneously turned on (“on”) when the switching elements 52 and 53 are kept off (“off”). A current in a predetermined direction flows through the motor 20, and the motor 20 rotates clockwise. The switching elements 52 and 53 are simultaneously turned on when the switching elements 51 and 54 are kept in a non-conductive state. At this time, the electric motor 20 is turned on in a direction opposite to the predetermined direction. And the motor 20 rotates to the left.

The input side of the current detection circuit 60 is connected to both ends of a resistor 56 functioning as a motor current sensor, and the output side is connected to the ADC 43. As shown in FIG. 3, the current detection circuit 60 includes a first peak hold circuit 61 and a second peak hold circuit 62. First and second peak hold circuits 61,
62 is a voltage (shunt voltage) VUD across the resistor 56
And amplifies the held analog voltage (that is, the analog amount corresponding to the magnitude of the motor current flowing through the electric motor 20) with different amplification factors, and converts the amplified analog voltages VP1 and VP2 to the ADC 43. Are output to the input channels CH1 and CH2, respectively.

More specifically, the first peak hold circuit 61 includes a comparator 61a, an operational amplifier 61b, a diode 61c, a resistor 61d having a resistance value of R1, a resistor 61e having a resistance value of R2, a capacitor 61f, and a not shown. And a resistor 61g having one end connected to the constant voltage source. The non-inverting input terminal (+ input terminal) of the comparator 61a is connected to the upstream side (point U) of the resistor 56, and the inverting input terminal (−input terminal) of the comparator 61a is connected to the downstream side of the resistor 56 (point D). The output terminal of the comparator 61a is a resistor 6
1g and the anode of the diode 61c. The cathode (point P1) of the diode 61c is
It is connected to the inverting input terminal of the comparator 61a via the resistor 61d and is grounded via the capacitor 61f. The cathode of the diode 61c is also connected to the non-inverting input terminal of the operational amplifier 61b.
The operational amplifier 61b has an output terminal connected to the inverting input terminal and functions as a voltage follower, and the output terminal is connected to the input channel CH1 of the ADC 43.

The second peak hold circuit 62 has the same configuration as the first peak hold circuit 61, and includes a comparator 62a, an operational amplifier 62b, a diode 62c,
It is composed of a resistor 62d having a resistance value of R3, a resistor 62e having a resistance value of R4, a capacitor 62f, and a resistor 62g having one end connected to a constant voltage source (not shown).
The non-inverting input terminal of the comparator 62a is connected to the upstream side of the resistor 56 (point U), and the inverting input terminal of the comparator 62a is connected to the downstream side of the resistor 56 (point D) via the resistor 62e. The output terminal of the comparator 62a is connected to the other end of the resistor 62g and the anode of the diode 62c. Cathode of diode 62c (point P2)
Is connected to the inverting input terminal of the comparator 62a via a resistor 62d and is grounded via a capacitor 62f. The cathode of the diode 62c is also connected to the non-inverting input terminal of the operational amplifier 62b. The operational amplifier 62b has an output terminal connected to the inverting input terminal and functions as a voltage follower. The output terminal is connected to the input channel CH of the ADC 43.
Connected to two. The steering torque sensor 31 is connected to the input channel CH3 of the ADC 43.

Next, the operation of the power steering control device configured as described above will be described from the current detection circuit 60. As described above, the switching elements 51 and 5
4, and the switching elements 52 and 53 are simultaneously turned on for a predetermined time. FIG. 4 shows the motor current IM and the resistance 56 when the switching elements 51 and 54 (the switching elements 52 and 53) are drive-controlled.
2 shows a waveform of the voltage VUD between both ends. The voltage VUD between both ends changes abruptly from a negative value to a positive value when the switching elements 51 and 54 are changed from “OFF” to “ON”, and thereafter gradually increases as the motor current IM increases. Further, the voltage VUD between both ends rapidly changes from a positive value to a negative value when the switching elements 51 and 54 are changed from “ON” to “OFF”, and thereafter gradually increases. For this reason,
When trying to detect the motor current IM from the both-ends voltage VUD, different end-to-end voltages VUD are obtained for the same motor current IM depending on the detection timing. Therefore,
In the above embodiment, the current detection circuit 60 employs the first and second peak hold circuits 61 and 62 so as to hold a value (that is, a peak value) in which the voltage VUD between both ends is maximum (maximum). Has become.

Here, the operation of the first peak hold circuit 61 will be described. When a current flows through the resistor 56, the potential of the non-inverting input terminal of the comparator 61a (the potential at the point U) increases. When the potential of the non-inverting input terminal of the comparator 61a becomes higher than the potential of the inverting input terminal of the comparator 61a, the comparator 61a is turned off and the diode 61c is turned on. As a result, a current flows to the capacitor 61f via the resistor 61g and the diode 61c, and the capacitor 61f is charged. As a result of this charging, when the potential of the inverting input terminal of the comparator 61a becomes higher than the potential of the non-inverting input terminal of the comparator 61a, the comparator 61a is turned on and the diode 61c is turned off, and the charging of the capacitor 61f stops. At the same time, discharging of the capacitor 61f is performed via the resistors 61d and 61e. At this time, the potential VP1 at the point P1 is represented by the following equation 1 with the peak value of the voltage VUD between both terminals being VUDM. The operational amplifier 61b converts the signal at the point P1 into low impedance and outputs the signal to the channel CH1 of the ADC 43. The values of the elements of the first peak hold circuit 61 such as the resistance values R1 and R2 and the capacitance of the capacitor 61f are the maximum value of the analog voltage VP1 (the analog voltage when the motor current becomes the maximum value that can be controlled). VP
1) is selected to be equal to the maximum value of the analog-to-digital conversion voltage of the ADC 43.

[0028]

[Equation 1] VP1 = VUDM · (1 + R1 / R2)

The second peak hold circuit 62 operates similarly to the first peak hold circuit 61. Therefore,
The potential VP2 between the non-inverting input terminal of the diode 62c and the non-inverting input terminal of the operational amplifier 62b (that is, the potential at the point P2) is represented by the following equation 2, and this potential VP2 is given to the channel CH2 of the ADC 43.

[0030]

[Equation 2] VP2 = VUDM · (1 + R3 / R4)

In the above embodiment, the resistance value R2 and the resistance value R4 are set to be equal (R2 = R4). The resistance value R3 is set to the sum (10 · R1 + 9 · R2) of a value (10R1) ten times the resistance value R1 and a value (9R2) nine times the resistance value R2. As a result, the following relationship is established between the potential VP1 and the potential VP2. Note that the resistance value R1 is set to be 12 times the resistance value R2 (R1 = 12 · R2).

[0032]

[Equation 3] VP2 = 10 · VP1

Next, the control of the motor current of the electric motor 20 will be described with reference to FIGS. 5 and 6, which show a routine (program) executed by the CPU 41 every time a predetermined time elapses. 5 and 6 constitute a current control means for controlling the motor current. FIG.
The routine is executed every elapse of a very short time as compared with the routine of FIG.

First, when the driver changes an ignition switch (not shown) from “OFF” to “ON”, the CP
U41 executes an initial routine (not shown), performs processing such as setting the value of the previous drive current value ICNTOLD to "0", which will be described later, and thereafter, at a predetermined timing from step 500 in FIG. The processing of the routine is started, and the routine proceeds to step 505. Then, in step 505, the CPU 41 converts the digital output value of the steering torque sensor 31 (hereinafter, the digital value obtained by analog-digital conversion) into the digital value (digital amount) by the AD conversion routine shown in FIG. AD value.) Take in TMAD.

Here, the A / D conversion routine of FIG. 6 which is repeatedly executed by the CPU 41 every time a predetermined time elapses will be described. When the predetermined timing comes, the CPU 41 starts the processing from step 600, and in step 610 the variable n
Is incremented by “1”. The value of the variable n is initially set to “0” in the initial routine (not shown). Next, in step 620, it is determined whether or not the value of the variable n is equal to “4”, and “Yes”
If it is determined in step 630, the value of the variable n is set to “1” in step 630, and the process proceeds to step 640. On the other hand, if “No” is determined in step 620, the process directly proceeds to step 640. Then, at step 640, the ADC
Of the 43 channels CH1 to CH3, the channel CHn specified by the variable n is AD-converted, and the routine is temporarily ended in step 695.

As described above, CH1 to CH3 are sequentially and repeatedly selected, and the analog voltage VP input to CH1 to CH3 is selected.
1, VP2 and VTM are sequentially converted to AD values. That is, in the case of the present embodiment, the first peak hold circuit 61
The output voltage VP1 of the (operational amplifier 61b) is converted into an AD value AD1, and after a predetermined time, the second peak hold circuit 62
The output voltage VP2 of the (operational amplifier 62b) is converted into an AD value AD2, and after a lapse of a predetermined time from that point, the output voltage VTM of the steering torque sensor 31 is converted into an AD value TMAD.
This conversion is repeated.

Referring again to FIG. 5, the CPU 41 determines in step 505 the AD value of the output of the steering torque sensor 31.
After the TMAD is fetched, the process proceeds to step 510, where the vehicle speed V is fetched from the output of the vehicle speed sensor 32. The vehicle speed V is calculated by a vehicle speed calculation routine (not shown) executed every time a predetermined time elapses, based on the number of pulses of the vehicle speed sensor 32 generated within an interval of the calculation routine. Next, the CPU 41 proceeds to step 51.
5, the target current value IT is changed to the steering torque value TMAD.
, The vehicle speed V, and the memory 45 shown in step 515
From the target current value map stored in the table.

Next, the CPU 41 proceeds to step 520, at which point the AD value AD1 of the output voltage VP1 of the first peak hold circuit 61, which has already been converted to the AD value, is "100".
It is determined whether it is greater than. In the present embodiment,
The maximum value of the motor current is set to 100A. Therefore, the LSB of the AD value AD1 is about 0.1 A (accurately, 100 A /
1023), the meaning of step 520 is that the motor current value is 10A (accurately, 10A / 1.
023) That is, it is determined whether or not this is the case.

As described above, the output voltage VP2 of the second peak hold circuit 62 is ten times the output voltage VP1 of the first peak hold circuit. Therefore, when the motor current value is 1
If it is 0 A or more, the second peak hold circuit 62
Since the AD value AD2 of the output voltage VP2 has overflown, the CPU 41 determines “Yes” in step 520, and proceeds to step 525, in which the value obtained by multiplying the AD value AD1 by 10 is used as the motor current value IM (digital amount). Set to. The reason for multiplying the AD value AD1 by 10 is to make the LSB of the motor current value IM used in the control described later be the same as the LSB of the AD value AD2.

On the other hand, when the motor current value is smaller than 10 A, the output voltage VP2 of the second peak hold circuit 62
The D value AD2 does not overflow. Therefore, CPU
41 determines "No" in step 520 and proceeds to step 530 to set the AD value AD2 to the motor current IM.

Next, the CPU 41 proceeds to step 535, where the previous drive current value ICNTOLD (see steps 555 and 560) calculated when the routine was last executed is 0.
It is determined whether or not the above is true. If the determination is “Yes”, at step 540, the signed motor current SG
Set the above motor current IM as it is in NIM. On the other hand, if “No” is determined in step 535, a value obtained by inverting the sign of the motor current IM, that is, −IM, is set in step 545 in the signed motor current SGNIM. The above steps 535 to 545 are based on the previous drive current value ICNTOL.
The direction of the current flowing through the motor 20 is determined based on D,
This is a step for setting the motor current value to a value with a sign.

Next, the CPU 41 determines in steps 550 and 55
Proceed to 5 to execute proportional integral control (PI control) of the motor current IM. Specifically, in step 550, the integral value IS of the difference between the target current value IT and the signed motor current SGNIM is calculated. That is, assuming that α is an arbitrary value of 0 to 1, (1-
α) · IS + α · (IT−SGNIM) is calculated, and the calculation result is set as the current integrated value IS. Next, the CPU 41 proceeds to step 555 to calculate the current drive current value ICNT. Specifically, the sum of the proportional component k1 · (IT−SGNIM) and the integral component k2 · IS is set as the current drive current value ICNT, where k1 and k2 are arbitrary positive constants. Next, in step 560, the CPU 41 sets the current drive current value ICNT as the previous drive current value ICNTOLD.

Thereafter, the CPU 41 proceeds to step 565, executes PWM control based on the drive current value ICNT obtained in step 555, and executes switching control.
4, the switching element to be turned on is determined, and the "on" time (that is, duty) is determined. Then, in step 570, a command signal is output to the determined switching element to be turned "on" so that the switching element is turned "on" for a time based on the determined duty, and the process proceeds to step 595. Ends this routine once. In the following, the CPU
41 starts the processing of this routine from step 500 every time a predetermined time elapses. As a result, the current flowing through the motor 20 is set to a value corresponding to the steering torque TM, the vehicle speed V, or the like.
Going controlled.

As described above, according to the first embodiment, the channels CH1 and CH2 of the ADC 43 are controlled by the first and second peak hold circuits 61 and 62 of the current detection circuit 60.
The analog voltage VP1 corresponding to the motor current and the analog voltage VP corresponding to the motor current IM,
Analog voltage VP2, which is 10 times the voltage of 1
And these values represent the AD value AD representing the motor current.
1 and AD2 are converted from analog to digital. That is, the actual motor current and the AD values AD1 and AD2 correspond as shown in FIG. 7, and therefore, the LSB of the AD value AD1 is 10 times the LSB of the AD value AD2.

As described above, the first peak hold circuit 61
And the ADC 43 constitute first conversion means for converting the motor current into “LSB is a digital amount of the magnitude of the first current”.
The second peak hold circuit 62 and the ADC 43 constitute a second conversion unit that converts the motor current into a “digital amount of a second current whose LSB is smaller than the first current”. The first and second peak hold circuits 6
1, 62 are analog voltages corresponding to the motor current,
It constitutes first and second voltage conversion means for respectively converting to the second voltage. Furthermore, the first and second peak hold circuits 61 and 62 constitute first and second amplifier circuits that amplify respectively at first and second amplification factors different from each other.

Then, the CPU 41 determines that the motor current is the AD value.
When it is determined that the value is smaller than the maximum value (about 10 A) that can be represented by AD2, the AD value AD2 is adopted as the AD value of the motor current IM used for the PI control of the motor current. On the other hand, when it is determined that the motor current IM is larger than the maximum value that can be represented by the AD value AD2, the AD value AD1 is adopted as the AD value of the motor current IM used for controlling the motor current.

As a result, especially when the handle 21 is near neutral, the motor current actually flowing to the electric motor 20 is small, and the motor current (motor torque) to be passed to the electric motor 20 must be delicately controlled. Even in the required operating state, the highly accurate AD value AD2 of the motor current IM can be used for controlling the motor current, so that it is possible to prevent the driving feeling from being deteriorated. In the first embodiment, the AD value AD1 and the AD value AD2 are both 10 bits.
A that can handle unnecessarily large data
Since it is not necessary to employ DC, the cost of the apparatus can be reduced. Further, in the first embodiment, the AD value AD
Since 1 and the AD value AD2 are subjected to analog-to-digital conversion by the same ADC 43, the cost can be further reduced as compared with the case where individual ADCs are employed.

Next, a description will be given of a second embodiment of the electric power steering control device according to the present invention. The second embodiment differs from the first embodiment only in that the current detection circuit 60 of the first embodiment is replaced with the current detection circuit 80 shown in FIG.
This is different from the embodiment. Therefore, only the current detection circuit 80 will be described below.

The current detection circuit 80 shown in FIG. 8 includes one peak hold circuit 81, a first amplification circuit 82,
And an amplifier circuit 83. The peak hold circuit 81 holds the peak value of the voltage across the resistor 56 and outputs the held analog voltage to the first and second amplifier circuits 82 and 83. The first and second amplifier circuits 82 and 83 amplify the input analog voltages at different amplification factors and output the amplified analog voltages VP31 and VP32 to the input channels CH1 and CH2 of the ADC, respectively. I have.

More specifically, the peak hold circuit 81
Are a comparator 81a, a diode 81b, a resistor 81c having a resistance value of R5, and a resistor 81c having a resistance value of R6.
d, a capacitor 81e, and a resistor 81f having one end connected to a constant voltage source (not shown). The non-inverting input terminal of the comparator 81a is connected to the upstream side (point U) of the resistor 56, and the inverting input terminal of the comparator 81a is connected to the downstream side (point D) of the resistor 56 via the resistor 81d. The output terminal of the comparator 81a is a resistor 8
1f and the anode of the diode 81b. The cathode of the diode 81b is connected to a resistor 81c.
Is connected to the inverting input terminal of the comparator 81a via the capacitor 81e, and is grounded via the capacitor 81e.

The first amplifier circuit 82 includes an operational amplifier 82a,
A resistor 82b having a resistance value of R7 and a resistor 82c having a resistance value of R8 are provided. Operational amplifier 82a
Is connected to the cathode (point P3) of the diode 81b of the peak hold circuit 81. The inverting input terminal of the operational amplifier 82a is grounded via a resistor 82b, and is connected to the output terminal of the operational amplifier 82a via a resistor 82c. The output terminal of the operational amplifier 82a is connected to the input channel CH1 of the ADC 43.
It is connected to the.

The second amplifier circuit 83 has the same circuit configuration as the first amplifier circuit 82, and includes an operational amplifier 83a, a resistor 83b having a resistance value of R9, and a resistor 83c having a resistance value of R10. Have been. The non-inverting input terminal of the operational amplifier 83a is connected to the cathode (point P3) of the diode 81b of the peak hold circuit 81. The inverting input terminal of the operational amplifier 83a is grounded via a resistor 83b, and is connected to the output terminal of the operational amplifier 83a via a resistor 83c. The output terminal of the operational amplifier 83a is connected to the input channel CH2 of the ADC 43.
It is connected to the.

Next, the operation of the second embodiment will be described. The peak hold circuit 81 functions in the same manner as the first and second peak hold circuits 61 and 62 of the first embodiment. Is held (amplified at a predetermined amplification rate determined by resistors 81c, 81d, etc.), and the held voltage is output to point P3. The first and second amplifying circuits 82 and 83 calculate the held voltage (potential at the point P3) VP3 by the following equations (4) and (5).
Are converted (amplified) into voltages VP31 and VP32 indicated by, and output to channels CH1 and CH2 of the ADC 43, respectively. The resistance values R5 to R8 are selected so that the maximum value of the analog voltage VP31 and the maximum value of the ADC 43 that can be converted from analog to digital are equal.

[0054]

## EQU4 ## VP31 = VP3. (1 + R8 / R7)

[0055]

VP32 = VP3 · (1 + R10 / R9)

In the second embodiment, the resistance value R7
And the resistance value R9 are set to be equal (R7 = R9). The resistance value R10 is 10 times the resistance value R8 (10 · R8) and 9 times the resistance value R7 (9 · R
7) (10 · R8 + 9 · R7).
As a result, the following relationship is established between the potential VP31 and the potential VP32.

[0057]

[Equation 6] VP32 = 10 · VP31

As a result, the first and second current detection circuits 80
The channel CH of the ADC 43 is set by the amplifier circuits 82 and 83.
1, CH2 includes an analog voltage VP31 corresponding to the motor current actually flowing through the electric motor 20 and an analog voltage corresponding to the motor current, which is ten times as large as the analog voltage VP31. A certain analog voltage VP32 is provided.

On the other hand, also in the second embodiment, the CPU 4
1 executes the routine shown in FIGS. 5 and 6 as in the first embodiment. As a result, the analog voltages VP31 and VP32 are converted from analog to digital into AD values AD1 and AD2 representing the actual motor current, respectively. That is, even in this case,
The actual motor current and the AD values AD1 and AD2 correspond as shown in FIG. Therefore, the LSB of the AD value AD1 is the AD value AD2
10 times the LSB of

As described above, the peak hold circuit 81, the first amplifier circuit 82, and the ADC 43 reduce the motor current by “LS”.
B is converted to a digital quantity of the magnitude of the first current.
The conversion means is configured, and the peak hold circuit 81, the second amplification circuit 83, and the ADC 43 convert the motor current into a "digital amount of the second current whose LSB is smaller than the first current". This constitutes a second conversion means.
Further, the first and second amplifier circuits 82 and 83 constitute part or all of first and second voltage converting means for converting an analog voltage corresponding to the motor current into first and second voltages, respectively. I have.

Then, the CPU 41 determines that the motor current is the AD value.
If determined to be smaller than the maximum value that can be represented by AD2, the motor current used for PI control of the motor current
The AD value AD2 is adopted as the IM AD value. On the other hand, when it is determined that the motor current is larger than the maximum value that can be represented by the AD value AD2, the AD value AD1 is adopted as the AD value of the motor current IM used for PI control of the motor current.

As a result, especially when the steering wheel 21 is near neutral, the motor current actually flowing to the electric motor 20 is small, and the motor current (motor torque) to be passed to the electric motor 20 must be delicately controlled. Even in the required operating state, the highly accurate AD value AD2 of the motor current IM can be used for controlling the motor current, so that it is possible to prevent the driving feeling from being deteriorated. In the second embodiment, the AD value AD1 and the AD value AD2 are both 10 bits.
A that can handle unnecessarily large data
Since it is not necessary to employ DC, the cost of the apparatus can be reduced. Further, in the second embodiment, the AD value AD
Since 1 and the AD value AD2 are subjected to analog-to-digital conversion by the same ADC 43, the cost can be further reduced as compared with the case where individual ADCs are employed. In the second embodiment, the number of operational amplifiers is three, which is smaller than the number of operational amplifiers in the first embodiment, so that the cost can be further reduced.

Next, a description will be given of a third embodiment of the electric power steering control device according to the present invention. The third embodiment differs from the first embodiment only in that the current detection circuit 60 of the first embodiment is replaced with the current detection circuit 90 shown in FIG.
This is different from the embodiment. Therefore, only the current detection circuit 90 will be described below.

The current detection circuit 90 shown in FIG. 9 has one peak hold circuit 91 and the impedance conversion circuit 9
2 and a resistance dividing circuit 93. Since the peak hold circuit 91 is the same as the peak hold circuit 81 of the second embodiment, the description is omitted. However, resistance 8
The resistance values R5 and R6 of 1c and 81d and the capacitor 81e
Is selected to be an appropriate value different from that of the peak hold circuit 81.

The impedance conversion circuit 92 comprises an operational amplifier 92a. The non-inverting input terminal of the operational amplifier 92a is connected to the cathode (point P4) of the diode 81b of the peak hold circuit 81, and the inverting input terminal is connected to its output terminal. Accordingly, the impedance conversion circuit 92 converts the signal at the point P4 into a low impedance and outputs the signal from the output terminal of the operational amplifier amplifier 92a.

The resistance dividing circuit 93 includes a resistor 93a having a resistance value of R11 and a resistor 93b having a resistance value of R12. One end of the resistor 93a is connected to the output terminal of the operational amplifier 92a, and the other end of the resistor 93a is connected to the resistor 93b.
Is connected to one end. The other end of the resistor 93b is grounded. Then, the one end of the resistor 93a (ie,
The point P5), which is the output terminal of the operational amplifier 92a, is
3, the other end of the resistor 93a (the connection point P6 between the resistor 93a and the resistor 93b) is connected to the input channel CH2.
It is connected to the input channel CH1 of C43.

Next, the operation of the third embodiment will be described. The peak hold circuit 91 functions similarly to the peak hold circuit 81 of the second embodiment, and holds the peak value of the voltage VUD across the resistor 56. Output to point P4. Then, the impedance conversion circuit 92 converts and outputs the impedance of the signal at the point P4. Resistance divider circuit 93
Converts the potential VP4 at the point P4 into voltages VP5 and VP6 expressed by the following equations 7 and 8, and applies the voltages to the channels CH2 and CH1, respectively. The resistance values R5, R6, and the like are selected such that the maximum value of the analog voltage VP6 is equal to the maximum value of the analog-to-digital conversion voltage of the ADC 43.

[0068]

[Equation 7] VP5 = VP4

[0069]

VP6 = VP4 · R12 / (R11 + R12) = VP5
・ R12 / (R11 + R12)

In the third embodiment, the resistance value R1
1 is set to be nine times the resistance value R12 (R11 = 9 · R12). As a result, the following equation 9 is established between the potential VP5 and the potential VP6.

[0071]

[Equation 9] VP5 = 10 · VP6

As a result, the resistance division circuit 93 of the current detection circuit 90 supplies the channels CH1 and CH2 of the ADC 43 to the channels CH1 and CH2.
An analog voltage VP6 corresponding to the motor current actually flowing through the electric motor 20 and an analog voltage VP5 which is an analog voltage corresponding to the motor current and having a magnitude ten times the analog voltage VP6 are provided. Can be

On the other hand, also in the third embodiment, the CPU 4
1 executes the routine shown in FIGS. 5 and 6 as in the first embodiment. As a result, the analog voltages VP5 and VP6 are converted from analog to digital into AD values AD2 and AD1, respectively, representing the actual motor current. That is, also in this case, the actual motor current and the AD values AD1 and AD2 correspond as shown in FIG. Therefore, the LSB of the AD value AD1 is the LSB of the AD value AD2.
It is 10 times of SB.

As described above, the peak hold circuit 91, the impedance conversion circuit 92, the resistance division circuit 93, and A
The DC 43 constitutes first conversion means for converting the motor current into “LSB is a digital amount of the magnitude of the first current”, and at the same time, they convert the motor current into “LSB is smaller than the magnitude of the first current”. It also constitutes a second conversion means for converting into a "digital amount having a small second current magnitude". The resistance dividing circuit 93 converts the analog voltage corresponding to the motor current into the first
It constitutes all or a part of the first and second voltage converting means for respectively converting to the second voltage.

Then, the CPU 41 determines that the motor current is the AD value.
If determined to be smaller than the maximum value that can be represented by AD2, the motor current used for PI control of the motor current
The AD value AD2 is adopted as the IM AD value. On the other hand, when it is determined that the motor current is larger than the maximum value that can be represented by the AD value AD2, the AD value AD1 is adopted as the AD value of the motor current IM used for PI control of the motor current.

As a result, especially when the handle 21 is near neutral, the motor current actually flowing to the electric motor 20 is small, and the motor current (motor torque) to be passed to the electric motor 20 must be delicately controlled. Even in the required operating state, the highly accurate AD value AD2 of the motor current IM can be used for controlling the motor current, so that it is possible to prevent the driving feeling from being deteriorated. In the third embodiment, the AD value AD1 and the AD value AD2 are both 10 bits.
A that can handle unnecessarily large data
Since it is not necessary to employ DC, the cost of the apparatus can be reduced. Further, in the third embodiment, the AD value AD
Since 1 and the AD value AD2 are converted from analog to digital by the same ADC 43, the cost can be further reduced as compared with the case where individual ADCs are employed. In the third embodiment, the number of operational amplifiers is as small as one, and the inexpensive resistance dividing circuit 93 is employed, so that the cost can be further reduced.

Next, a description will be given of a fourth embodiment of the electric power steering control apparatus according to the present invention. In the fourth embodiment, the magnitude of the motor current is represented by an AD value AD1 with LSB being the magnitude of the first current, and an AD value AD2 with the magnitude of the second current being LSB smaller than the magnitude of the first current. This is the same as the first embodiment in that it is converted into On the other hand, the fourth embodiment is employed for controlling the motor current when the AD value AD2 has a small absolute value of the steering angular velocity STω (when the steering angle ST is stable near a predetermined value), and is employed. AD value AD2 is configured to be the AD value of the motor current within a predetermined range around the motor current IK indicated by the AD value AD1 when the absolute value of the steering angular velocity STω is small, This is different from the first embodiment. Therefore, hereinafter, the description will be given focusing on the difference with reference to FIGS. 10 to 15, but the same components as those in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted.

In the fourth embodiment, as shown in FIG. 10, a steering angle sensor 34 for detecting the steering angle of the steering wheel 21 is added. The steering angle sensor 34 is mounted on the steering shaft 23 and, as shown in FIG. 11, is connected to an input interface 42 of the electric control device 10 ′, and outputs the detected steering angle to the CPU 41 via the interface 42. Is supplied in accordance with the signal ST (steering angle ST).

The electric control device 10 'differs from the electric control device 10 of the first embodiment only in that the microcomputer 40 and the current detection circuit 60 are replaced with a microcomputer 40' and a current detection circuit 100, respectively. It is different from 10. The microcomputer 40 ′ includes a CPU 41, an input interface 42, and an ADC 4 which are components of the microcomputer 40.
3 and an output interface 44.
A digital-analog converter 46 (hereinafter referred to as DAC 46) is connected to U41 via a bus and connected to the current detection circuit 100.

As shown in detail in FIG. 12, the current detection circuit 100 includes a first peak hold circuit 101, a second peak hold circuit 102, and a bias voltage circuit 103. The first peak hold circuit 101 includes a peak value VUD of a voltage VUD across the resistor 56 having a resistance value of Rx.
While holding M, the held analog voltage (that is, an analog amount corresponding to the magnitude of the motor current flowing through the electric motor 20) VUDM is amplified at a predetermined amplification factor (first amplification factor), and the amplified analog voltage is amplified. Voltage VP10 to ADC4
3 is output to the input channel CH1.

More specifically, the first peak hold circuit 101 includes a comparator 101a and an operational amplifier 1
01b, a diode 101c, a resistor 101d having a resistance value of R21, a resistor 101e having a resistance value of R22, a capacitor 101f, and a resistor 101g having one end connected to a constant voltage source (not shown). These connection relationships are based on the first peak hold circuit 61 of the first embodiment.
Is the same as the connection relationship of the corresponding elements. Therefore, the first
The operation of the peak hold circuit 101 is the same as that of the first peak hold circuit 61. The potential of the output side (cathode side) of the diode 101c shown as a point P10 in FIG. 12, that is, the output of the operational amplifier 101b functioning as a voltage follower. Voltage VP10 is represented by the following equation (10).

[0082]

VP10 = VUDM · (1 + R21 / R22)

The second peak hold circuit 102 includes a resistor 5
6 holds the peak value of the voltage (VUD-Voff) obtained by offsetting the voltage VUD at both ends by a predetermined offset voltage Voff, and holds the held analog voltage (VUDM-Voff).
At a second amplification factor larger than the first amplification factor of the first peak hold circuit 101, and the amplified voltage VP20 is
The signal is output to the input channel CH2 of the DC 43.

More specifically, the second peak hold circuit 102 includes a comparator 102a and an operational amplifier 102
b, diode 102c, resistor 1 having a resistance value of R23
02d, a resistor 102e having a resistance value of R24, a capacitor 102f, a resistor 102g having one end connected to a constant voltage source (not shown), and a resistor 102h having a resistance value of Rd. These connection relationships are the same as those of the first embodiment except that the non-inverting input terminal of the comparator 102a is connected to the upstream side (point U) of the resistor 56 via the resistor 102h.
This is the same as the connection relationship of the corresponding elements of the second peak hold circuit 62 of the embodiment.

The bias voltage circuit 103 is for applying the bias voltage Voff to the comparator 102a, and includes three resistors 103a, 103b,
103c. These resistors 103a,
The resistance values of 103b and 103c are values Ra and R, respectively.
b and Rc. One end of the resistor 103a is connected to the DAC 46.
, And the other end of the resistor 103a is connected to one end of the resistor 103b. Resistance 103b
Is grounded. One end of the resistor 103c is a resistor 1
The other end of the resistor 103c is connected between the resistor 102h and the non-inverting input terminal of the comparator 102a.

The operation of the second peak hold circuit 102 is basically the same as that of the second peak hold circuit 62, except that the bias voltage circuit 103 applies a bias voltage Voff to a non-inverting input terminal of a comparator 102a which is an operational amplifier. Is applied, the point P2 in FIG.
The potential on the output side of the diode 102c shown as 0, that is, the operational amplifier 10 functioning as a voltage follower
The output voltage VP20 of 2b is represented by the following equation (11).

[0087]

VP20 = (VUDM + Voff) · (1 + R23 / R24)

When the voltage of the output channel CH of the DAC 46 is VDA, the bias voltage Voff is expressed by the following equation (12).
Is represented by In this embodiment, the resistance value Rx
Is 2.5 mΩ, resistance Rc is 100 kΩ, and resistance Rd is 5 k
Ω. Therefore, the resistance value Rx is sufficiently smaller than the resistance values Rc and Rd, and the equation 12 is derived based on this. From this equation 12, the output channel CH of the DAC 46 is obtained.
It can be understood that the bias voltage Voff can be changed by changing the voltage VDA.

[0089]

Voff = (Rb / (Ra + Rb)) · VDA · (Rd
/ (Rc + Rd))

In this embodiment, the resistance value Ra is 1200Ω,
Since the resistance value Rb is set to 300Ω, when a specific numerical value is substituted into the above equation 12, the same equation 12 is rewritten into the following equation 13.

[0091]

[Expression 13] Voff = VDA / 105

Further, the resistance value R22 and the resistance value R24 are set to be equal, and the resistance value R23 is the sum of the value of 10 times the resistance value R21 and the value of 9 times the resistance value R22 (10 · R21 + 9 ·
R22). As a result, the potential VP10 and the potential
The following equation (14) is established with the VP20.

[0093]

VP20 = 10 · VP10 + 10 · Voff (1 + R21 / R22)

On the other hand, in this embodiment, R21 = 5.5 k
Ω, R22 = R24 = 5 kΩ, and R23 = 100 kΩ. By substituting these numerical values into Equations 10 and 11, they can be rewritten as Equations 15 and 16, respectively.

[0095]

[Equation 15] VP10 = 2.1 · VUDM

[0096]

[Equation 16] VP20 = 21 · (VUDM + Voff)

On the other hand, from Expression 13 and Expression 14 (or Expression 13, Expression 15, and Expression 16), Expression 17 is obtained.

[0098]

[Equation 17] VP20 = 10 · VP10 + 21 · Voff = 10 · VP10 + (21
/ 100) · VDA

As described above, the voltages VP10 and VP20 are set to the same ADC4
When converted to AD values AD1 and AD2 at 3, the AD value AD2 becomes L
It is understood that SB is 1/10 of the LSB of the AD value AD1, and is a value offset by 0.21 · VDA. FIG.
The relationship between such AD values AD1 and AD2 is shown.

Next, the operation of the fourth embodiment will be described. The CPU 41 of the fourth embodiment is similar to that of FIGS.
And the program (routine) shown in the flowchart in FIG. 14 is executed. The routine shown in FIG. 13 replaces the routine of FIG. 5, and the same steps as those in FIG. 5 are denoted by the same reference numerals. The routine shown in FIG.
This is a time interruption routine that is executed by the CPU 41 every time a very short time elapses compared to the routines of FIGS.

The CPU 41 starts the execution of the routine shown in FIG. 13 every time a predetermined time elapses from step 1300, proceeds to step 505, takes in the AD value TMAD of the output of the steering torque sensor 31, and proceeds to step 510. The vehicle speed V is obtained based on the output of the vehicle speed sensor 32. Next, the CPU 41 proceeds to step 515, where the target current value I
T is determined from the steering torque value TMAD, the vehicle speed V, and the target current value map stored in the memory 45 shown in step 515.

Next, the CPU 41 proceeds to step 1305 to determine whether or not the value of the AD value selection flag F is "1". The value of the AD value selection flag F is set to “0” in an initial routine (not shown) that is executed at the time of starting when the ignition switch is changed from “off” to “on”. It is changed by execution of the time interrupt routine shown in FIG.

Here, the routine shown in FIG. 14 will be described. The CPU 41 determines that the absolute value of the steering angular velocity STω is smaller than the predetermined value K for a predetermined reference time or more by the routine shown in FIG. When the steering is held or the steering is relatively slow)
The value of the value selection flag F is changed to “1”, and in other cases, the value of the flag F is changed to “0”. Further, an offset voltage Voff corresponding to a value obtained by subtracting a predetermined current value from the motor current value when the value of the AD value selection flag F is changed to “1”.
Through the DAC 46 and the bias voltage circuit 103.
This is applied to the comparator 102a of the peak hold circuit 102.

More specifically, the CPU 41 starts processing from step 1400 at a predetermined timing, proceeds to step 1405, and changes the current steering angle ST to the previous steering angle.
The steering angular velocity STω is obtained by subtracting STOLD (the steering angle ST a predetermined time before the execution interval time of this routine). Next, the CPU 41 proceeds to step 1410, and determines whether or not the absolute value of the steering angular velocity STω is smaller than a positive predetermined value K.

Now, assuming that the steering is being performed and the absolute value of the steering angular velocity STω is larger than the predetermined value K,
41 is determined as “No” in step 1410, and proceeds to step 1415. In step 1415, the counter CN
The value of T is cleared to "0", and the routine proceeds to step 1420, where A
The value of the D value selection flag F is set to “0”. Then C
The PU 41 proceeds to step 1425 to store the current steering angle ST as the previous steering angle STOLD for calculating the steering angular velocity STω in the next execution of the present routine, and proceeds to step 1495 to terminate the present routine once. Thus, when the steering is being performed and the absolute value of the steering angular velocity STω is larger than the predetermined value K, the value of the AD value selection flag F is set to “0”.

Next, a case will be described in which the state is shifted from a state during steering to a state in which steering is maintained or steering is performed slowly. The CPU 41 executes Step 1 at a predetermined timing.
Step 410 is executed. In this case, since the absolute value of the steering angular velocity STω is smaller than the predetermined value K, “Yes” is determined in step 1410 and the process proceeds to step 1430 to increase the value of the counter CNT by “1”. I do. Next, the CPU 41 proceeds to step 1435, in which the value of the counter CNT is
It is determined whether it is greater than K (corresponding to the predetermined reference time). At this time, the value of the counter CNT is smaller than the predetermined value CNTK since it is immediately after the value of the counter CNT has been set to “0” in the previous step 1415. Accordingly, the CPU 41 determines in step 1435 that “N
o ", the flow advances to step 1420 to set the value of the AD value selection flag F to" 0 ", and the flow advances to step 1425 to store the current steering angle ST as the previous steering angle STOLD. To end this routine once.

If such an operation state continues, step 1430 is repeatedly executed, so that the value of the counter CNT gradually increases. As a result, when the predetermined time has elapsed, the value of the counter CNT becomes larger than the predetermined value CNTK. Therefore, the CPU 41 determines “Yes” in step 1435 and proceeds to step 1440.

The CPU 41 determines in this step 1440
It is determined whether the value of the AD value AD1 is greater than “50”.
At this time, if the value of the AD value AD1 is smaller than “50”, C
The PU 41 determines “No” in the step 1440, executes the steps 1420 and 1425, and thereafter ends the present routine in a step 1495.

On the other hand, when the value of the AD value AD1 is larger than “50” at the time of execution of step 1440, the CP
U41 determines “Yes” in the same step 1440,
In step 1445, the DA value VDA output from the channel CH of the DAC 46 is set to a value k · (AD1-50) (mV) in order to change the offset voltage Voff. In addition, according to each of the above-described resistance values, the value k is 26.25.

Here, the DA value VDA (= 26.25 · (AD1−5
0)) will be explained. Now, it is assumed that the motor current value at the time when the value of the counter CNT becomes larger than the predetermined value CNTK is IK (A), and the input voltage of the comparator 102a is offset by a value corresponding to the value IK-5 (A). Considering this, the potential Voff of the non-inverting input terminal of the comparator 102a may be determined as in the following Expression 18.

[0111]

Voff (mV) = Rx · (IK−5) = 2.5 (m
Ω) ・ (IK-5) (A)

On the other hand, since the ADC 43 has 10 bits as described in the first embodiment, the current value IK and the AD value AD
The following equation (19) holds between 1:

[0113]

[Equation 19] IK (A) = AD1 · (100/1023) ≒ AD1 / 10

Therefore, Equations (18), (19) and (13)
Gives the following equation (20).

[0115]

VDA = 26.25 (AD1-50) (mV)

From the above, the above steps 1445,
By executing 1450, the offset voltage is applied to the comparator 102a by a value corresponding to the value IK-5 (A). Next, the CPU 41 proceeds to step 1455, sets the value of the AD value selection flag F to “1”, executes step 1425, and then proceeds to step 1495 to temporarily end this routine. As a result, as shown in FIG.
Execution of the AD conversion interrupt routine causes AD value AD2 to change to AD value AD1.
A value having an LSB that is 1/10 of the LSB of
AD conversion is performed as a value offset by -5 (A) (see FIG. 15).

Referring again to FIG. 13, at step 1305, the CPU 41 determines whether or not the value of the AD value selection flag F determined by the routine of FIG. 14 is "1".
If the value of the flag F is "1", the process proceeds to step 1310, where the AD value AD2 is changed to the same AD value AD2 and AD
The value AD1 and a function f storing the relationship shown in FIG. 15 are converted into a motor current value, and the converted value f (AD2) is stored as a motor current IM used for controlling the motor current. If the value of the AD value selection flag F is not "1" at the time of execution of step 1305, the CPU 41 proceeds to step 1315, multiplies the AD value AD1 by 10, and stores this value as the motor current value IM. To multiply the AD value AD1 by 10 is
This is to make the LSB of the motor current value IM equal to the LSB of the AD value AD2. Thereafter, the CPU 41 executes the processing of steps 535 to 570 described in the first embodiment, and ends this routine once in step 1395. Thus, the motor current is controlled according to the AD value AD1 or AD value AD2.

As described above, according to the fourth embodiment, when the state where the absolute value of the steering angular velocity STω is smaller than the predetermined value K has continued for a predetermined time or more, the motor current value at that time
A value smaller than IK by a predetermined current (5 (A) in this example)
Offset voltage Voff corresponding to the comparator 102a
Is applied to And AD value AD2 with small LSB and high accuracy
Are used to control the motor current.

As a result, in particular, since the steering wheel 21 is gently operated to rotate and the steering torque tends to fluctuate, the motor current (motor torque, assist force) to be passed must be delicately controlled. The highly accurate AD value AD2 can be used for controlling the motor current. Accordingly, it is possible to prevent the driving feeling from deteriorating in such an operating state. In addition, the fourth
Also in the embodiment, the AD value AD1 and the AD value AD2 are both 10
Since there is no need to employ an ADC that can handle data larger than necessary, the cost of the device can be reduced.

In the fourth embodiment, the steering angle sensor 34 and steps 1405 and 1425 in FIG.
Constitutes a steering state detecting means, and corresponds to step 141 in FIG.
0 to 1420 and steps 1430 to 1455, and FIG.
Steps 1305 to 1315 of 3 correspond to the AD value AD1 and the AD value A
This is a digital amount selecting means for selecting and determining any one of D2 as a value used for controlling the motor current.

Further, in the fourth embodiment, the steering angular velocity STω is detected by using the steering angle sensor 34. However, the motor rotational angular velocity is obtained from the differential value of the motor current IM or the motor rotational angle sensor and the like, and the steering angular velocity STω May be obtained. In addition, as the value indicating the steering state detected by the steering state detecting means, in addition to the steering angular velocity STω, a steering angle ST, a time differential value of the steering angular velocity STω, and a value determined from the steering angular velocity STω and the steering angle ST ( For example, the steering angular velocity
The value may be larger as STω is smaller and larger as steering angle ST is smaller.

Next, a description will be given of a fifth embodiment of the electric power steering control device according to the present invention. In the fifth embodiment, it is determined whether or not the values of the AD values AD1 and AD2 have become abnormal. When the values are determined to be abnormal, the motor current control abnormality processing is performed. 5 and FIG. 6 executed by each CPU 41 of the third embodiment, and only the first to first routines shown in FIG. 16 inserted into the routine of FIG. 5 are executed. This is different from the third embodiment. Therefore, an explanation will be given below mainly with reference to FIG.

First, the description starts with the case where the AD values AD1 and AD2 are normal. As described above, the CPU 41
Starts the execution of the routine shown in FIG. 5 from step 500 every time a predetermined time elapses.
After executing 515 to calculate the target current value IT, the process proceeds to step 1605 shown in FIG.

At step 1605, the CPU 41 determines whether or not the value of the abnormality flag FIJO is "0". The value of the abnormality flag FIJO is set to “0” in an initial routine (not shown). Therefore, the CPU 41 determines in step 1605 for the first time after the initial routine.
Is executed, "Yes" is determined in step 1605, and the process proceeds to step 1610, where
The value of the AD value AD1 is multiplied by 10 and stored as the AD value AD10. This is to make the LSB of the AD value AD1 coincide with the LSB of the AD value AD2.

Next, the CPU 41 determines in step 1615
It is determined whether or not the AD value AD10 is larger than the judgment value K1 and the AD value AD2 is smaller than the judgment value K2 which is smaller than the judgment value K1. The difference between the determination value K1 and the determination value K2 is set to a value that cannot be a difference between the normal AD values AD10 and AD2. At this stage, since the AD values AD10 and AD2 are both normal, the above condition is not satisfied. Therefore, CP
U41 determines "No" in step 1615, and proceeds to step 1620.

The CPU 41 determines in step 1620 that the AD value
It is determined whether AD10 is smaller than the judgment value K2 and whether the AD value AD2 is larger than the judgment value K1. This condition is also
If the values AD10 and AD2 are normal values, the condition is not satisfied. Therefore, the CPU 41 determines in step 1620 that “N
o ", the routine proceeds to step 520 and the subsequent steps in FIG. 5, and normal motor current control is performed.

Next, the case where the AD value AD1 or AD value AD2 becomes an abnormal value will be described.
Since either condition of 615 or step 1620 is satisfied, the CPU 41 proceeds to step 1615 or step 1
620, the determination is “Yes” and the process proceeds to step 1625, where the abnormality flag FI
Set the value of JO to "1".

Next, CPU 41 executes steps 1630 to 1640 for abnormality processing. That is, CPU4
1 subtracts a predetermined positive value β from the current (current) drive current ICNT in step 1630 and sets this as a new drive current value ICNT. In the subsequent step 1635, the drive current value ICNT is “ It is determined whether or not the value is smaller than a breaking current value I1 close to “0”. At the present stage, that is, at the stage where the positive value β is first reduced in step 1630, the driving current value ICNT is usually larger than the cutoff current value I1, so the CPU 41 determines “No” in step 1635, The process proceeds to Step 565 of Step 5 and subsequent steps. Thereby, a current corresponding to the drive current value ICNT from which the positive value β has been reduced is supplied to the motor 22.

Thereafter, the CPU 41 executes step 1605 after a predetermined time has elapsed. At this time, the abnormal flag
Since the value of FIJO is “1”, the CPU 41 determines “No” in step 1605 and proceeds directly to step 1630. Then, in step 1630, a predetermined positive value β is subtracted from the drive current ICNT at that time, and this is set as a new drive current value ICNT. Next, the CPU 41 executes the above-mentioned step 1635, and the drive current value ICNT is changed to the cutoff current value I1.
If the drive current value ICNT is smaller than the cutoff current value I1, the process proceeds to step 565 and the subsequent steps.
After setting the value of the drive current value ICNT to “0” at 0, the process proceeds to step 565 and thereafter.

Thus, the drive current value ICNT is changed when the value of the abnormality flag FIJO changes from “0” to “1” (ie,
The value is reduced by a positive value β every time a predetermined time elapses from the value of AD values AD1 and AD2 when abnormality is recognized), and becomes “0” after the value becomes smaller than the cutoff current value I1.

As described above, according to the fifth embodiment, it is determined whether or not the AD values AD1 and AD2 are abnormal by using the AD values AD1 and AD2. Current value IC
NT is gradually reduced toward “0”, and the assist force is gradually reduced. Therefore, even if the AD values AD1 and AD2 become abnormal, it is possible to avoid a sudden change in the assist force.

Note that the above steps 1605 to 1620
Constitutes an abnormal state detecting means for detecting an abnormal state of the first converting means and the second converting means by using both digital values of the AD values AD1 and AD2, and in steps 1630 to 1640.
Constitutes abnormality processing means for performing abnormality processing when an abnormal state is detected.

The fifth embodiment is also applicable to the fourth embodiment. In this case, between step 1610 and step 1615 in FIG.
Is converted to a value having the same scale as the AD value AD1 by the function f. Further, after the CPU 41 determines “No” in the step 1635 or executes the step 1640, the process proceeds to the step 565 in FIG.
If "No" is determined in step 1620,
It is configured to proceed to step 1305 of No. 3.

As described above, according to each of the embodiments of the present invention, the AD value of the motor current with high accuracy is limited to a limited bi value.
Obtained by t number of ADCs, the same AD value can be used for motor current control as needed. As a result, it is possible to prevent the steering feeling from deteriorating.

Note that the present invention is not limited to the above embodiment, and various modifications can be adopted within the scope of the present invention. For example, in each of the above embodiments, there is one ADC, but as shown in FIG.
A plurality of ADCs are employed (see ADCs 43a and 43b), and the input channels CH1 and CH2 of the ADC 43 are set to A.
DC 43a, 43b, respectively, and two output terminals of the current detection circuits 60, 80, 90, 100 are ADC
It may be configured to connect to each of 43a and 43b. In the above embodiments, the motor current is controlled by the PI control. However, the motor current can be controlled by the PID control, the P control, or the like. As for the sign of the motor current IM, the voltage across the electric motor 20 may be detected, and the direction of the motor current IM may be determined from the detected voltage across the motor. Furthermore, in each of the above embodiments, only the two conversion means, the first and second conversion means, are employed, but the LSB of the digital amount obtained by the first and second conversion means may be different if necessary. Third conversion means for obtaining the AD value of the motor current having the LSB, or more conversion means may be employed.

[Brief description of the drawings]

FIG. 1 is a schematic system diagram in which a control device for an electric power steering according to a first embodiment of the present invention is applied to a vehicle.

FIG. 2 is an electric circuit diagram of the electric power steering control device shown in FIG.

FIG. 3 is a schematic diagram of the current detection circuit shown in FIG.

FIG. 4 is a time chart showing waveforms of a switching element, a motor current, and a shunt voltage.

FIG. 5 is a flowchart showing a program executed by a CPU shown in FIG. 2;

FIG. 6 is a flowchart showing a program executed by a CPU shown in FIG. 2;

FIG. 7 is a diagram showing a relationship between a motor current and an AD value.

FIG. 8 is a schematic diagram of a current detection circuit according to a second embodiment of the present invention.

FIG. 9 is a schematic diagram of a current detection circuit according to a third embodiment of the present invention.

FIG. 10 is a schematic system diagram in which a control device for an electric power steering according to a fourth embodiment of the present invention is applied to a vehicle.

11 is an electric circuit diagram of the electric power steering control device shown in FIG.

12 is a schematic diagram of the current detection circuit shown in FIG.

FIG. 13 is a flowchart showing a program executed by the CPU shown in FIG. 11;

FIG. 14 is a flowchart showing a program executed by the CPU shown in FIG. 11;

FIG. 15 is a diagram showing a relationship between a motor current and an AD value.

FIG. 16 is a flowchart illustrating a program executed by a CPU according to a fifth embodiment of the present invention.

FIG. 17 is a schematic diagram showing a connection relationship between a current detection circuit and an analog-digital converter according to a modification of each embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Electric control apparatus, 20 ... DC electric motor, 21 ... Handle, 22 ... Deceleration mechanism, 23 ... Steering axis, 24 ... Rack bar, 31 ... Steering torque sensor, 32 ... Vehicle speed sensor, 4
0 ... microcomputer, 41 ... CPU, 42 ... input interface, 43 ... analog-digital converter (ADC), 44 ... output interface, 45 ... memory, 50 ... motor drive circuit, 51-54 ... switching element, 55 ... resistance, 56 ... resistance (shunt resistance), 6
0: current detection circuit, 61: first peak hold circuit, 6
2. Second peak hold circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) B62D 119: 00 B62D 119: 00 127: 00 127: 00 (72) Inventor Katsumi Tsuchida Toyota-cho Toyota-cho, Aichi Prefecture No. 1 Toyota Motor Corporation F-term (reference) 3D032 CC08 DA15 DA23 DA49 DA64 DD17 EA01 EC23 GG01 3D033 CA03 CA13 CA16 CA20 CA21 CA31 5H571 AA03 BB09 CC02 EE02 EE03 GG04 GG07 GG08 HA09 HC01 HD01 JJ03 JJ17 JJ16 JJ16 JJ16 JJ16

Claims (7)

[Claims] An analog-to-digital converter for converting a magnitude of a motor current flowing through an electric motor for generating a steering assist force into a digital amount; and controlling the motor current in accordance with the digital amount of the converted motor current. An analog-to-digital conversion means, wherein the analog-to-digital conversion means converts the magnitude of the motor current into a digital amount of a magnitude of a first current by an LSB. And an electric power steering device comprising: a second converting means for converting the magnitude of the motor current into a digital amount having a magnitude of a second current whose LSB is smaller than the magnitude of the first current. Control device. 2. The electric power steering control device according to claim 1, wherein the first converting means is configured to convert an analog voltage corresponding to the motor current into a first voltage. 1
An analog-to-digital converter connected to voltage conversion means, wherein the second conversion means converts an analog voltage corresponding to the motor current to a second voltage larger than the first voltage. A controller for an electric power steering, comprising: a converter and an analog-digital converter connected to the second voltage converter. 3. The electric power steering control device according to claim 2, wherein said first voltage conversion means includes a first amplifier circuit for amplifying an analog voltage corresponding to said motor current at a first amplification factor. Wherein the second voltage converting means includes a second amplifier circuit for amplifying an analog voltage corresponding to the motor current at a second amplification factor larger than the first amplification factor. Steering control device. 4. The control device for an electric power steering according to claim 2, wherein the first voltage conversion means and the second voltage conversion means include:
A control device for an electric power steering, comprising a resistance dividing circuit for dividing an analog voltage corresponding to the motor current. 5. The electric power steering control device according to claim 2, wherein the number of bits of a digital value handled by an analog-to-digital converter of the first conversion means and the second conversion. The electric power steering control device, wherein the number of bits of the digital value handled by the analog-to-digital converter is the same. 6. The electric power steering control device according to claim 1, wherein: a steering state detecting means for detecting a steering state of the electric power steering; and controlling the motor current based on the detected steering state. And a digital quantity selecting means for setting the digital quantity used in the first and second conversion means to be one of the digital quantities converted by the first and second conversion means. 7. The electric power steering control device according to claim 1, wherein the control unit uses the two digital quantities converted by the first conversion unit and the second conversion unit. A control device for an electric power steering, comprising an abnormal state detecting means for detecting an abnormal state of the first converting means and the second converting means.