JP2002043524A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in the conventional semiconductor integrated circuit where in order to perform high precise measurement with a built-in ring oscillator, its circuit scale is increased, and arrangement wiring of an internal circuit is restricted, so that a chip size is increased. SOLUTION: In this semiconductor integrated circuit in which I/O cells 6 provided with VDD wiring 7 connected with a power source VDD and GND wiring 8 connected with a ground source GND are arranged side by side on the periphery, the I/O cell 6 is provided with inverters 9 which invert an inputted signal and output it. The inverters 9 are connected with neighboring inverters 9 through signal wiring 10 and form a ring oscillator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an ECA (Embedded Cell Array) formed by combining macro cells (inverters, NAND circuits, etc.).
And a semiconductor integrated circuit such as a cell base.

[0002]

2. Description of the Related Art In recent years, as the process technology of semiconductor integrated circuits has advanced, the distance between wirings has become narrower, and the influence of the delay time due to the wiring capacitance between adjacent wirings has become greater than the delay time due to the transistors themselves. Therefore, in order to improve the timing accuracy of signal transfer between transistors, not only the simulation accuracy of the transistors is improved, but also an environment capable of accurately simulating the influence of adjacent wiring is required.

The wiring capacitance between adjacent wirings is affected by the actual finished shape of the aluminum wiring, the wiring interval, the thickness of the aluminum wiring, and the shape of the material formed in the oxide film filling the space between the aluminum wirings, and the chip performance between lots is affected. Is the cause of the variation. Therefore, in the basic design, it is necessary to design in consideration of the worst case of the variation of the wiring capacitance of the adjacent wiring. In addition, it is necessary to monitor the wiring capacity between adjacent wirings in all chips, feed back the process, and control the line devices so that an appropriate wiring capacity is provided.

However, the wiring capacitance inside the chip is extremely small, and if a direct measurement is to be performed, the error will fluctuate greatly due to a slight change in the measurement environment, and measurement cannot be performed with high accuracy. For this reason, the indirect measurement is performed by replacing the wiring capacitance inside the chip with the delay time of the circuit operation.

A typical circuit is a ring oscillator, and FIG. 7 shows a circuit diagram thereof. In the figure, 1 is a NAND circuit (first-stage inversion circuit) that outputs an inverted signal of the logical product of the control signal and the output signal of the inverter 2h, and 2a is the NA
An inverter that inverts the output signal of the ND circuit 1 and outputs it (two-stage inverting circuit); 2b, an inverter that inverts and outputs the output signal of the inverter 2a (a three-stage inverting circuit);
c is an inverter (k-1 stage inverting circuit) and 2d is an inverter (k that inverts and outputs the output signal of the inverter 2c.
2e is an inverter (k + 1-stage inverting circuit) that inverts the output signal of the inverter 2d and outputs the inverted signal.
f is an inverter (k + 2 stage inverting circuit) that inverts and outputs the output signal of the inverter 2e, and 2g is an inverter (n
-1 stage inverting circuit), 2h is an inverter (n-stage inverting circuit) that inverts the output signal of inverter 2g and outputs it to NAND circuit 1, 3a is an inverter that inverts and outputs the output signal of inverter 2d, 3b Is an inverter that inverts the output signal of the inverter 3a and outputs the inverted signal to the outside. By arranging dozens of inverting circuits in a loop, a rectangular wave oscillation signal is output.

The inversion circuits (NAND circuit 1 and inverters 2a,..., 2h, 3a, 3b) are connected by aluminum wiring, and this aluminum wiring is adjacent to wiring of circuits other than the ring oscillator. 8, the capacity (C ₁ ,
_{C 2, ···, C k,} ···, C n-1, C n and C
_in , C _out ). Capacities C ₁ , C ₂ , ...
.., C _k ,..., C _n−1 , C _n , the frequency of oscillation increases or decreases, and as the capacity increases, the frequency decreases.

[0007] The ring oscillator will be described. For simplicity, a five-stage inversion circuit (NAND circuit 4) as shown in FIG.
And a ring oscillator composed of inverters 5a, 5b, 5c and 5d). In the figure, reference numeral 4 denotes a NAND circuit (first-stage inversion circuit) that outputs an inverted signal of a logical product of the control signal and the output signal of the inverter 5d;
Let the signal delay time be T _d1 . 5a is a NAND circuit 4
(A two-stage inverting circuit) that inverts and outputs the output signal of (1), and the delay time of the signal is _Td2 . Reference numeral 5b denotes an inverter (three-stage inverting circuit) that inverts the output signal of the inverter 5a and outputs the inverted signal, and sets the signal delay time to T _{d 3}
And Reference numeral 5c denotes an inverter (four-stage inverting circuit) that inverts and outputs the output signal of the inverter 5b, and the signal delay time is _Td4 . Reference numeral 5d denotes an inverter (five-stage inverting circuit) for inverting the output signal of the inverter 5c and outputting the inverted signal to the external circuit and the NAND circuit 4.
_d5 .

Next, the operation will be described. The ring oscillator is configured by arranging an odd number of inverters (the first stage is a NAND circuit) in a ring shape. As an initial value, the control signal is set to L
Level, the output signals of NAND circuit 4 and inverters 5b and 5d are at H level, and the output signals of inverters 5a and 5c are at L level.

In this state, when the control signal is set to the H level, the control signal of the H level and the output signal of the inverter 5d of the H level are input to the NAND circuit 4.
The output signal of the AND circuit 4 changes to the L level after the time _Td1 . The output signal of the inverter 5a is time (T _d1 + T
_d2 ) Later, it changes to the H level. Therefore, the inverter 5d operates for the time (T _d1 + T _d2 + T _d3 + T _d4 + T
_d5 ) Later, it changes to L level.

Here, the time when the inverter 5d changes to the L level is used as a reference. Since the H-level control signal and the L-level output signal of the inverter 5d are input to the NAND circuit 4, the output signal of the NAND circuit 4 is set at the time T.
It changes to the H level after _d1 . The output signal of the inverter 5a changes to the L level after a time (T _d1 + T _d2 ).
Therefore, the inverter 5d operates at time (T _d1 + T _d2 +
After T _d3 + T _d4 + T _d5 ), the level changes to the H level.

As described above, the output (A) of the ring oscillator
The output signal of the inverter 5d) is time (T_d1+ T_d2+
T_d3+ T_d4+ T_d5), Level change (H → L
Or L → H). Where T_d2=
T_d3= T_d4= T_d5Therefore, the oscillation frequency f
_OSCIs f_OSC= 1/2 (T_d1+ 4 × T_d2). Make the number of inverter stages very large (n stages)
And the effect of the delay of the first stage NAND circuit 4 is reduced.
So f_OSC≒ 1 / 2nT_d2 ... (1) Therefore, the oscillation frequency f_OSCMeasure
The delay time T of the inverter_d2Is T_d2= 1 / 2nf_OSC  Can be evaluated.

Further, the delay time T _d2 of the inverter is changed by the wiring capacitance Co at the subsequent stage of the inverter, and T _d2 = m ₁ + m ₂ × (Co) ^α (m ₁ , m ₂ and α are constants) 2) Therefore, from equations (1) and (2), the oscillation frequency f _OSC decreases as the capacitance Co increases.

[0013]

As the number of inverters constituting the ring oscillator increases, the circuit scale increases because the measurement can be performed with higher accuracy, and the inverters are arranged in a horizontal (vertical) configuration. FIG. 10 is a configuration diagram showing a conventional semiconductor integrated circuit, in which 100 is a semiconductor integrated circuit, 101 is a ring oscillator, 102 is an I / O cell for inputting a control signal to the ring oscillator 101, 1
03 denotes an I / O cell for outputting the oscillation signal of the ring oscillator 101 to the outside,
Reference numeral 105 denotes an internal circuit composed of an analog circuit adjacent to the ring oscillator 101.

As described above, the conventional semiconductor integrated circuit 100
The ring oscillator 101 in FIG.
05, the signal flowing through the wiring of the internal circuit 104 and the noise of the internal circuit 105 formed of an analog circuit affect the ring oscillator 101.

Since the conventional semiconductor integrated circuit is configured as described above, the circuit scale of the ring oscillator 101 becomes large and the arrangement and wiring of the internal circuits 104 and 105 are restricted in order to perform highly accurate measurement. Will add
There is a problem that the chip size becomes large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a ring oscillator capable of performing high-accuracy measurement without reducing the arrangement area of internal circuits and reducing the chip size. It is an object of the present invention to obtain a semiconductor integrated circuit capable of performing the above.

[0017]

A semiconductor integrated circuit according to the present invention has a first power supply line connected to a first power supply and a second power supply connected to a second power supply having a lower potential than the first power supply. In a semiconductor integrated circuit in which input / output cells having two power supply lines are arranged side by side, the input / output cells include an inversion circuit for inverting and outputting an input signal, and the inversion circuit is connected to an adjacent inversion circuit and a signal line. To form a ring oscillator.

The signal wiring of the semiconductor integrated circuit according to the present invention is wired between the first power supply wiring and the second power supply wiring.

In the semiconductor integrated circuit according to the present invention, the inverting circuit is any one of an inverter, a NAND circuit, and a NOR circuit.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a configuration diagram showing input / output cells in a semiconductor integrated circuit according to Embodiment 1 of the present invention.
In the figure, reference numeral 6 denotes an I / O cell (input / output cell) having input / output pads and the like and arranged around a semiconductor integrated circuit;
/ O cell 6, a VDD wiring (first power supply wiring) connected to a voltage source VDD (first power supply), and VDD wirings 7 of adjacent I / O cells 6 are connected to each other. . 8 is wired to the I / O cell 6, and is connected to a ground source GND (second
(Second power supply line), and the GND lines 8 of the adjacent I / O cells 6 are connected to each other. Reference numeral 9 denotes an inverter (inverting circuit) arranged in the I / O cell 6, which corresponds to the inverter 2a in FIG. Numeral 10 is a signal wiring for connecting the inverter 9 with the adjacent inverter 9.

FIG. 2 is a block diagram showing an inverter in the semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 2, reference numeral 11 denotes a wiring forming the inverter 9, and 12 denotes a gate section forming the inverter 9. Signal wiring 10
Is connected to the second Al wiring layer (aluminum wiring), and the wiring 11
Are connected to the first Al wiring layer (aluminum wiring).

FIG. 3 is a configuration diagram showing a corner cell in the semiconductor integrated circuit according to the first embodiment of the present invention.
In the figure, 13 is a corner cell arranged at each of the four corners of the semiconductor integrated circuit, and 14 is a V
This is a DD wiring (first power supply wiring) and is connected to the VDD wiring 7 of the adjacent I / O cell 6. Reference numeral 15 denotes a GND wiring (second power supply wiring) wired to the corner cell 13, which is connected to the GND wiring 8 of the adjacent I / O cell 6. Numeral 16 denotes a signal wiring wired to the corner cell 13 and is connected to the signal wiring 10 of the adjacent I / O cell 6.

FIG. 4 is a block diagram showing a semiconductor integrated circuit according to the first embodiment of the present invention. In the figure, reference numeral 17 denotes an I / O in which a NAND circuit (inverting circuit) corresponding to the NAND circuit 1 of FIG. 7 is arranged. O cells (input / output cells) 18 are I / O cells (input / output cells) in which an inverter with output (inverting circuit) corresponding to the inverter 3b in FIG. 7 is arranged. Reference numeral 19 denotes a semiconductor integrated circuit in which corner cells 13 are arranged at four corners, and a plurality of I / O cells 6 are arranged between the corner cells 13. The location is any one of the locations where the I / O cell 17 in which the NAND circuit is located and the location of the plurality of I / O cells 6 are located.
The place is an I / O cell 18 in which an inverter with output is arranged.
It has become. Reference numeral 20 denotes an I / I around the semiconductor integrated circuit 19.
This is a ring oscillator configured by arranging the O cells 6, 17, 18 and the corner cells 13, and a signal line connecting each inverting circuit (inverter or NAND circuit) is wired between a VDD line and a GND line. I have.

Next, the operation will be described. The basic operation of the ring oscillator is the same as that of the prior art, and a description thereof will be omitted. In the semiconductor integrated circuit 19 according to the first embodiment, corner cells 13 are arranged at four corners, a plurality of I / O cells 6 are arranged side by side between the corner cells 13, and a plurality of I / O cells 6 are arranged. Of these, an I / O cell 17 including a NAND circuit is arranged at an arbitrary location, and an I / O cell 18 including an inverter with an output is arranged at an arbitrary location among a plurality of I / O cells 6. I have.
The VDD wirings (7, 14) of the adjacent I / O cells 6, 17, 18 or the corner cells 13 are connected to each other to form a ring-shaped VDD wiring, and the GND wirings (8, 15) are also connected to each other to form a ring-shaped VDD wiring. It constitutes a GND wiring. Then, the signal wirings (10, 16) of the adjacent I / O cells 6, 17, 18 or the corner cell 13 are connected to each other, and the signal wirings (10, 16) are connected to the VDD wirings (7, 14) and GN.
The ring oscillator 20 sandwiched between the D wirings (8, 15) is configured.

The correspondence between the ring oscillator 20 and the ring oscillator shown in FIG. 7 will be described. The NAND circuit arranged in the I / O cell 17 corresponds to the NAND circuit 1 and
The inverter 9 arranged in the O cell 6 corresponds to the inverter 2a and the like, and the inverter with output arranged in the I / O cell 18 corresponds to the inverter 3b. The control signal is I / O
The rectangular wave oscillating signal which is input to the NAND circuit arranged in the cell 17 is output from the output-equipped inverter arranged in the I / O cell 18.

In the conventional semiconductor integrated circuit, the ring oscillator is arranged in the area where the internal circuit, which is a circuit other than the ring oscillator, is arranged. Therefore, the ring oscillator is adjacent to the internal circuit, and the signal or the signal flowing through the wiring of the internal circuit is lost. The noise of the internal circuit affects the ring oscillator. Semiconductor integrated circuit 1 according to Embodiment 1 of the present invention
In FIG. 9, since the ring oscillator 20 is arranged around the semiconductor integrated circuit 19 instead of the area where the internal circuit is arranged, the ring oscillator 20 is not adjacent to the internal circuit, and the signal flowing through the wiring of the internal circuit and the noise of the internal circuit are reduced. It does not affect the ring oscillator 20. In addition, ring oscillator 2
0 signal wiring (10, 16) is VDD wiring (7, 14)
And GND wiring (8, 15),
Since the adjacent wiring capacitance of the signal line can be calculated with high accuracy, there is an effect that the characteristics of the transistor can be accurately extracted.

Although a ring oscillator composed of an inverter ring has been described, a ring oscillator composed of a NAND ring as shown in FIG. 5 and a ring oscillator composed of a NOR ring as shown in FIG. 6 may be used. NAND
In a ring oscillator composed of a ring, the characteristics of a Pch transistor are emphasized. In a ring oscillator composed of a NOR ring, the characteristics of an Nch transistor are emphasized. Therefore, a ring oscillator composed of an inverter ring, a ring oscillator composed of a NAND ring, and N
By using the ring oscillator composed of the OR ring properly, there is an effect that the characteristics of the Pch transistor and the Nch transistor can be extracted in more detail.

As described above, according to the first embodiment, the first power supply wiring 7 connected to the first power supply VDD and the second power supply GND having a lower potential than the first power supply VDD.
In the semiconductor integrated circuit 19 in which the input / output cells 6 provided with the second power supply wiring 8 connected to the semiconductor integrated circuit 19 are arranged side by side, the input / output cells 6 include an inverting circuit 9 for inverting and outputting an input signal, Since the inverting circuit 9 is connected to the adjacent inverting circuit 9 by the signal wiring 10 to form the ring oscillator 20, the ring oscillator 20 is arranged around the semiconductor integrated circuit 19, not in the area where the internal circuit is arranged. Since the oscillator 20 is not adjacent to the internal circuit, there is an effect that a semiconductor integrated circuit 19 in which a signal flowing through the wiring of the internal circuit or noise of the internal circuit does not affect the ring oscillator 20 can be obtained.

The signal wiring 10 is connected to the first power supply wiring 7.
And the second power supply wiring 8, so that
Since the signal wiring 10 of the ring oscillator 20 is sandwiched between the VDD wiring 7 and the GND wiring 8, it is possible to calculate the wiring capacitance adjacent to the signal line with high accuracy. is there.

Further, the inversion circuit 9 includes an inverter, an NA,
Since either the ND circuit or the NOR circuit is used, the characteristics of the Pch transistor are emphasized in the ring oscillator constituted by the NAND circuit, and the characteristics of the Nch transistor are emphasized in the ring oscillator constituted by the NOR circuit. By selectively using the ring oscillator constituted by the inverter, the ring oscillator constituted by the NAND circuit, and the ring oscillator constituted by the NOR circuit, there is an effect that the characteristics of the Pch transistor and the Nch transistor can be extracted in more detail.

[0031]

As described above, according to the present invention, the first
A semiconductor integrated circuit in which input / output cells each having a first power supply line connected to a power supply and a second power supply line connected to a second power supply having a lower potential than the first power supply are arranged side by side. The input / output cell includes an inverting circuit for inverting and outputting an input signal, and the inverting circuit is connected to an adjacent inverting circuit by signal wiring to form a ring oscillator. Since the ring oscillator is not located in the placement area but around the semiconductor integrated circuit and the ring oscillator is not adjacent to the internal circuit, a semiconductor integrated circuit in which signals flowing through the wiring of the internal circuit and noise of the internal circuit do not affect the ring oscillator can be obtained. There is.

According to the present invention, the signal wiring is arranged between the first power supply wiring and the second power supply wiring, so that the signal wiring of the ring oscillator is connected to the VDD wiring and the GND wiring.
Since the capacitor is sandwiched between the wirings, the capacitance of the wiring adjacent to the signal line can be calculated with high accuracy, so that there is an effect that the characteristics of the transistor can be accurately extracted.

According to the present invention, the inverting circuit is any one of an inverter, a NAND circuit, and a NOR circuit. Therefore, in the ring oscillator constituted by the NAND circuit, the characteristics of the Pch transistor are emphasized and the NOR circuit is enhanced.
Since the characteristics of the Nch transistor are emphasized in the ring oscillator constituted by the circuit, the ring oscillator constituted by the inverter, the ring oscillator constituted by the NAND circuit, and the ring oscillator constituted by the NOR circuit are selectively used, so that more details are provided. To P
There is an effect that the characteristics of the channel transistor and the channel transistor can be extracted.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing input / output cells in a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram showing an inverter in the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 3 is a configuration diagram showing a corner cell in the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 4 is a configuration diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 5 is a circuit diagram showing a ring oscillator constituted by a NAND circuit.

FIG. 6 is a circuit diagram showing a ring oscillator constituted by a NOR circuit.

FIG. 7 is a circuit diagram showing a ring oscillator.

FIG. 8 is a circuit diagram showing a ring oscillator.

FIG. 9 is a circuit diagram showing a ring oscillator.

FIG. 10 is a configuration diagram showing a conventional semiconductor integrated circuit.

[Explanation of symbols]

6, 17, 18 I / O cells (input / output cells), 7, 14
VDD wiring (first power supply wiring), 8, 15 GND wiring (second power supply wiring), 9 inverter (inverting circuit),
10, 16 signal wiring, 11 wiring, 12 gate part,
13 corner cell, 19 semiconductor integrated circuit, 20 ring oscillator.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 CD02 CD05 CD09 DF01 DT06 DT08 EZ10 EZ20 5F064 BB05 BB06 BB07 BB31 BB40 DD14 DD33 DD34 EE17 EE43 EE45 EE52 HH09 5J043 AA05 AA09 LL01

Claims (3)

[Claims] 1. An input / output cell having a first power supply line connected to a first power supply and a second power supply line connected to a second power supply having a lower potential than the first power supply. Wherein the input / output cell includes an inverting circuit for inverting and outputting an input signal, and the inverting circuit is connected to the adjacent inverting circuit by a signal line to form a ring oscillator A semiconductor integrated circuit characterized by the above. 2. The semiconductor integrated circuit according to claim 1, wherein the signal wiring is wired between the first power supply wiring and the second power supply wiring. 3. The semiconductor integrated circuit according to claim 1, wherein the inverting circuit is any one of an inverter, a NAND circuit, and a NOR circuit.