JP2002043215A - Method for forming resist pattern, semiconductor manufacturing apparatus, semiconductor device, and portable information terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a resist pattern by which a high- density resist pattern the line width of which can be controlled excellently on the surface of a wafer and between wafers can be formed, a semiconductor manufacturing apparatus a semiconductor device, and a portable information terminal. SOLUTION: In the method for forming resist pattern in which exposure is performed in a vacuum or a dry atmosphere, a resist is applied to a substrate in a resist applying step S1 and, after applying the resist, the substrate is pre- baked in a pre-baking step S2. Then, after the resist film on the pre-baked substrate is exposed in an exposing step S3, the performance stability of the resist is improved by promoting the diffusion of exposure products in the resist film in a diffusion promoting step S4. After the promoting step S4, the substrate is baked in a baking step S5 and the resist film is developed in a developing step S6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a resist pattern for fine patterning using a resist, a semiconductor manufacturing apparatus, a semiconductor device, and a portable information terminal.

[0002]

2. Description of the Related Art Conventionally, in semiconductor devices such as LSIs (Large Scale Integrated Circuits), resists have been widely used as a material for an etching mask. In particular, in order to increase the density as electronic devices become more functional and more sophisticated, resist patterns are formed by using light with shorter wavelengths, ionizing radiation, and electron beams for exposure to finer resist patterns. A method has been proposed. In the exposure in these resist pattern forming methods, it is necessary to expose in a vacuum or in a dry atmosphere in order to prevent the short-wavelength light, radiation and electron beam radiation sources from being attenuated by the atmosphere.

As a method of forming a resist pattern to be exposed in a vacuum or under a dry atmosphere, a method of forming a resist pattern using a chemically amplified resist has been proposed (JP-A-7-57997). In this method of forming a resist pattern using a chemically amplified resist, the amount of residual solvent in the resist before baking after exposure affects the sensitivity and resolution of the resist. It is controlled to become.

[0004]

However, in the method of forming a resist pattern using light having a shorter wavelength, ionizing radiation, or an electron beam for exposure, the method described above is performed in a vacuum (or in a dry atmosphere).
Since the resist applied to the substrate is exposed in the step, the amount of residual solvent varies with the sensitivity and resolution of the resist according to the holding time during which the substrate is held in vacuum (or in a dry atmosphere), and the amount of residual solvent is In addition, there is a problem that the sensitivity and resolution of the resist change depending on the degree of vacuum (or the degree of drying) when the substrate is held in a vacuum.

FIGS. 7 and 8 show a chemically amplified positive resist TDUR-P015 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) of 500.
Rotational coating is performed at 0 rpm, a resist film having a thickness of 200 nm is formed, and the change in sensitivity when the holding time or the degree of vacuum is changed is shown. In FIG. Is the sensitivity, and in FIG. 8, the horizontal axis is the degree of vacuum,
The vertical axis is the sensitivity. As shown in FIG. 7, the longer the standing time in vacuum, the lower the sensitivity. In addition, as shown in FIG. 8, the higher the degree of vacuum (the lower the pressure), the lower the sensitivity. These tendencies are the same when the exposure is performed in a dry atmosphere.

Further, when the solvent is left in the resist, when the exposure is performed in a vacuum, the solvent is diffused in the vacuum, or the reaction product generated in the resist by the exposure is diffused in the vacuum. And contaminate the exposure system. This problem also occurs when exposure is performed in a dry atmosphere.

Further, the amount of water remaining in the resist film affects the sensitivity and resolution, similarly to the solvent. In addition, water diffuses into the vacuum (or under a dry atmosphere), and reaction products generated in the resist by exposure diffuse into the vacuum (or under a dry atmosphere), thereby contaminating the exposure system. Problem.

Accordingly, an object of the present invention is to provide a high-density resist pattern which can make the sensitivity and resolution of a resist uniform in exposure in a vacuum or in a dry atmosphere, and has good line width control within a wafer surface and between wafers. It is an object of the present invention to provide a method of forming a resist pattern which can be formed and prevent contamination of an exposure system and a semiconductor manufacturing apparatus using the same, and a semiconductor device with a high density and a portable information terminal using the same.

[0009]

In order to achieve the above object, a method of forming a resist pattern according to the present invention comprises the steps of: applying a resist on a substrate; and prebaking the substrate after the resist application step. A pre-bake step of forming a film, an exposure step of exposing the resist film after the pre-bake step, a diffusion promotion step of promoting diffusion of a product by exposure in the resist film after the exposure step, and a diffusion promotion step A post-exposure bake step of baking the substrate after the step; and a development step of developing the resist film after the post-exposure bake step.

According to the above resist pattern forming method,
Product by exposure in the resist film after the exposure step
(E.g., acid generated by exposure in a chemically amplified resist) is promoted in a diffusion promoting step, and by diffusing a product by exposure in the resist film, the stability of the resist performance is improved, and the wafer surface is improved. A high-density resist pattern with good line width control between wafers can be formed.

In one embodiment of the present invention, a method of forming a resist pattern includes a residual solvent removing step of removing a residual solvent in the resist after the prebaking step.

According to the method of forming a resist pattern of the above embodiment, the residual solvent in the resist is removed in advance before the exposure step, and the residual solvent in the resist is made uniform. It is possible to form a high-density resist pattern with improved line width controllability within a wafer surface and between wafers. In the subsequent diffusion promotion step, for example, the substrate is kept under a solvent atmosphere of the resist, and the residual solvent is replenished, thereby facilitating diffusion of the product by exposure.

Further, the method for forming a resist pattern according to the present invention includes a resist coating step of coating a resist on a substrate, a prebaking step of forming a resist film by prebaking the substrate after the resist coating step.
An anti-diffusion film forming step of forming an anti-diffusion film for preventing diffusion of residual solvent in the resist on the resist film after the pre-baking step, and an exposing step of exposing the resist film after the anti-diffusion film forming step, A post-exposure bake step of baking the substrate after the exposure step; and a development step of developing the resist film after the post-exposure bake step.

According to the above resist pattern forming method,
By forming the residual solvent diffusion preventing film on the resist, it is possible to prevent the residual solvent during exposure from diffusing into vacuum (or under a dry atmosphere) and contaminating the exposure system. Further, the residual solvent diffusion preventing film can also prevent the product by exposure from diffusing into vacuum (or under a dry atmosphere).

In one embodiment of the present invention, the resist pattern forming method further comprises a silylation step of silylating the resist film after the post-exposure bake step and before the development step. It is characterized by developing.

According to the resist pattern forming method of the above embodiment, the exposed area of the resist film is silylated by the silylation step after the post-exposure bake step and before the development step, and other areas are removed by dry development. By doing so, a resist pattern with good line width controllability can be obtained.

In one embodiment, the method for forming a resist pattern comprises a step of removing the diffusion barrier film after the post-exposure bake step, and a step of removing the resist layer after the diffusion barrier film removal step and before the development step. And a silylation step of silylating the resist film, wherein the resist film is dry-developed in the development step after the silylation step.

According to the resist pattern forming method of the above embodiment, after the post-exposure baking step, the diffusion preventing film is removed in the diffusion preventing film removing step, and then the resist film is formed by the silylation step before the developing step. By exposing the exposed area to silylation and removing the other area by dry development, a resist pattern with good line width controllability can be obtained.

In one embodiment of the resist pattern forming method, in the resist coating step, two different resists are sequentially applied to a lower layer and an upper layer, and the upper layer of the resist film is wet-developed in the developing step. The method is characterized in that the lower layer of the resist film is dry-developed later.

According to the resist pattern forming method of the above embodiment, in the two-layer resist process technique, after the upper resist is wet-developed to form a pattern,
The lower resist is dry-developed with plasma or the like to form a pattern. Therefore, a resist pattern with good line width controllability can be obtained by using a two-layer resist process technique capable of forming a fine pattern even on a substrate having a step.

In one embodiment, the resist pattern forming method is characterized in that the substrate is held in a solvent atmosphere of the resist in the diffusion promoting step.

According to the resist pattern forming method of the above embodiment, the solvent lost during the exposure can be replenished in the resist, and the diffusion of the product by the exposure can be easily promoted.

In one embodiment of the present invention, in the method of forming a resist pattern, the substrate is washed with water or the substrate is heated in a steam atmosphere in the diffusion promoting step.

According to the method of forming a resist pattern of the above embodiment, the substrate is washed with water in the step of accelerating the diffusion, thereby allowing water to penetrate into the resist and facilitating the diffusion of the product by exposure. Further, in the diffusion promoting step, by heating the substrate in a water vapor atmosphere, water can penetrate into the resist, and the diffusion of the product by exposure can be easily promoted.

In one embodiment of the method of forming a resist pattern, the substrate is heated at a temperature equal to or higher than the boiling point of the solvent of the resist in the residual solvent removing step.

According to the resist pattern forming method of the embodiment, the substrate is heated at a temperature higher than the boiling point of the solvent of the resist in the step of removing the residual solvent, so that the residual solvent in the resist is efficiently removed in a short time. it can.

In one embodiment of the method of forming a resist pattern, the substrate is held under reduced pressure in the residual solvent removing step.

According to the resist pattern forming method of the above embodiment, the substrate is held under reduced pressure in the residual solvent removing step, so that the residual solvent is easily diffused from the resist film to the outside. Can be efficiently removed.

In one embodiment of the method of forming a resist pattern, the substrate is heated under reduced pressure in the residual solvent removing step.

According to the resist pattern forming method of the above embodiment, by heating the substrate under reduced pressure in the residual solvent removing step, the residual solvent is easily diffused from the resist film to the outside, and the residual solvent in the resist is removed. Can be efficiently removed.

In one embodiment of the present invention, the resist pattern is exposed in a vacuum or a dry atmosphere in the exposing step.

According to the resist pattern forming method of the above embodiment, light (or radiation, electron beam, etc.) from a radiation source is attenuated by exposing the resist film in a vacuum or under a dry atmosphere in the above exposure step. The factors can be eliminated, and the required exposure can be easily secured.

In one embodiment of the present invention, the resist film is exposed in a vacuum of 10 ^-4 Torr or less.

According to the resist pattern forming method of the embodiment, when exposing the resist film, 10 ^-4 To
Exposure in a vacuum below rr allows light from the source to
(Or radiation, electron beam, etc.) can be eliminated, and the required exposure can be easily secured. On the other hand, if the exposure step exceeds 10 ^-4 Torr, the light (or radiation, electron beam, etc.) from the radiation source is attenuated, making it difficult to obtain the required exposure.

In one embodiment of the present invention, in the above-mentioned exposure step, the resist film is exposed under a dry atmosphere, and the exposure is performed under a dry atmosphere using an inert gas.

According to the resist pattern forming method of the above embodiment, when exposing the resist film in a dry atmosphere with an inert gas, light (or radiation, electron beam, etc.) from a radiation source is emitted. It can be prevented from being absorbed by the atmosphere and attenuation can be reduced.

The resist pattern forming method according to one embodiment is characterized in that a resist that needs to be baked after exposure is used as a resist applied to the substrate.

According to the method for forming a resist pattern of the above embodiment, if the resist is in a state after the exposure and before the baking, the solvent or moisture of the resist easily penetrates into the resist, and the permeated moisture causes the product formed by the exposure. Diffusion is easy.

Further, in the semiconductor manufacturing apparatus according to the present invention, in the diffusion promoting step of the resist pattern forming method,
A semiconductor manufacturing apparatus for introducing a solvent of the resist into a wafer holding chamber holding the substrate, wherein an inert gas is used as a carrier gas.

According to the semiconductor manufacturing apparatus having the above structure, in the step of promoting diffusion in the method of forming a resist pattern,
Since the resist solvent is introduced into the wafer holding chamber holding the substrate by using an inert gas as a carrier gas, the resist solvent can be easily introduced into the wafer holding chamber with a simple configuration.

Further, according to the semiconductor manufacturing apparatus of the present invention, in the step of promoting diffusion of the resist pattern forming method,
A semiconductor manufacturing apparatus for introducing a solvent of the resist into a wafer holding chamber in which the substrate is held, wherein the wafer holding chamber is evacuated, and the solvent of the resist is introduced into the wafer holding chamber with a vapor pressure of the solvent. After the introduction, the inside of the wafer holding chamber is maintained at a constant pressure.

According to the semiconductor manufacturing apparatus having the above structure, after introducing the solvent of the resist into the wafer holding chamber in a vacuum state at the vapor pressure of the solvent, the inside of the wafer holding chamber is maintained at a constant pressure. Thereby, the introduction amount of the solvent can be adjusted by adjusting the pressure in the wafer holding chamber, and the diffusion promotion can be processed with high accuracy.

Further, a semiconductor device according to the present invention is characterized by being manufactured by using the above-described method for forming a resist pattern.

According to the semiconductor device having the above-described structure, by using a high-density resist pattern having good line width controllability, it is possible to greatly suppress the variation in the wiring resistance and the variation in the characteristics of the device. And can operate at high speed. Further, the power supply voltage can be set to 0.5 V, and the power consumption can be significantly reduced.

A portable information terminal according to the present invention is characterized by comprising the above-mentioned semiconductor device.

According to the portable information terminal having the above-described structure, a portable information terminal such as a portable telephone which requires high-speed operation and low power consumption can be realized by using the semiconductor device.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION As a result of repeated studies, the applicant has
When the resist on the wafer held in vacuum (or under a dry atmosphere) is exposed, the residual solvent in the resist diffuses out. There is a problem that the reaction product generated by exposure diffuses in vacuum (or under a dry atmosphere) and contaminates the exposure system.Therefore, in vacuum (or under a dry atmosphere) In order to improve the stability of the resist performance during the exposure, it was found that it was important to prevent the residual solvent and water in the resist film from coming out of the resist film during the exposure. Furthermore, it has been found that replenishment of the resist film with the residual solvent and water diffused in the vacuum on the substrate held in the vacuum after the exposure is effective for improving the controllability of the line width.

Hereinafter, a resist pattern forming method, a semiconductor manufacturing apparatus, a semiconductor device, and a portable information terminal according to the present invention will be described in detail with reference to the illustrated embodiments. However, needless to say, the present invention is not limited to the following embodiments.

(First Embodiment) FIG. 1 shows a process flow of a method for forming a resist pattern according to a first embodiment of the present invention. In the first embodiment, a silicon wafer that has been subjected to a surface treatment at 25 ° C. with HMDS (hexamethyldisilazane) vapor after a dehydration bake at 200 ° C. in advance is used.

First, in a resist coating step S1, a chemically amplified positive resist TD is formed on the silicon wafer.
UR-P015 (Tokyo Ohka Kogyo Co., Ltd.) 5000r
Spin coating at pm. At this time, the resist is applied not only on the silicon wafer but also on a substrate required in a semiconductor manufacturing process. The substrate required in the semiconductor manufacturing process includes, for example, a silicon oxide film, a silicon nitride film, a titanium nitride film, an aluminum film, and a copper film. In addition, the resist is not limited to the chemically amplified positive resist TDUR-P015, and may be any resist that can withstand etching, implantation, and the like in the next step.

Thereafter, a pre-bake (bake after coating) step S
In step 2, the resist-coated silicon wafer was
Prebake at 0 ° C. for 60 seconds to form a resist film having a thickness of 200 nm. This prebaking is suitably performed at about 90 ° C., but may be performed at about 80 ° C. to about 130 ° C. Also, the resist film thickness can be from 100 nm to 2000 nm, and may be any film thickness that can withstand etching, implantation, and the like in the next step.

Next, in the exposure step S3, the silicon wafer on which the resist film has been formed is introduced into an exposure chamber (degree of vacuum: 10 ⁻⁵ Torr), and extreme ultraviolet light (13 nm) is applied.
The resist film on the silicon wafer is exposed through a mask at an exposure amount of 5 mJ / cm ² by a reduced reflection exposure system (numerical aperture NA: 0.1, reduction ratio: 1/5) using the above method. The amount of exposure at this time varies depending on the type of resist and the pattern shape.

FIG. 4 is a schematic configuration diagram of the above-mentioned reduced reflection exposure system, wherein 1 is a silicon wafer, 2 is a mask,
3 is a first mirror, 4 is a second mirror, 5 is a third mirror, 6
Denotes EUV (extreme ultraviolet) light, and 7 denotes a vacuum chamber. In this reduced reflection exposure system, the EUV light 6 enters the vacuum chamber 7 and illuminates the mask 2. The above mask 2
Then, the EUV light 6 is reflected, and is reflected on the EUV light 6 on which the pattern information of the mask 2 is reflected. Then, the reflected EUV light 6 is repeatedly reflected by the first mirror 3, the second mirror 4, and the third mirror 5, and the pattern information of the mask 2 is reduced to expose the resist film on the silicon wafer.

Next, in the diffusion promoting step S4, the silicon wafer is held on a hot plate in an atmosphere saturated with a resist solvent, ie, PEGMEA (propylene glycol monomethyl ether acetate) vapor, and the
Perform solvent vapor treatment at 5 ° C. for 60 seconds. Here, PE
Although the treatment was performed with the GMEA vapor, the same effect can be obtained by treating with an organic solvent vapor that is effective in diffusing the reactant generated by the exposure. As organic solvents,
For example, it may be selected from solvents such as methyl alcohol, ethyl alcohol, n-propyl alcohol, isopropyl alcohol, acetone, N-methylpyrrolidone, ethyl cellosolve acetate, ethyl lactate, ethyl acetate, methyl acetate, butyl acetate and the like. It may be a mixture. When an organic solvent is used in the step of accelerating the diffusion, the solvent can be easily diffused into the resist, and the effect appears in a short time.

The diffusion promoting step S4 is performed by a solvent diffusion apparatus as a semiconductor manufacturing apparatus shown in FIG.
In FIG. 9, 101 is a silicon wafer, 108 is a wafer support pin, 109 is a hot plate, 110 is a dispersion plate, 111 is a chamber, 112 is a vaporized solvent inlet, 1
Reference numeral 13 denotes a PGMEA as a solvent, 114 denotes a carrier gas inlet, 115 denotes a liquid level of the PGMEA, and 118 denotes a container.

The silicon wafer 101 is held on the hot plate 109 in the chamber 112 by the wafer support pins 108, and a PGMEA solution is prepared in the container 118, and the P gas in the container 118 is prepared using nitrogen gas as a carrier gas.
EGMEA is bubbled and vaporized, and the vaporized PEG
The MEA is supplied to the chamber 11 through the vaporized solvent inlet 112.
2 is introduced. At this time, a dispersion plate 110 was introduced to uniformly treat the silicon wafer 101 with PEGMEA. In this solvent expansion device, nitrogen was used as a carrier gas for transporting PEGMEA, but any inert gas such as helium can be used. Further, in the above-mentioned solvent expansion apparatus, the silicon wafer 101 is
, The heat from the hot plate 109 can be uniformly transmitted to the silicon wafer 101, and the temperature variation of the silicon wafer 101 can be suppressed to ± 0.1 ° C. or less. The solvent diffusion device shown in FIG. 9 can be manufactured at low cost.

It is also possible to use a solvent diffusion apparatus as another semiconductor manufacturing apparatus shown in FIG. 10 to perform the diffusion promoting step. In FIG. 10, 201 is a silicon wafer, 208 is wafer support pins, 209 is a hot plate, 210 is a dispersion plate, 211 is a chamber, 212
Is a vapor solvent inlet, 213 is PEGME as a solvent
A and 215 are liquid levels of PEGMEA, 216A and 216B
Is a valve, 217 is a pressure gauge, and 218 is a container.

The silicon wafer 201 is held by the wafer support pins 208 on the hot plate 209 in the chamber 211, and a pegmea solution is prepared in the container 218. Then, the valve 216B is opened, and the inside of the chamber 211 is evacuated to 1 Torr or less by a vacuum pump (not shown). Then, the evacuation is stopped, and the valve 216A between the container 218 of the PEGMEA liquid and the chamber 211 is opened. Using the vapor pressure of PEGMEA, the chamber 21
Introduce PEGMEA into 1. At that time, the pressure gauge 21
7, the pressure of the chamber 211 is monitored,
Adjust the amount of EA introduced. PEGMEA solution container 218
By heating the vapor pressure of PEGMEA can be increased,
The introduction amount can be increased. In this first embodiment, PEGM
The processing is performed by maintaining the chamber 211 at a pressure of 30 Torr at EA of 25 ° C. for 60 seconds. The solvent diffusion device shown in FIG. 10 can perform highly accurate processing.

Next, in the post-exposure bake step S5, the post-exposure bake (PEB: Post Expo
Make sure bake) at 110 ° C for 90 seconds. At this time, the post-exposure bake can be performed at about 100 to 140 ° C., but the amount of exposure greatly depends on the bake.

Further, in the developing step S6, the TM
AH (tetramethylammonium hydroxide)
2.38% aqueous solution NMD-3 (manufactured by Tokyo Ohka Kogyo Co., Ltd.)
To develop a resist film, and post-bake at 100 ° C. for 60 seconds. At this time, post-baking is performed at 80 ° C to 120 ° C.
Places are possible. The developer used in the developing step S6 may be any developer that can develop a chemically amplified positive resist.

With respect to the resist pattern formed by the method of forming a resist pattern according to the first embodiment, the line width of 25 points is measured over the entire surface of the wafer using a length measuring SEM (scanning electron microscope). As a result of randomly extracting 10 wafers from 50 wafers and measuring their respective line widths, the variation in the wafer surface with a line width of 0.1 μm: ± 5% or less of the line width between wafers with a line width of 0.1 μm Dispersion: ± 5% or less of line width In-plane variation of wafer with a line width of 0.2 μm: ± 3% or less of line width Variation between wafers with a line width of 0.2 μm: ± 3% or less of line width Contact hole diameter 0 .15 μm in-wafer variation: ± 5% or less of diameter Diameter of contact hole diameter of 0.15 μm between wafers: ± 5% or less of diameter Here, for example, a line width of 0.1 μm
Is less than ± 5% of the line width when the
The range is from 95 μm to 0.105 μm.

On the other hand, as a result of performing the pattern formation by proceeding exactly the same steps as in the first embodiment without performing the diffusion promoting step, the variation in the wafer surface having a line width of 0.1 μm was obtained as follows: ± 15% of line width Variation between wafers with a line width of 0.1 μm: ± 15% of line width Variation within a wafer with a line width of 0.2 μm: ± 10% of a line width Between wafers with a line width of 0.2 μm Variation: ± 10% of line width Variation in wafer surface of contact hole diameter 0.15 μm: ± 15% of diameter Variation between wafers of contact hole diameter 0.15 μm: ± 15% of diameter

As described above, in the diffusion promotion step after the above-mentioned exposure step, the diffusion of the product by the exposure in the resist film is promoted, and the stability of the resist performance is improved. A high-density resist pattern with good line width controllability can be formed while suppressing variations in line width between wafers.

(Second Embodiment) FIG. 2 shows a process flow of a method for forming a resist pattern according to a second embodiment of the present invention. The method for forming a resist pattern according to the second embodiment is the same as the steps S1 to S6 of the method for forming a resist pattern according to the first embodiment except for a residual solvent removing step described later.

In the second embodiment, in the process flow shown in the first embodiment, after the pre-bake step S2,
Further, before the exposure step S3, the silicon wafer on which the resist film is formed is placed on a hot plate using a resist solvent (PE
GMEA) boiling point (146 ° C) or higher at 150 ° C and 60 ° C
The residual solvent removing step S11 of heating at atmospheric pressure for a second is performed. At this time, the same effect can be obtained even if the pre-bake step S2 is omitted.

As a result of the residual solvent removing step S11, the residual solvent in the resist film became 0.75% by weight. The residual solvent amount was measured by subtracting the weight of the silicon wafer before applying the resist from the weight of the silicon wafer after applying the resist to obtain the applied resist weight,
Furthermore, from the thickness of the resist film and the size of the applied wafer, calculate the volume of the applied resist, multiply the resist density and the resist volume, and calculate the weight of the resist film when there is no residual solvent. The weight of the resist film thus obtained was subtracted from the actually measured weight of the resist to determine the amount of residual solvent.

The amount of residual solvent in the resist has characteristics as shown in FIGS. FIG. 5 shows the relationship between the prebake temperature and the residual solvent amount when the prebake time is set to 60 seconds. FIG. 6 shows that the pre-bake temperature is 60 ° C.
4 shows the relationship between the prebake temperature and the amount of residual solvent. As shown in FIG. 5, the residual solvent amount decreases as the pre-bake temperature increases, and when the temperature exceeds about 110 ° C., the residual solvent amount converges to a constant value. Further, as shown in FIG. 6, the longer the pre-bake time, the smaller the residual solvent amount. When the temperature exceeds about 200 ° C., the residual solvent amount converges to a constant value.

After the pre-bake step S2 and before the exposure step S3, in the residual solvent removing step S11 in which the resist-coated silicon wafer is heated on a hot plate at a temperature equal to or higher than the boiling point of the resist solvent, the boiling point of the PEGMEA (146 (° C.) or more, but under reduced pressure, the residual solvent can be sufficiently reduced even if the heating temperature is low. For example, at 90 ° C. and 60 ° C. under a reduced pressure of 1 Torr.
Even under the condition of seconds, it is possible to reduce the residual solvent to 0.7% by weight.

After performing the residual solvent removing step S11, the exposure step S3 to the developing step S3 are performed in the same manner as in the first embodiment.
By proceeding with No. 6, line width controllability similar to the resist pattern forming method of the first embodiment can be obtained.

As described above, by removing the residual solvent in the resist in advance in the residual solvent removing step S11 before the exposure step S3, the sensitivity of the resist can be made uniform and the line width controllability within the wafer surface and between the wafers can be achieved. And a high-density resist pattern with good quality can be formed.

(Third Embodiment) FIG. 3 shows a process flow of a method for forming a resist pattern according to a third embodiment of the present invention. In the third embodiment, a silicon wafer which has been subjected to a surface treatment at 25 ° C. with HMDS (hexamethyldisilazane) vapor after dehydration baking at 200 ° C. in advance is used.

First, in the resist coating step S21,
On the silicon wafer, a chemically amplified positive resist T
DUR-P015 (Tokyo Ohka Kogyo Co., Ltd.) 5000
Spin coating at rpm.

Thereafter, in a pre-bake step S22,
After the application, baking is performed at 90 ° C. for 60 seconds to form a resist film having a thickness of 200 nm.

Next, a residual solvent diffusion preventing film forming step S23
Then, the silicon wafer having the resist film formed thereon has a thickness of 5
A solution for a residual solvent diffusion preventing film of 0 nm is spin-coated, and after the application, baking is performed at 90 ° C. for 60 seconds to form a residual solvent diffusion preventing film. The solution for the residual solvent diffusion preventing film is a solution in which a polymer is dissolved in a solvent having a low boiling point, and for example, a solution in which polyvinyl alcohol is dissolved in ethyl alcohol. Preferably, the polymer used for the residual solvent diffusion preventing film may be any polymer that can be peeled off with a developing solution in the subsequent developing step.

Next, in the exposure step S24, the silicon wafer on which the residual solvent diffusion preventing film has been formed is placed in the exposure chamber.
(Vacuum degree 10 ⁻⁵ Torr), and through a mask by a reduced reflection exposure system (numerical aperture NA: 0.1, reduction ratio 1/5) using extreme ultraviolet light (13 nm) shown in FIG. Then, the resist film on the silicon wafer is exposed at an exposure amount of 7 mJ / cm ² .

Next, in the post-exposure bake step S25,
Post-exposure bake (PEB) is applied to the exposed silicon wafer by 11
Perform at 0 ° C. for 90 seconds.

Further, in a developing step S26, the resist film is developed with a 2.38% aqueous solution of TMAH (tetramethylammonium hydroxide) NMD-3 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 60 seconds, and post-processed at 100 ° C. for 60 seconds. Bake.

As a result, line width controllability similar to that of the resist pattern forming method of the first embodiment can be obtained.

Further, the residual solvent diffusion preventing film is formed on the resist in the residual solvent diffusion preventing film forming step S23 before the exposure step S24, so that the residual solvent during the exposure and the product by the exposure are diffused in a vacuum. To prevent contamination of the exposure system.

(Fourth Embodiment) A resist pattern forming method according to a fourth embodiment of the present invention has the same steps as the resist pattern forming method according to the first embodiment except for a resist and a developing step. Invite. In the method of forming a resist pattern according to the fourth embodiment, silylation and dry development are performed using a silylation resist. In the fourth embodiment, after a dehydration bake at 200 ° C. in advance, HMDS (hexamethyldisilazane) vapor is used at a temperature of 25 ° C.
Is used.

First, in a resist coating step S1, a silylation resist NTS-4 is formed on the silicon wafer.
(Sumitomo Chemical Co., Ltd.) is spin-coated at 3000 rpm. At this time, the resist is applied not only on the silicon wafer but also on a substrate required in a semiconductor manufacturing process. The substrate required in the semiconductor manufacturing process includes, for example, a silicon oxide film, a silicon nitride film, a titanium nitride film, an aluminum film, and a copper film.

Thereafter, a pre-bake (bake after coating) step S
In step 2, the resist-coated silicon wafer was
Pre-baking is performed at 0 ° C. for 60 seconds to form a resist film having a thickness of 400 nm. Pre-bake, 80 ° C to 130 ° C
It is also possible in the order. Also, the thickness of the formed resist can be from 200 nm to 2000 nm,
Any material can be used as long as it can withstand the etching and implantation in the next step.

Next, in the exposure step S3, the silicon wafer on which the resist film has been formed is introduced into an exposure chamber (degree of vacuum: 10 ⁻⁵ Torr), and the extreme ultraviolet light shown in FIG.
(13 nm) reduced reflection exposure system (numerical aperture N
A: A resist film on a silicon wafer is exposed through a mask at an exposure amount of 5 mJ / cm ² at a rate of 0.1 and a reduction ratio of 1/5). The exposure at this time is appropriately adjusted according to the type of resist and the pattern shape.

Thereafter, in the diffusion promoting step S4, the silicon wafer is held on a hot plate in an atmosphere saturated with PEGMEA (propylene glycol monomethyl ether acetate) vapor as a resist solvent at 25 ° C. for 60 seconds. Perform solvent vapor treatment. Here, the processing is performed with the pegmea vapor, but the same effect can be obtained by performing the processing with the organic solvent vapor that is effective for diffusing the reactant generated by the exposure. For example, as the organic solvent, methyl alcohol, ethyl alcohol, n-propyl alcohol, isopropyl alcohol, acetone, N-methylpyrrolidone, ethyl cellosolve acetate, ethyl lactate, ethyl acetate, methyl acetate,
It may be selected from solvents such as butyl acetate or a mixture thereof.

Next, in a post-exposure bake step S5, a post-exposure bake (PEB) is applied to the silicon wafer after the above-described processing by one step.
Perform at 10 ° C. for 90 seconds. At this time, the bake after exposure is 100
A temperature of about 140 ° C. is possible, but the amount of exposure greatly depends on it.

In the silylation step (not shown), dimethylaminodimethylsilane is used as a silylating agent.
The silylation is performed using (DMADMS). This silylation is performed in a silylation chamber manufactured by Lam Research Co., Ltd., and the silylation condition is a pressure of 30 Torr of the silylating agent.
r, chamber temperature 80 ° C., time 60 seconds. 2 μm
A silylation layer having a square area and a thickness of 100 nm is formed.
The thickness of the silylation layer at this time largely depends on the type of the resist and the silylation conditions. The thickness of the formed silylated layer is optimally 50 to 150 nm, and the thickness can be arbitrarily determined depending on the silylation conditions. In the fourth embodiment, dimethylaminodimethylsilane (DMADMS) is used as a silylating agent. However, diethylaminodimethylsilane, dimethylaminotrimethylsilane, and the like can be used similarly.

Next, in a dry development step (not shown), the resist film is dry-developed using a TCP (Transfer Coupled Plasma (Inductively Coupled Plasma)) processing apparatus TCP9400 (manufactured by Lam Research). Then, a resist pattern is formed. Dry development conditions at this time are as follows: TCP power: 500 W Substrate bias power: 100 W Pressure: 5 mTorr Gas flow rate: Oxygen gas 130 sccm Sulfur dioxide: 30 sccm Overetching amount: 50% (using an end point detector).

With respect to the resist pattern formed by the method of forming a resist pattern according to the fourth embodiment, the line width of 25 points is measured over the entire surface of the wafer using a length measuring SEM (scanning electron microscope). As a result of randomly extracting 10 wafers from 50 wafers and measuring their respective line widths, the variation in the wafer surface with a line width of 0.1 μm: ± 5% or less of the line width between wafers with a line width of 0.1 μm Dispersion: ± 5% or less of line width In-plane variation of wafer with a line width of 0.2 μm: ± 3% or less of line width Variation between wafers with a line width of 0.2 μm: ± 3% or less of line width Contact hole diameter 0 .15 μm in-wafer variation: ± 5% or less of diameter Diameter of contact hole diameter of 0.15 μm between wafers: ± 5% or less of diameter

On the other hand, the other steps were performed in exactly the same manner as in the first embodiment without performing the diffusion promoting step, and the pattern formation was performed. As a result, the variation in the wafer width of the line width of 0.1 μm was observed. : ± 15% of line width Variation between wafers with a line width of 0.1 μm: ± 15% of line width Variation in wafer plane of a line width of 0.2 μm: ± 10% of line width Between wafers with a line width of 0.2 μm Dispersion: ± 10% of line width Dispersion in wafer surface of contact hole diameter 0.15 μm: ± 15% of diameter Dispersion between wafers with contact hole diameter 0.15 μm: ± 15% of diameter

As described above, the variation in the line width in the silicon wafer can be suppressed.

Also, after the post-exposure bake step S5 and before the development step, the exposed area of the resist film is silylated by a silylation step, and the other areas are removed by dry development, so that the line width controllability is improved. A resist pattern can be obtained.

(Fifth Embodiment) A resist pattern forming method according to a fifth embodiment of the present invention is different from the resist pattern forming method according to the third embodiment except for the step of removing the resist and the residual solvent diffusion preventing film and the developing step. The same process is performed, and FIG. 3 is referred. In the method of forming a resist pattern according to the fourth embodiment, a silylation resist is used as a resist, and after the residual solvent diffusion preventing film is removed, silylation and dry development are performed. In the fifth embodiment, a silicon wafer that has been subjected to a surface treatment at 25 ° C. with HMDS (hexamethyldisilazane) vapor after dehydration baking at 200 ° C. in advance is used.

First, in the resist coating step S21,
On the silicon wafer, a silylation resist NTS-
4 (manufactured by Sumitomo Chemical Co., Ltd.) is spin-coated at 3000 rpm.

Thereafter, a pre-bake (bake after coating) step S
At 22, the silicon wafer coated with the resist is prebaked at 90 ° C. for 60 seconds to form a resist film having a thickness of 400 nm.

Next, a residual solvent diffusion preventing film forming step S23
Then, on the silicon wafer on which the resist is formed, a film thickness of 50
A solution for a residual solvent diffusion preventing film having a thickness of nm is spin-coated, and after the application, baking is performed at 90 ° C. for 60 seconds to form a residual solvent diffusion preventing film. The solution for the residual solvent diffusion preventing film is a solution in which a polymer is dissolved in a solvent having a low boiling point, and for example, a solution in which polyvinyl alcohol is dissolved in ethyl alcohol. Preferably, the polymer used for the residual solvent diffusion preventing film may be any polymer that can be peeled off with a developing solution in the subsequent developing step. Further, the thickness of the residual solvent diffusion preventing film can be applied in the range of 10 nm to 200 nm.

Next, in the exposure step S24, the silicon wafer on which the residual solvent diffusion preventing film is formed is introduced into the exposure chamber (vacuum degree: 10 ⁻⁵ Torr), and the extreme ultraviolet light (13 nm) shown in FIG. Using the reduced reflection exposure system (numerical aperture NA: 0.1, reduction ratio 1/5), the resist film on the silicon wafer was exposed through a mask to an exposure amount of 7 mJ / cm.
^2. Exposure is performed.

Next, in the post-exposure bake step S25,
Post-exposure bake (PEB) is applied to the exposed silicon wafer by 11
Perform at 0 ° C. for 90 seconds.

Next, a step of removing the residual solvent diffusion preventing film
(Not shown), the exposed silicon wafer is removed by removing the residual solvent diffusion preventing film using pure water. This peeling treatment is performed by rotating the silicon wafer at 500 rpm at 24 ° C. for 60 seconds while applying pure water to the silicon wafer.
The silicon wafer is rotated at 00 rpm without applying pure water to dry the silicon wafer.

Further, the same silylation step and dry development step as in the fourth embodiment are performed to obtain a resist pattern.

As a result, line width controllability similar to that of the resist pattern forming method of the fourth embodiment can be obtained.

After the post-exposure bake step S25, the diffusion preventing film is removed in a diffusion preventing film removing step, and thereafter, the exposed area of the resist film is silylated by a silylation step before the developing step, and the other areas are dried. By removing the resist pattern by development, a resist pattern having good line width controllability can be obtained.

(Sixth Embodiment) In a method of forming a resist pattern according to a sixth embodiment of the present invention, in the process flow shown in the first embodiment, pure water treatment is performed instead of the pegmea vapor treatment after exposure. is there. This pure water treatment is performed by rotating the silicon wafer at 500 rpm for 60 seconds at 24 ° C. while applying pure water to the silicon wafer. Thereafter, a post-exposure bake is performed, and the resist film is developed to form a resist pattern. When pure water is used, the apparatus can be easily used since pure water is used in a normal developing process.

The same effect can be obtained by performing steam treatment instead of the pure water treatment. This steam treatment is
Water vapor is put into the chamber at 00 ° C., and the silicon wafer is held therein for 60 seconds.

Thereafter, by performing the post-exposure steps in the same manner as in the resist pattern forming method of the first embodiment, it is possible to obtain the same line width controllability as in the first embodiment.

As described above, by washing the substrate with water in the above-mentioned diffusion promoting step, water can be permeated into the resist, and the diffusion of the product by exposure can be easily promoted. Heating underneath allows water to penetrate into the resist and facilitates the diffusion of the product by exposure.

(Seventh Embodiment) A seventh embodiment of the present invention relates to a device (semiconductor device) using any one of the resist pattern forming methods of the first to sixth embodiments. The gate processing which is important in characteristics will be described below.

First, the silicon substrate after the element isolation step is oxidized by 1.5 nm to form a gate oxide film on the silicon substrate. On top of this, a polysilicon film is formed by CVD method.
Deposit 0 nm.

Next, a resist pattern is formed on the polysilicon film by any one of the resist pattern forming methods of the first to sixth embodiments. By doing so, with a resist film thickness of 200 nm, the line width variation in the silicon wafer surface at a line width of 100 nm could be suppressed to ± 5% or less.

Next, the underlying polysilicon is dry-etched using the resist pattern as a mask, and the polysilicon gate is processed according to the mask. The line width variation at that time is ± 5% within the silicon wafer surface at a line width of 100 nm.
The following could be suppressed. Also, the resist pattern is 60 n by a reduced reflection exposure system (numerical aperture NA: 0.1, reduction ratio 1/5) using extreme ultraviolet light (13 nm).
m. Further, by increasing the numerical aperture NA of this reduced reflection exposure system to 0.2, the line width 30n
m.

The device manufactured by the above-described method for forming a resist pattern has a gate length of 100 nm or less, and furthermore, by suppressing the variation of the gate length to 5% or less,
Variation in characteristics of individual devices can be suppressed, and 1000M
It is possible to operate at high speed at the frequency of Hz,
The power supply voltage can be set to 0.5 V, and the power consumption can be significantly reduced. Such devices are:
The present invention can be applied to a portable information terminal such as a mobile phone that requires high-speed operation and low power consumption.

(Eighth Embodiment) An eighth embodiment of the present invention is a device using any one of the resist pattern forming methods of the first to sixth embodiments, and is particularly important in device characteristics. The contact hole processing and the through hole processing will be described.

First, on the silicon substrate after the gate processing,
A 500 nm interlayer insulating film is deposited. As this interlayer insulating film, BPSG (boron, phosphorus, silicate, glass),
There are a silicon oxide film such as a fluorine-doped silicon oxide film and an organic film such as polyimide.

Next, a resist pattern is formed on the interlayer insulating film by any one of the first to sixth embodiments. By doing so, the diameter of the resist pattern for processing the contact hole becomes 100
In the case of nm, the variation of the hole diameter could be suppressed to 5% or less.

Next, using the resist pattern for processing the contact hole as a mask, the interlayer insulating film is processed by dry etching to form a 100-nm hole, and furthermore, copper is buried in the hole, and furthermore, A resist pattern for wiring processing is formed by any one of the first to sixth embodiments. The line width is 100 nm, and the variation is 5% or less. The underlying copper is processed using the resist pattern for wiring processing as a mask. Furthermore, a multilayer wiring can be formed by depositing an interlayer insulating film and repeating the same process as described below.

The device manufactured by the above-described method for forming a resist pattern can have 10 or more multilayer wirings, and the variation in wiring resistance can be suppressed to 5% or less. In addition, variations in characteristics of individual devices can be suppressed, and 1000 MHz
, And the power supply voltage can be set to 0.5 V, and the power consumption can be greatly reduced. Such devices are:
The present invention can be applied to a portable information terminal such as a mobile phone that requires high-speed operation and low power consumption.

In the first to eighth embodiments, the resist pattern forming method using the extreme ultraviolet light (wavelength 13 nm) exposure method as the exposure method has been described. (1) The exposure method using an electron beam (for example, SCALPEL
(Scattering Agular Limited Projection Electron-bea
m Lithography) method, blanking aperture array (Bla
(nking Aperture Array) method, partial batch exposure method, variable shaping exposure method, point beam exposure method) (2) Exposure method using ion beam in vacuum such as ion projection lithography (3) F ₂ excimer laser (157 nm), ArF excimer laser (193 nm), KrF excimer laser (2
48 nm), Ar dimer excimer laser light (121 n
The same applies to an exposure method under a dry atmosphere using the wavelength of m). Also, extreme ultraviolet light is 3 ~
It may be 15 nm, or X-rays may be used. Here, in the exposure method in a vacuum, it is more effective if the degree of vacuum is a vacuum of 10 ^-4 Torr or less, and if it exceeds 10 ^-4 Torr, light and electron beams are excessively attenuated, which is effective. Exposure becomes impossible. In the exposure method under a dry atmosphere, performing exposure while purging with an inert gas is effective for suppressing attenuation of light (or radiation and an electron beam, etc.) from a radiation source. , An inert gas such as nitrogen or He is used.

In the first to eighth embodiments, the positive type chemically amplified resist is used. However, a resist that needs to be baked after exposure (a negative type chemically amplified resist, a surface imaging resist, diazonaphthoquinone / A similar effect can be obtained with a novolak-based resist.

[0118]

As is clear from the above, according to the method for forming a resist pattern of the present invention, when forming a resist pattern by exposure in a vacuum or under a dry atmosphere,
It is possible to form a resist pattern having good line width controllability within the silicon wafer surface and between the silicon wafers.

Further, according to the semiconductor manufacturing apparatus of the present invention, in the diffusion promoting step of the resist pattern forming method, the wafer is held in the wafer holding chamber holding the substrate.
Since the resist solvent is introduced using an inert gas as a carrier gas, the resist solvent can be easily introduced into the wafer holding chamber with a simple configuration.

After introducing the solvent of the resist into the wafer holding chamber in a vacuum state by the vapor pressure of the solvent,
By adjusting the pressure in the wafer holding chamber, the introduction amount of the solvent can be adjusted, and a semiconductor manufacturing apparatus that can process diffusion promotion with high accuracy can be realized.

Further, according to the semiconductor device of the present invention, by manufacturing using the above-described method for forming a resist pattern, ten or more multi-layer wirings can be formed, and the variation in the wiring resistance can be greatly suppressed. Characteristic variations can be suppressed, high-speed operation can be performed at a frequency of 1000 MHz, and operation can be performed at a power supply voltage of 0.5 V, so that power consumption can be significantly reduced.

Further, the portable information terminal of the present invention can realize a portable information terminal (such as a portable telephone) which operates at high speed and consumes low power by using the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a process flow of a method for forming a resist pattern according to a first embodiment of the present invention.

FIG. 2 is a process flow of a method for forming a resist pattern according to a second embodiment of the present invention.

FIG. 3 is a process flow of a method for forming a resist pattern according to a third embodiment of the present invention.

FIG. 4 is a schematic diagram of a reduced reflection exposure system using extreme ultraviolet light.

FIG. 5 is a diagram showing a relationship between a residual solvent amount in a resist and a pre-bake temperature.

FIG. 6 is a diagram showing a relationship between a residual solvent amount in a resist and a pre-bake time.

FIG. 7 is a diagram showing a relationship between a standing time in a vacuum and sensitivity.

FIG. 8 is a diagram showing the relationship between the degree of vacuum and the sensitivity.

FIG. 9 is a schematic configuration diagram of a solvent diffusion device.

FIG. 10 is a schematic configuration diagram of another solvent diffusion device.

[Explanation of symbols]

 1, 101, 201: silicon wafer, 2: mask, 3: first mirror, 4: second mirror, 5: third mirror, 6: EUV (extreme ultraviolet) light, 7: vacuum chamber, 8, 108, 208 ... Wafer support pins, 9,109,209 ... Hot plate, 110,210 ... Dispersion plate, 111,211 ... Chamber, 112,212 ... Vaporized solvent inlet, 113,213 ... PEGMEA, 114 ... Carrier gas inlet, 115 , 215: liquid level, 216A, 216B: valve, 217: pressure gauge.

Claims (19)

[Claims] A resist coating step of applying a resist on a substrate; a prebaking step of forming a resist film by prebaking the substrate after the resist coating step; and an exposing step of exposing the resist film after the prebaking step A diffusion promoting step of promoting diffusion of a product by exposure in the resist film after the exposure step; a post-exposure baking step of baking the substrate after the diffusion promoting step; and And a developing step of developing the resist film. 2. The method for forming a resist pattern according to claim 1, further comprising a residual solvent removing step of removing a residual solvent in the resist after the pre-baking step. A resist coating step of applying a resist on the substrate; a prebaking step of forming a resist film by prebaking the substrate after the resist coating step; and a resist coating on the resist film after the prebaking step. An anti-diffusion film forming step of forming an anti-diffusion film for preventing the diffusion of the residual solvent, an exposure step of exposing the resist film after the anti-diffusion film formation step, and a post-exposure bake of baking the substrate after the exposure step And a developing step of developing the resist film after the post-exposure bake step. 4. The resist pattern forming method according to claim 1, further comprising a silylation step of silylating the resist film after the post-exposure bake step and before the development step. A method of forming a resist pattern, comprising dry developing a resist film. 5. The method of forming a resist pattern according to claim 3, wherein the step of removing the diffusion barrier film after the post-exposure bake step includes the steps of: removing the diffusion barrier film; and after the diffusion barrier film removal step and before the development step. A silylation step of silylating the resist, wherein the resist film is dry-developed in the development step after the silylation step. 6. The method for forming a resist pattern according to claim 1, wherein two different types of resists are sequentially applied to the lower and upper layers in the resist application step, respectively. A method of forming a resist pattern, comprising wet-developing an upper layer of the resist film and dry-developing a lower layer of the resist film. 7. The method for forming a resist pattern according to claim 1, wherein the substrate is held in a solvent atmosphere of the resist in the diffusion promoting step. 8. The method for forming a resist pattern according to claim 1, wherein the substrate is washed with water or the substrate is heated in a steam atmosphere in the step of promoting diffusion. 9. The resist pattern forming method according to claim 2, wherein the substrate is heated at a temperature equal to or higher than a boiling point of the solvent of the resist in the residual solvent removing step. 10. The resist pattern forming method according to claim 2, wherein said substrate is held under reduced pressure in said residual solvent removing step. 11. The method according to claim 2, wherein the substrate is heated under reduced pressure in the residual solvent removing step. 12. The resist pattern forming method according to claim 1, wherein the resist film is exposed in a vacuum or a dry atmosphere in the exposing step. . 13. The resist pattern forming method according to claim 12, wherein the resist film is exposed in a vacuum, wherein the resist film is exposed to a vacuum of 10 ^-4 Torr or less. Pattern formation method. 14. The method for forming a resist pattern according to claim 12, wherein the exposing step of exposing the resist film in a dry atmosphere is performed in a dry atmosphere with an inert gas. A method for forming a resist pattern. 15. The method of forming a resist pattern according to claim 1, wherein a resist that needs to be baked after exposure is used as a resist applied to the substrate. Method. 16. A semiconductor manufacturing apparatus for introducing a solvent of the resist into a wafer holding chamber holding the substrate in the diffusion promotion step of the method for forming a resist pattern according to claim 7. A semiconductor manufacturing apparatus, comprising: using as a carrier gas. 17. A semiconductor manufacturing apparatus for introducing a solvent of the resist into a wafer holding chamber holding the substrate in the diffusion promotion step of the method for forming a resist pattern according to claim 7. A semiconductor manufacturing apparatus, wherein the chamber is evacuated, the solvent of the resist is introduced into the wafer holding chamber at the vapor pressure of the solvent, and then the inside of the wafer holding chamber is held at a constant pressure. 18. A semiconductor device manufactured by using the method of forming a resist pattern according to claim 1. Description: 19. A portable information terminal comprising the semiconductor device according to claim 18.