JP2002040111A - Logic semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic semiconductor testing device to perform clock frequency screening tests on a plurality of DUTs by simultaneous measurements at a high speed. SOLUTION: (1) The same test signal is impressed on the plurality of DUTs, and the logical patterns of response signals from the plurality of DUTs are logically compared with expected value patterns from a pattern generator at each pattern comparator. The results of the logical comparison are stored in the failure analysis memory of a failure analysis memory part to perform the clock frequency screening tests in the logic semiconductor testing device for simultaneous measurements and testings. The logic semiconductor testing device is provided with (2) a fail register provided on the preceding stage of the failure analysis memory to store total fails signal DUT by DUT and (3) a failure analysis memory control part for fetching the contents of the fail register in the failure analysis memory and to perform control, when the frequency screening tests are completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic semiconductor test apparatus for performing a clock frequency selection test of a logic semiconductor LSI, which is a DUT (device under test), in a simultaneous measurement test. Semiconductor devices include a logic semiconductor, a semiconductor memory, and a mixed semiconductor device in which logic, memory, and an analog department are mixed. The present invention relates to a logic semiconductor test device, but is also applicable to a mixed semiconductor test device.

[0002]

2. Description of the Related Art First, an outline of a logic semiconductor test apparatus will be described. FIG. 6 shows a basic block diagram of the logic semiconductor test apparatus. The control device 30, which is generally called a test processor, controls the entire device, and supplies control signals to the units of each department via a tester bus.

A pattern generator 31 generates an applied pattern to be applied to a DUT (device under test) 25i (i = 1 to n) and an expected value pattern to be applied to a pattern comparator 37i (i = 1 to n). The reason why there are a plurality of DUTs or the like is that a test of simultaneous measurement (hereinafter referred to as “simultaneous measurement”) is performed in parallel. The reference clock generator 32 receives a clock control signal from the pattern generator 31, generates a plurality of high-precision reference clocks, and supplies them to the pattern generator 31, the timing generator 33, and the like.

The timing generator 33 generates a timing pulse signal to determine a test period signal and a test timing of the entire apparatus, and generates a pattern generator 31, a waveform shaper 34i (i = 1 to n) and a pattern comparator. Container 37 (i =
1 to n) and the like, and the timing of the test is set. The waveform shaper 34i shapes the applied pattern from the pattern generator 31 into a test signal waveform, and supplies a test signal to the DUT 25i via a driver (not shown).

[0005] The DUT 25i is inserted into each insertion portion 27i of the DUT insertion portion 27 and tested. Although not shown, the response signal read from the DUT 25i is compared with a voltage by a comparator, and the resulting logical pattern signal is given to a pattern comparator 37i. The pattern comparator 37i
The logical pattern of the test result from the comparator and the expected value pattern from the pattern generator 31 are logically compared to detect a match / mismatch, and the pass / fail judgment of the DUT 25i is performed. The result of the determination is transmitted to the failure analysis memory unit 39 and 1
If any failure occurs, a fail signal is sent to the fail signal generator 38.

The fail signal generator 38 receives a fail signal from the pattern comparator 37i, generates a fail signal for each DUT, and supplies it to the pattern generator 31. The failure analysis memory unit 39 receives the capture control signal from the pattern generator 31 and stores failure information from the pattern comparator 37i, address information from the pattern generator 31, and the like.

FIG. 7 shows an internal configuration diagram of an example of a conventional failure analysis memory section 39 and a pattern generator 31 relating to failure analysis. Each part of the failure analysis memory section 39 and the pattern generator 31 is controlled by the control device 30 via a tester bus. The failure analysis memory unit 39 includes the failure detection unit 4
0, failure analysis memory control unit 41 and failure analysis memory 42
It is composed of

The fail detector 40 receives a fail signal in DUT units from the fail signal generator 38 and transmits the fail signal to the failure analysis memory controller 41 and the sequence controller 50 of the pattern generator 31. The failure analysis memory control unit 41 includes a failure detection unit 40
And sends a memory fetch signal to the failure analysis memory 42 or the like. The failure analysis memory 42 receives a memory fetch control signal from the failure analysis memory control unit 41,
The fail signal from the fail detector 40, the pattern address signal from the sequence controller 50, and the pattern count signal are stored in the memory.

The pattern generator 31 comprises a sequence control unit 50, a pattern data memory 51 and a control data memory 52. For failure analysis, a pattern address signal and a pattern count signal from the sequence control unit 50 are used. It is provided to the failure analysis memory 42. The pattern count is the number of times the test pattern has been generated, and is counted by the pattern generator 31.
Different from pattern address.

In the logic semiconductor test apparatus, failure analysis is performed using the total failure, pattern address and pattern count stored in the failure analysis memory 42. Total failure means that any one signal fails, and a flag is set at that time. All the test items are measured with this configuration, and the clock frequency selection test for the CPU and the like is also performed with this configuration.

FIG. 8 shows a DUT measurement flowchart for analyzing the clock frequency selection test of the prior art. The test starts at test start 100. Next, frequency setting 1
Perform 01. The setting of the clock frequency and the determination of the frequency are performed by a main program in the control device 30, and are set via a tester bus. Other operations are performed on the hardware wafer side. When frequency setting 101 is performed, pattern start 10
2 Next, it is determined 103 based on the DUT unit fail signal received by the fail detection unit 40 whether or not a failure has occurred in the DUT unit. If YES, a memory write 106 is performed in the failure analysis memory 42 to perform failure analysis. After the failure analysis, a determination 107 is made as to whether all DUTs have failed.
When the determination is NO, the process returns to the determination 103 of whether or not a failure has been made in DUT units in step 103. If the determination is YES, the process proceeds to the determination 108 of the end of the all-frequency test.

If the determination in step 103 as to whether or not a failure has occurred in DUT units is NO, a determination is made in step 104 as to whether or not the pattern has been completed. If the determination is NO, the process returns to the step 103 to determine whether or not the DUT has failed. YES
In the case of, the process proceeds to the judgment 108 of the end of the all frequency test. If the determination 108 of the end of the all-frequency test is NO, the next frequency setting is performed and repeated. If YES, the test ends 109.

[0013]

The clock frequency selection test can be sufficiently performed with the conventional configuration and procedure. However, in the conventional measurement test, each time any one of the DUTs 25i fails, the total fail signal, the pattern address signal, and the pattern count signal are stored in the failure analysis memory 42, and the failure analysis is performed.

The capacity of the conventional failure analysis memory 42 is 25
Since the clock frequency selection test is performed with a relatively small number of 6 to 1,000 words, the capacity is insufficient, and a failure analysis must be performed for each failure in each frequency test. This required a long test time. In order to shorten the test time, it is necessary to have a large capacity failure analysis memory for a clock frequency selection test.

According to the present invention, in the case of an LSI clock frequency selection test, only information on which DUT failed at which frequency by changing the frequency is required, and failure analysis is required for each failure. In view of such a characteristic, it is an object of the present invention to provide a logic semiconductor test apparatus capable of performing a clock frequency selection test at a high speed by using a conventional failure analysis memory and adding a few devices.

[0016]

In order to achieve the above object, according to the present invention, a small-capacity fail register of several words is provided at the preceding stage of a conventional failure analysis memory, and a total fail signal in DUT units is provided for each DUT. Store for each frequency. When the fail register is a single flip-flop, it is stored every clock frequency test measurement. Further, when a register such as a FIFO in which a plurality of flip-flops are subordinately connected is used, all frequency test measurements are stored continuously. In other words, in the clock frequency selection test, the failure is not analyzed for each failure, and only the phenomenon is recorded to continue the test. At the stage when the predetermined frequency selection test is completed,
The data is transferred to the failure analysis memory by a memory fetch control signal from the failure analysis memory control unit. Next, the configuration of the invention will be described.

The first invention is a basic invention for performing a clock frequency selection test. That is, the same test signal is applied to a plurality of DUTs, the logical pattern of response signals from the plurality of DUTs and the expected value pattern from the pattern generator are logically compared by respective pattern comparators, and the results are analyzed for failure. A logic semiconductor test apparatus for a simultaneous measurement test for performing a clock frequency selection test by storing in a failure analysis memory of a memory unit, the failure register being provided in a stage preceding the failure analysis memory and storing a total fail signal in DUT units. And a failure analysis memory control unit that takes in the contents of the fail register into the failure analysis memory when the frequency selection test is completed.

The second invention is an invention which is effective in practical use by allowing conventional tests to be performed. In other words, multiple DUTs
The same test signal is applied to each of the plurality of DUTs, and the logical patterns of the response signals from the plurality of DUTs and the expected value pattern from the pattern generator are logically compared by the respective pattern comparators. A logic semiconductor memory test device capable of simultaneous measurement testing in which a failure is stored in a memory, performs a failure analysis, and further performs a clock frequency selection test. The logic semiconductor memory testing device receives a total fail signal, a pattern address signal, and a pattern count signal for each DUT, and A signal switch that transmits only the total fail signal to the fail register during the frequency selection test, and a signal switch that transmits the received signal directly to the failure analysis memory during other tests, and a total fail signal in DUT units from the signal switch Fail register for receiving and storing, and clock frequency selection test Number screening test performs capture control the contents of the fail register at the end to the failure analysis memory, DUT during other tests during total fail signal
The logic semiconductor test apparatus includes a failure analysis memory control unit that performs control of taking in a total failure signal, a pattern address signal, and a pattern count signal of the unit into the failure analysis memory.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on examples with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of another embodiment of the present invention, FIG. 3 is a measurement flowchart of one embodiment of the present invention, and FIG. FIG. 5 is a conceptual diagram of good (PASS) / bad (FAIL) for each DUT and each frequency stored in the register. FIG. 5 shows DUs stored in the fail register and the failure analysis memory.
FIG. 4 is a configuration diagram showing an example of good / bad for each T and each frequency. In the above drawings, the same parts as those in FIGS. 6 and 7 are denoted by the same reference numerals.

The configuration diagram of FIG. 1 is a basic invention, and is different from the conventional configuration diagram of FIG. 7 in a logic semiconductor test apparatus for a simultaneous measurement test for performing a clock frequency selection test shown in FIG. Points will be described. In the prior art, a fail signal, a pattern address signal, and a pattern count signal are provided and stored in the failure analysis memory 42. According to the present invention, the fail register 11 is provided in the preceding stage of the failure analysis memory 42, and only the total fail signal in the unit of DUT is supplied to the fail register 11 and stored when the failure occurs. The total fail signal for each DUT is DU
A signal in which any one of the pins fails in T units.

If the test frequency is changed from a low frequency to a high frequency, the first total fail signal is stored for each DUT for each frequency. This is because a higher frequency thereafter can be regarded as a failure, and the test of the DUT may be stopped thereafter.
The fail register 11 may be cleared only once at the start of the test. DU stored in the fail register 11
FIG. 4 shows a conceptual diagram of good (PASS) and bad (FAIL) for each T and each frequency.

In FIG. 4, as an example, the test frequency is set to 100 M
Hz, 125 MHz, 133 MHz, 150 MHz, 166 MHz, and 200 MHz. Here, in the test of 100 MHz, all DUTs 25i are PA
SS (good), only DUT 25 ₁ has F in 125 MHz test
AIL (poor) to have, DUT25 ₁ is regarded as a subsequent fail. In the 133 MHz test, only the DUT 25i failed. In the 200 MHz test, all DUTs failed.
L. These PASS / FAIL are set to fail register 1
When the value is stored in "1", the fail register 11 is initially cleared and is "0". Therefore, it is preferable to set the value to "1" when the total fail signal is transmitted.

FIG. 5 shows an example of a configuration embodying the concept of FIG. The fail register 11 has a single flip-flop for each DUT 25i or a register in which a plurality of stages of flip-flops corresponding to the number of frequency tests are cascaded. The total fail signal from the fail signal generator 38 is set for each frequency test. The data content of the fail register 11 is transferred to the failure analysis memory 42 at the time of a memory fetch control signal from the failure analysis memory control unit 41.

When the fail register 11 is a single flip-flop, data is transferred to the failure analysis memory 42 every time one clock frequency test is completed. Also, a register having a capacity corresponding to the number of frequency tests, for example, a FIFO
If an O register or the like is used, all data is transferred at once after all clock frequency tests are completed. Either may be used.
As shown in FIG. 5, data is stored in the failure analysis memory 42 as in the conceptual diagram of FIG.

FIG. 3 shows a measurement flowchart according to an example of the present invention. This flowchart shows a case where all data is transferred after one clock frequency test is completed using a single flip-flop for the fail register 11. Therefore, the capacity of the fail register 11 is D
Only the number of UTs 25i is sufficient, and only a few words or less are required. Compare with the measurement flowchart of FIG. 8 of the prior art. In the prior art, the determination 103 as to whether or not a failure has occurred on a DUT basis,
At the time of ES, memory writing 106 was performed. The memory writing was performed simultaneously with the pattern address and the pattern count, but the failure analysis was performed at this stage because the memory capacity was relatively small. After the failure analysis, it moved to the next step.

In the present invention shown in FIG. 3, if it is determined 203 as to whether or not a failure has occurred on a DUT basis, the result is set 204 in a fail register. The conventional failure analysis is omitted. That is, at the time of the clock frequency selection test, the failure is not analyzed for each failure, and only the phenomenon is recorded to continue the test. And all DUTs failed 205
In the case of, and in the case of the pattern end 207, the memory writing 206 is performed, and when the determination of the test end 208 of all frequencies is YES, the test end 209 is reached. Thereafter, the DUT 25i is sorted according to the test data.

FIG. 2 shows another embodiment which is effective in practical use. The difference will be described with reference to FIGS. The configuration of FIG. 1 has an excellent function in the clock frequency selection test. The configuration of FIG. 7 of the related art is excellent in failure analysis for other tests, for example, a pass / fail test of a logic pattern. Therefore, a signal switch 12 is additionally provided so that both tests can be performed.

The signal switch 12 is supplied with a total fail signal, a pattern address signal and a pattern count signal for each DUT. Then, in the clock frequency selection test, the signal switch 12 is switched so that only the total fail signal in DUT units is
To perform the above-described clock frequency selection test. During other tests, the signal switch 12 is switched to
The conventional test is performed by directly supplying the unit total fail signal, the pattern address signal, and the pattern count signal to the failure analysis memory 42.

The failure analysis memory control unit 41 controls the taking in of the contents of the fail register 11 into the failure analysis memory 42 at the end of the frequency selection test at the time of the clock frequency selection test, and the total failure signal of the DUT unit at the time of another test. And the pattern address signal and the pattern count signal are taken into the failure analysis memory 42. Therefore, not only the clock frequency selection test but also all tests can be performed at high speed.

[0030]

As has been described in detail above, the present invention provides a conventional logic semiconductor test apparatus in which a small-capacity fail register 11 of several words or less is added in front of the failure analysis memory 42, thereby achieving high-speed operation. Clock frequency selection test can be performed.

Further, a signal switch 12 is provided to switch between a total fail signal, a pattern address signal, and a pattern count signal in units of DUT, so that only the total fail signal is stored in the fail register at the time of the clock frequency selection test, and at the time of another test. The three signals are directly stored in the failure analysis memory 42. Therefore, all tests can be performed and high-speed tests can be performed. The present invention is put to practical use and its effect is great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of another embodiment of the present invention.

FIG. 3 is a measurement flowchart of one embodiment of the present invention.

FIG. 4 shows D stored in a fail register 11 of the present invention.
It is a conceptual diagram of good / bad for every UT25i and every frequency.

FIG. 5 is a configuration diagram of an example of good / bad for each DUT 25i and each frequency stored in the fail register 11 and the failure analysis memory 42 according to the present invention.

FIG. 6 is a block diagram of a basic example of a semiconductor logic test apparatus.

FIG. 7 shows a failure analysis memory unit 39 required for conventional failure analysis.
FIG. 2 is an internal configuration diagram of an example of a pattern generator 31.

FIG. 8 is a DUT measurement flowchart that also performs analysis of a clock frequency selection test according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Failure analysis memory unit 11 Fail register 12 Signal switch 25i (i = 1 to n) DUT (device under test) 27, 27i (i = 1 to n) DUT insertion unit 30 Control device (test processor) 31 Pattern generation Device 32 reference clock generator 33 timing generator 34i (i = 1 to n) waveform shaper 37i (i = 1 to n) pattern comparator 38 fail signal generator 39 failure analysis memory unit 40 failure detection unit 41 failure analysis memory Control unit 42 Failure analysis memory 50 Sequence control unit 51 Pattern data memory 52 Control data memory

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Claims (2)

[Claims] 1. The same test signal is applied to a plurality of DUTs, and a logical pattern of a response signal from the plurality of DUTs and an expected value pattern from a pattern generator are logically compared by respective pattern comparators. Register in the failure analysis memory of the failure analysis memory unit for performing a clock frequency selection test for a simultaneous measurement test, a fail register which is provided at the preceding stage of the failure analysis memory and stores a total fail signal for each DUT. And a failure analysis memory control unit for taking in the contents of the fail register into the failure analysis memory when the frequency selection test is completed, and a failure analysis memory control unit. 2. The same test signal is applied to a plurality of DUTs, and a logical pattern of a response signal from the plurality of DUTs and an expected value pattern from a pattern generator are logically compared by respective pattern comparators. In the failure analysis memory of the failure analysis memory section to perform failure analysis, and also to perform a clock frequency selection test. A signal switch that receives signals and transmits only the total fail signal to the fail register during the clock frequency selection test, and switches the received signal directly to the failure analysis memory during other tests, and a DUT unit from the signal switch A fail register that receives and stores the total fail signal of At the time of the wave number selection test, when the frequency selection test is completed, the contents of the fail register are fetched into the failure analysis memory, and at the time of other tests, the total failure signal, the pattern address signal, and the pattern count signal of the DUT unit are transmitted at the time of the total failure signal. And a failure analysis memory control unit for performing a loading control to the failure analysis memory.