JP2002033782A - Demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulation circuit which is less likely to be hardly affected by adjacent signals. SOLUTION: A received quadrature modulated signal 301 is demodulated by a demodulation circuit 1, having a quadrature demodulation function, and after the adjacent signal is removed from a baseband by an LPF composed of VCF 11 and 13, capable of varying a cutoff frequency, the signal is modulated again by a modulation circuit 2 which has quadrature modulation function. Then, after a BPF is constituted and the adjacent signal has been removed, demodulating operation is regularly performed by a demodulation circuit 3, having quadrature demodulation function. Since a baseband signal is provided by this demodulation circuit 3, an LPF for adjacent signal removal is easily provided. Therefore, when demodulating an arbitrarily desired receive wave, resistance to the influence of the adjacent signal is enhanced. Since the same signals, as the local signal of the demodulation circuit having the quadrature demodulation function for regular demodulation, are used for the respective local signals of the demodulation circuit having the quardature demodulation function comprising the BPF and the modulation circuit having the quadrature modulation function, a similar effect for demodulating the arbitrarily desired receive wave in a receiving frequency band is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit, and more particularly to a demodulation circuit for demodulating a quadrature-modulated received signal with a local signal quadrature signal.

[0002]

2. Description of the Related Art FIG. 13 shows a configuration example of a conventional receiver of this type.
Shown in The received signal 301 is an LPF (low pass filter)
The output 302 is input to an HPF (high-pass filter) 41. This HPF output 303 is L
Unnecessary signals in frequency bands other than the reception band are removed by the PF 40 and the HPF 41. The signal 303 from which unnecessary signals in frequency bands other than the reception band have been removed is supplied to the mixer 42.
And converted into frequency by local signal 327 (304).
Is done.

If the frequency of the received signal is represented by fc and the frequency of the frequency-converted local signal is represented by fLO = f (C + i), the mixer output will be one of the frequencies converted into fi and f (2C + i). Unnecessary signals other than the received signal are further removed by a BPF (Band Pass Filter) 43 having fi as the center frequency (305). Here, a specific frequency will be described as an example. fc = 480 MHz, fLO = 761
MHz, the frequency of the mixer output is fi = 281
MHz and f (2C + i) = 1721 MHz. here,
The signal of f (2C + i) = 1721 MHz is removed by the BPF 43.

The output 305 of the BPF 43 is adjusted in signal level by the variable gain amplifier 45 to an input level within a specified range of the demodulation circuit (306), and is input to the demodulation circuit 46. In the demodulation circuit 46, the signal is branched into two by a HYB (hybrid) 461 and supplied to the demodulators 462 and 463. In each of these demodulators, a BB (baseband) signal 30 demodulated by local signals orthogonal to each other is used.
7,308.

The local signal of the demodulation circuit 46 branches the output 323 of the voltage controlled oscillator 58 into two at the HYB 465, and one of the two is shifted in phase by π / 2 by the π / 2 shifter 464. The demodulated BB signals 307 and 308 are
The signal is amplified at 48 (309, 310) and input to RX LPFs (reception low-pass filters) 49, 50. RXL
The bandwidth of the PFs 49 and 50 is such that the signal transmission loss is 0.1 dB.
If it is less than or equal to, the LPF needs to be 1.5 times or more of the band of the received signal.

Outputs 311 and 3 of RX LPFs 49 and 50
The signal level and offset (OFS) voltage are adjusted by amplifiers 51 and 52 and input signals 313 and 314 of A / D (analog-digital) converters 53 and 54 are provided.
Becomes In the A / D converter, digital signals 315 and 316 converted by the sampling clock 317
Are input to a digital processing unit 55 having the functions of a digital filter / phase information extraction circuit / clock recovery circuit / level detection circuit / error correction circuit, and then output as demodulated data 318 and demodulated clock 319.

The phase information 320 extracted by the phase information extracting circuit in the digital processing section 55 is converted into an analog voltage 321 by a D / A (digital-analog) converter 56, and the voltage is controlled by a voltage controlled oscillator via a loop filter 57. 58
Of the control voltage 322. The detection voltage 324 signal detected by the level detection circuit is converted to an analog voltage by the D / A converter 59, and is converted to (3) through the loop filter 73.
25) The signal is input to the AGC (automatic gain control) control circuit 60 and becomes the AGC control voltage 326.

The local signal 327 is obtained by level-amplifying the output signal 328 of the voltage controlled oscillator 61 by the amplifier 44. The output 328 of the voltage controlled oscillator 61 is input to the frequency divider 65, and the output 333 of the reference frequency oscillator 66 is input to the frequency divider 64. The setting signals 334 are set as follows so that the output frequency of the voltage controlled oscillation circuit becomes a desired frequency.
Is set by

The output frequency of the voltage controlled oscillator 61 is fLO, the frequency of the frequency divider 65 is N, the frequency of the frequency divider 64 is M (N and M are positive integers), 66
If the oscillation frequency is fR, the values of N and M are set so that fR / M = fLO / N. The output 331 of the frequency dividing circuit 65 and the output 332 of the frequency dividing circuit 64 are compared in phase by the phase comparing circuit 63.
It becomes a control signal 329 of the voltage controlled oscillation circuit 61 via the filter 62.

FIG. 14 shows a digital processing unit 55 shown in FIG.
An example is shown below. In FIG. 15, input received demodulated data 315 and 316 are converted to digital filters 110 and 1 respectively.
11 removes unnecessary waves other than the received signal and shapes the waveform. The frequency characteristics of the digital filter are equivalent to the spectrum of the received signal. Phase information 320 is extracted from the waveform-shaped data by the phase information extraction circuit 112. Here, the phase information extraction circuit 11
2 shows an example using Costas Loop,
The details will be described later.

The reproduction clock 712 extracts a clock frequency component from a signal 713 obtained by full-wave rectifying the digital filter output 703 or 704 by a full-wave rectifier circuit 114-3 by a tank filter 114-2, and outputs a voltage-controlled oscillator 114-1. Is obtained by performing the above control.

The digital filter outputs 703 and 704 are input to the error correction circuit 113, and after error code correction, become demodulated data 318 and a demodulated clock 319. The digital filter output 704 is output to the detection circuit 115-.
The output signal detected at 1 becomes a detection voltage 324.

FIG. 15 shows another example of the conventional demodulation circuit.
In the example of the conventional demodulator shown in FIG. 13, a forced sweep circuit is added to extend the range of receiving a desired signal. Only the differences from the example of the demodulator of FIG. 13 will be described below. The phase information signal of the output 322 of the loop filter 57 and the output 3 of the sawtooth wave generation circuit 71
13 is different from the example of FIG. 13 in that a sawtooth wave 340 obtained by converting 39 into an analog signal by a D / A converter 72 is added by an adder 67 to form a control signal 341 of a voltage controlled oscillator 58.

The control circuit 69 supplies a clock 337 to the counter circuit 70, and the counter circuit 70 counts the clock and sends a value 338 to the sawtooth wave generation circuit 71. The sawtooth wave generation circuit 71 holds the value, and outputs a D / A converter 72
Output to The control circuit 69 controls by changing or stopping the speed of the clock 337 applied to the counter circuit 70. This control is based on the judgment signal 23 output from the sweep judgment circuit.
9. An example of a determination method in the sweep determination circuit 68 will be described.

The error correction circuit in the digital processing unit 55
The error pulse 335 and the level detection signal 336 obtained from the level detection circuit are input to the sweep determination circuit 68. In the sweep determination circuit 68, the level detection signal 336 is compared with a predetermined threshold value. If the level detection signal 336 is lower than the predetermined threshold value, the clock frequency is set to f1 when sweeping is performed.
The clock frequency generated from the control circuit 69 is f2. Here, it is assumed that f1> f2. FIG. 16 shows an example of the output waveform of the sawtooth wave generation circuit at the time of sweeping, during synchronization establishment, and at the time of synchronization establishment, respectively.

The number of error correction pulses 335 is counted at regular intervals, the number is compared with a predetermined threshold value, and when the number of pulses becomes smaller than the threshold value, the clock generated from the control circuit 69 is stopped. Let it.

FIG. 17 shows the relationship between the control voltage of the voltage controlled oscillator of the conventional demodulator shown in FIGS. 13 and 15 and the output frequency of the voltage controlled oscillator. FIG. 17A shows the relationship between the control voltage of the voltage controlled oscillator and the output frequency of the voltage controlled oscillator in the phase locked loop. That is, ± Δ
Following up to the range of fi, synchronization can be established.

FIG. 17 (B) shows a control voltage vs. voltage controlled oscillator output frequency characteristic in the case of having a forced pull-in function by a sawtooth wave. By increasing the amplitude of the control voltage of the voltage-controlled oscillator by means of a sawtooth wave, the amplitude of the output frequency of the voltage-controlled oscillator is increased, and the pull-in range for a desired received signal is increased. Note that FIG.
In (A) and (B), {V '> △ V, {fi'>}
fi.

[0019]

In FIG. 4A,
The figure shows a case where the reception signal 301 is S, the reception bandwidth is 80 MHz in addition to the desired reception wave, and 533 waves of 60 Kbps signals are arranged at 75 KHz intervals on both sides of the reception signal in that band. The received signal S is

[0020]

(Equation 1) θ = 0, 90, 180, 270 °. Assuming that the local signal 327 is 2cos (ωc + ωi) t (2), the mixer output 304S 'is given by the formula (1) × (2)
From the formula,

[0021]

(Equation 2) Becomes

The center frequency of the BPF 43 is 2πfi = ωi
FIG. 18 shows a case where the residual of the adjacent wave is 60 waves on both sides of the frequency-converted reception frequency. Then
The output signal 305S ″ of the BPF 43 is

[0023]

(Equation 3) Becomes

Here, the first problem is that other signals adjacent to the desired signal in the reception band interfere with the demodulation of the desired signal, and the quality of data demodulated from the received signal deteriorates. Become. The reason is that if the total allowable reception power of the mixer input is exceeded, an intermodulation called IM (Intermodulation) occurs inside the mixer, which is a non-linear circuit, and the desired wave to be received jumps into the band. is there.

The second problem is that it is necessary to produce a local signal for frequency-converting an arbitrary signal desired to be received in a reception frequency band to a predetermined frequency. For this purpose, a synthesizer must be provided. Therefore, the signal pass band of the BPF to be inserted after the frequency conversion needs to be at least twice the same band as the band of the desired signal to be received. The reason is that a frequency shift of the converted signal occurs due to the frequency stability of the synthesizer. Also, the delay characteristic of the BPF affects the desired reception wave.

The third problem is that after frequency conversion, S
Although adjacent signals are removed as much as possible by a BPF such as an AW filter (Surface Acoustic Waves Filter), the same problem as the first problem occurs in a demodulation circuit due to an adjacent wave signal that cannot be removed. The reason for this is that it is difficult for a BPF centered on the converted frequency to achieve a characteristic of removing all but the desired wave to be received.

An object of the present invention is to convert a desired reception signal in a reception frequency band to a predetermined frequency and convert it to a BPF.
Instead of removing adjacent signals, demodulate and convert to baseband signals once, and remove adjacent signals with a variable cut-off frequency LPF composed of a baseband signal band VCF (voltage control filter) or the like. Then, by modulating again, a band variable BPF is configured to provide a demodulation circuit that is less affected by adjacent signals.

[0028]

According to the present invention, first demodulating means for demodulating a quadrature-modulated received signal with a quadrature signal of a local signal and converting the demodulated signal into a baseband signal is provided. Provided to eliminate the waves,
Variable cut-off frequency low-pass filter means whose cut-off frequency can be controlled by an external control signal, modulation means for modulating the filter output with a quadrature signal of the local signal, and demodulation of the modulated output again with the quadrature signal of the local signal A second demodulating means, and a frequency synthesizer means which can set the local signal in accordance with the frequency of an arbitrary desired reception signal in a reception signal band, and the center frequency is variable by this frequency synthesizer. A demodulation circuit having a bandpass filter function is obtained.

And a control means for controlling a reference frequency of the frequency synthesizer means using phase information extracted from demodulated data corresponding to a demodulated output by the second demodulator means. The local signals of the modulating means and the second demodulating means have a frequency which is 1/2 of that of the local signal of the first demodulating means.

The operation of the present invention will be described. A quadrature-modulated received signal is demodulated using a demodulation circuit having a quadrature demodulation function, adjacent signals are removed using a variable cut-off type LPF composed of a VCF or the like in the baseband, and then the quadrature modulation function is performed again. A band variable BPF is formed by modulating the signal with a modulation circuit having a frequency band. After removing adjacent signals, a demodulation operation is performed by a demodulation circuit having a regular quadrature demodulation function. Since the baseband signal is generated by a demodulation circuit having a quadrature demodulation function, the variable cutoff frequency LPF for removing adjacent signals can be configured as a VCF (voltage control filter) or the like, which is easy to realize. Therefore, when demodulating an arbitrary desired reception wave, there is a strong tolerance against the influence of an adjacent signal.

The local signals of the demodulation circuit having the quadrature demodulation function and the modulation circuit having the quadrature modulation function constituting the band variable BPF are local signals of the demodulation circuit having the quadrature demodulation function for normal demodulation. By using the same as
The same effect is obtained for demodulating any desired reception signal in the reception frequency band.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. The receiver according to one embodiment of the present invention shown in FIG. 1 includes a variable gain amplifier 10 for setting the level of a received signal 301, a quadrature demodulation circuit 1 for demodulating the amplified output 202 and converting it to a baseband signal, Variable cut-off frequency LPFs 11 and 1 constituted by a VCF (voltage control filter) or the like for removing adjacent signals and unnecessary waves from the converted baseband signal without affecting a desired signal to be received.
3 (including a circuit part of a control function for this VCF control), amplifiers 12 and 14 for setting the level and offset adjustment of the baseband signal from which adjacent signals and unnecessary waves have been removed, and their amplified outputs , A variable gain amplifier 15 for setting the level of the modulated wave, a quadrature demodulator 3 for demodulating the amplified output again, and the effect of the demodulated output on the desired reception wave. LPFs 16 and 18 for removing adjacent signals and unnecessary waves without providing
, Amplifiers 17 and 19 for level setting and offset adjustment of the LPF output, A / D converters 53 and 54 for digitizing the level setting output, and digital for digital processing with the digital signals 315 and 316 as inputs. And a processing unit 55.

Note that the digital processing unit 55 is provided in FIG.
Like the conventional examples shown in FIGS. 3 and 15, it is assumed that they have a digital filter function, a phase information extraction function, a clock recovery function, an error correction function, and a level detection function.

Further, a receiver according to an embodiment of the present invention comprises:
In order to control the gain of the variable gain amplifiers 10 and 15, A
It has a GC control circuit 60, a loop filter 73, and a D / A conversion circuit 59. Further, a frequency synthesizer for generating the same local signal for the demodulation circuits 1 and 3 and the modulation circuit 2 is provided. This frequency synthesizer includes a voltage controlled oscillator 5, a voltage controlled oscillator 58 for a synthesizer reference frequency, and , Loop filters 6 and 57, a phase comparator 7, frequency dividers 8 and 9, and a D / A converter 56, and has a phase locked loop configuration.

In such a configuration, the operation of the receiver according to one embodiment of the present invention will be described. In this example, a four-phase demodulator receiver will be described as an example. The received signal 301 is adjusted to a specified input level of the demodulation circuit 1 by the variable gain amplifier 10 and becomes a demodulation circuit input signal 202. The demodulation circuit 1 has a quadrature demodulation circuit configuration, and specific examples of the circuit are shown in FIGS. In both FIGS. 2A and 2B, the demodulation circuit input signal 202 is branched into two by the HYB 84. The two branched signals 402 and 403 are demodulators 81 and
82 is input. The demodulator 82 uses the local signal 408, and the demodulator 81 uses the local signal 415 having a phase difference of 90 degrees from the local signal 408 to generate the baseband signal 40.
5,404.

The local signal 406 is split into two by the HYB 83, one of which becomes a local signal 408 of the demodulator 82. The other side 407 is input to the voltage control π / 2 phase shifter 80 and becomes a local signal 415 having a phase difference of 90 degrees from the local signal 408.

In FIG. 2A, a multiplier 87 multiplies local signals 415 and 408 having a phase difference of 90 degrees from each other.
The multiplier output 411 passes through the loop filter 86 and the output 410 is input to the voltage control circuit 85. Voltage control circuit 8
5, the control signal 409 of the voltage control π / 2 phase shifter 80
The phase error at the time of frequency change is corrected by forming a loop.

In FIG. 2B, the correction value of the voltage control π / 2 phase shifter 80 when the frequency changes is stored in the storage circuit 89. A storage signal 413 read out for each frequency by an I / O (INPUT / OUTPUT) signal 414 is converted to an analog voltage 412 by a D / A converter 88 and input to a voltage control circuit 85. Voltage control π /
By using the control signal 409 of the two-phase shifter 80, the phase error at the time of frequency change is corrected.

FIG. 3 shows an example of the voltage controlled π / 2 phase shifter circuit 80 in FIG. This circuit includes a fixed phase shift circuit 90, a variable voltage capacity capacitor 91, and capacitors 92-1 and 92-2. Here, 9
A description will be given taking a 0 degree phase shifter as an example. Voltage control π /
The local signal 407 input to the two-phase shifter is first input to the fixed phase shift circuit 90. In the fixed phase shift circuit 90, the phase shift amount is first shifted by (90-α) degrees. The signal 418 phase-shifted by (90-α) degrees is passed through a capacitor 92-1 and further the remaining α-degree phase-shifted by a variable capacitor 91, passes through a capacitor 92-2, and is a signal 415 phase-shifted by 90 degrees. Becomes

The variable capacitor 91 has a voltage control π /
The capacitance is controlled by the control signal 409 of the two-phase shifter, and the α degree phase is controlled by the capacitance. The value of α is determined by the phase range that can be varied by the capacity of the voltage variable capacitor.

Now, in FIG. 1, the received signal 201 is
When the reception bandwidth is set to 80 MHz in addition to the desired reception wave, and 533 waves of 60 Kbps signals are arranged on both sides of the reception signal at intervals of 75 Kbps within the band, and the total reception signal is S (FIG. 4A) FIG. 2 shows a diagram of the total received signals in the band), and the above equation (1) is obtained.

The local signal 408 is sin (ωct + θ ′) (5) The local signal 415 is cos (ωct + θ ′) (6), and the output 404 of the demodulation circuit 1 is P = (1 ) Formula ×
(5), and the output 405 of the demodulation circuit 1 is Q =
Formula (1) × Formula (6). Therefore,

[0043]

(Equation 4) It is expressed as

FIG. 4B shows a waveform diagram of the output signal of the demodulation circuit 1. The baseband signals 404 and 405 converted by the demodulation circuit 1 are subjected to VCFs 11 and 13 to remove adjacent signals and unnecessary waves other than the desired signal. FIG. 4C shows characteristics of the reception filters 11 and 13 which are the VCF filters. The frequency characteristics of the receiving filters 11 and 13 are low-pass filtering characteristics, and the desired signal to be received does not lose power due to the frequency characteristics of the filters.
The cutoff frequency is set to about 1.3 to 1.5 times or more of the band of the desired reception signal.

FIG. 5 shows a circuit example of a variable cut-off frequency type LPF (low-pass filter) constituted by a VCF (voltage control filter) as the first-stage reception filter circuits 11 and 13 in FIG. . FIG. 5 shows an example of a voltage control filter constituted by an active filter. However, it is apparent that various modifications are possible without being limited to this circuit example.

CV1 to CV5 are connected in series to the capacitors C1 to C5 of this circuit, respectively, and the control voltage CONT1 is controlled.
Is CV4, CONT2 is CV2, CONT3 is CV1,
CV3, CV5 Voltage Capacitance The capacitance of the variable capacitor is varied from the minimum value to the maximum value, and the values of CV1 to CV5 are changed to CV1MIN to MAX, CV2MIN to MAX, CV3 MIN to M, respectively.
AX, CV4MIN to MAX, CV5MIN to MAX.

Resistors R1 = R2 = R3 = R4 = R5 =
R ', the value of each capacitor is Cn, and the normalized capacitor value is Can (n = 1, 2, 3, 4, 5). The cut-off frequency of this LPF is: fc = Can / (2π · Cn' R) Here, Cn 'is the parallel connection capacitance value of Cn and CVn. C4 '= C4 ・ CV4 / (C4 + CV4) C5' = C5 ・ CV5 / (C5 + CV5) By making the value of CVn variable, LPF
Can be obtained as a voltage control filter for obtaining a cutoff frequency of

The memory 149 stores CVs that provide several types of cutoff frequencies arbitrarily defined in the range of fcmin to fcmax.
The data of the D / A converter of the control voltage value from 1 to CV5 is stored. The value of the memory is set in the D / A converters 150-1 to 150-3 by the control signal CONT, and the capacities of CV1 to CV5 are set, thereby setting several types of cutoff frequencies arbitrarily set. Now, assuming that the range of the cut-off frequencies fcmin to fcmax is fc in FIG. 6, to further change the range, R1 to R5 and N resistors R1-1 to R1-N, R2-1 to R2-N, R3 respectively. -1 to R3-
N, R4-1 to R4-N, and R5-1 to R5-N are connected in parallel, and the on / off switches SW1-1 to SW are respectively connected.
1-N, SW2-1 to SW2-N, SW3-1 to SW3-N, SW
4-1 to SW4-N and SW5-1 to SW5-N are provided.

A function of turning on / off each switch by the control signals SW1 to SWN is provided. Now, SW
When 1-1, SW2-1, SW3-1, SW4-1 and SW5-1 are turned on, the respective resistances are as follows: R1 → R1 ′ = R1 · R1-1 / (R1 + R1-1). , R2 → R2 ', R3 → R3', R4 → R
4 ', R5 → R5', the cutoff frequency fc is high, and can be set in the range of fc1 as shown in FIG.

When the switch SW2 is turned on, the cutoff frequency of the voltage control filter can be sequentially set up to the range of fcN, such as the range of fc2. The row of switches to be turned on is N
Any number of columns. Further, the differential amplifier 13
2, 133 are provided with gains of 1 + R7 / R61 + R9 / R8 by R6 to R9, respectively, in order to correct the power passing loss of the present LPF.

FIG. 4C shows that the adjacent signal of the received signal is 1
The graph shows the reception filter characteristic when each wave remains.
The LPF is set to be at least about 1.5 times the band of the desired reception signal. At this time, if two adjacent waves remain, the output of the LPF 11 is set to P 'and the output of the LPF 13 is set to Q'.

[0052]

(Equation 5) Are represented respectively.

The outputs of the LPFs 11 and 13 from which adjacent signals other than the desired signal and unnecessary waves have been removed are output to the amplifiers 12 and 1 respectively.
4, the level and offset are adjusted to become input signals 207 and 208 of the modulation circuit 2. The modulation circuit 2 is a quadrature modulation circuit, and examples of the circuit are shown in FIGS.
Shown in 7 (A) and 7 (B), the modulation circuit input signal 2
07 and 208 are input to modulators 93 and 94.

The modulator 94 performs two-phase modulation with the local signal 606, and the modulator 93 performs two-phase modulation with the local signal 609 having a phase difference of 90 degrees with respect to the local signal 606. The modulated waves 603 and 604 that have been subjected to the two-phase modulation are input to the addition circuit 95 and added to form a four-phase modulated wave 209. Local signal 606
Is divided into two by the HYB 96, one of which is a modulator 9
4 of the local signal 607. The other one 608 is input to the voltage control π / 2 phase shifter 97 and becomes a local signal 609 having a phase difference of 90 degrees with respect to the local signal 607.

In FIG. 7A, the local signals 607 and 609 having a phase difference of 90 degrees from each other are multiplied by the multiplier 100, and the output 612 of the multiplier passes through the loop filter 99 and the output 611 of the multiplied voltage is applied to the voltage. Input to the control circuit 98. The voltage control circuit 98 makes a control signal 610 of the voltage control π / 2 phase shifter 97 and forms a loop to correct a phase error at the time of frequency change.

In FIG. 7B, the correction value of the voltage control π / 2 phase shifter 97 when the frequency changes is stored in the storage circuit 102. The storage signal 614 read for each frequency by the I / O signal 613 is converted into an analog voltage 615 by the D / A converter 101 and input to the voltage control circuit 98. Voltage control π / 2 phase shifter 9 by voltage control circuit 98
7, the phase error at the time of frequency change is corrected. As an example of the voltage control π / 2 phase shifter circuit, the circuit shown in FIG. 3 can be used, and its operation is as described above.

Here, assuming that the re-modulated two-phase modulated wave 603 is P ″, P ″ = (5) × (9), and that the re-modulated two-phase modulated wave 605 is Q ″,
Q ″ = Equation (6) × Equation (10).

[0058]

(Equation 6) It is represented by

Output 6 obtained by adding these two two-phase modulated waves
If 05 is S ′, then S ′ = Equation (11) + Equation (12).

[0060]

(Equation 7) Becomes FIG. 4D shows an output signal of the modulation circuit 2.

The level of the four-phase modulated wave 209 is adjusted by the variable gain amplifier 15 to a predetermined input level of the demodulation circuit 3, and becomes an input signal 210 of the demodulation circuit 3. The demodulation circuit 3 performs the same operation as the demodulation circuit 1 and converts the signals into baseband signals 211 and 212 again. After conversion, LP
The signals are input to F16 and F18 and are signals from which the remaining adjacent signals other than the desired reception wave and unnecessary waves have been removed. These LPF
The frequency characteristics of 16 and 18 are cut-off frequencies of 1.5 to 2 times or more the band of the desired reception signal so that power loss does not occur in the desired reception signal due to the frequency characteristics of the filter.

FIG. 8 shows an example of the circuits of the LPFs 16 and 18. Here, the passive filter configuration of each of the Butterworth filter and the Chebyshev filter is described as an example, but it is needless to say that the passive filter configuration may be configured by an active filter.

The signals from which the remaining adjacent signals other than the desired reception wave and unnecessary waves have been removed are adjusted in level and offset by the amplifiers 17 and 19, and become input signals to the A / D conversion circuits 53 and 54. In the A / D conversion circuits 53 and 54, digital signals 315 and 316 are sampled by the sampling clock 317,
5 is input. The configuration of the digital processing unit 55 is the same as the configuration shown in FIG.

Referring again to FIG. 14, the demodulated digital signals 315 and 317 are input to digital filters (reception filters composed of digital filters) 110 and 111 as digital filter input signals. Here, only the desired reception wave is the sampling clock 7
12, and becomes data P703 and data Q704.

Here, the output 211 of the demodulation circuit 3 is set to P ″ ′.
Then, since this is expressed by Expression (13) × Expression (5),

[0066]

(Equation 8) Becomes

The digital filter output signal 703 is set to PP
Then, PP = (１ ／) sin (θ−θ ′) (14)

If the output 212 of the demodulation circuit 3 is Q ″ ′, this is expressed by the equation (13) × (6).

[0069]

(Equation 9) Becomes

When the digital filter output signal 704 is QQ
Then, QQ = (１ ／) cos (θ−θ ′) (14)

The data PP and QQ are input to a phase information extracting circuit 112 (here, a Costas loop is described as an example). Output of Adder 112-1 and Subtractor 1
Since the output of the multiplier 112-4 from the output of 12-2 is [(PP + QQ) · (PP−QQ)] = PP ² −QQ ² , PP ² = ｛(1/4) sin (θ −θ ′)｝ ² (16) QQ ² = {(1/4) cos (θ−θ ′)} ² (17)

Therefore, PP ² −QQ ² = {(1/4) sin (θ−θ ′)} ² − {(1/4) cos (θ−θ ′)} ² = − (1/16) cos (2θ−2θ ′) (18)

The output of the multiplier 112-3 is PP · Q
Since it is Q, from equation (14) × (15), PP · QQ = {(1/4) sin (θ−θ ′)} · {(1/4) cos (θ−θ ′)} = (1/32) sin (2θ−2θ ′) (19)

The phase information signal 320 is represented by PP * QQ * (PP
²⁻ QQ ² ), and from the equation (18) × (19), PP · QQ · (PP ² −QQ ² ) = {− (1/16) cos (2θ−2θ ′)} · {( 1/32) sin (2θ−2θ ′)｝ = − (1/1024) {sin (4θ−4θ ′) + sin θ}, which is the phase information 320.

The phase information 320 is converted to an analog voltage by the D / A converter 56 and then input to the loop filter 57. The sin θ of the phase information is a loop filter 57.
Therefore, the output of the loop filter 57 becomes-(1/1024) ｛sin (4θ−4θ ′) (20) and becomes the control signal of the voltage controlled oscillator 58.

The output of the voltage controlled oscillator 5 is supplied to demodulation circuits 1 and 3
And a local signal of the modulation circuit 2, and is input to the frequency dividing circuit 8 as a feedback signal. The output of the voltage control transmitter 58 is input to the frequency dividing circuit 9. Dividing circuit 8
Each of the frequency dividing numbers of 9 and 9 is set in the following manner so that the output frequency of the voltage controlled oscillator 5 becomes a desired frequency.
Is set by

Now, let the output frequency of the voltage controlled oscillator 5 be f
v, the division number of the frequency divider 8 is N, and the frequency of the frequency divider 9 is M
(Where N and M are positive integers), assuming that the oscillation frequency of the voltage controlled oscillator 58 is fR, the values of N and M are set so that fR / M = fv / N.

The output of the frequency divider 8 and the output of the frequency divider 9 are compared in phase by the phase comparator 7, and the phase-compared signal becomes the control signal of the voltage controlled oscillator 5 via the loop filter 6. The output of the voltage controlled oscillator 5 is branched into three by the HYB 4 and becomes local signals of the demodulation circuits 1 and 3 and the modulation circuit 2. The demodulation circuits 1 and 3 and the modulation circuit 2 must use the same local signal.

FIG. 9A shows a desired reception signal. FIG. 9B shows a reception signal when the same local signal is used for the demodulation circuits 1 and 3 and the modulation circuit 2. FIG. 9C shows a received signal when the same local signal is not used for the demodulation circuits 1 and 3 and the modulation circuit 2. In this case, the frequency error of the received signal and the frequency error of the local signal are shown. Occurs, and a folded signal is generated, so that the signal cannot be correctly demodulated.

The reproduced clock 712 shown in FIG. 14 is a signal 71 obtained by subjecting the output 703 or 704 of the digital filter 111 to full-wave rectification by the full-wave rectifier circuit 114-3.
3, only the clock frequency component is supplied to the tank filter 11.
4-2, and can be obtained as a control signal 714 of the voltage controlled oscillator 114-1.

The output 703 of the digital filter 111,
704 is input to the error correction circuit 113, and after error code correction, becomes the demodulated data 318 and the demodulated clock 319. A detection voltage 324 obtained by detecting an output 704 of the digital filter 111 by a detection circuit 115-1 constituting a level detection circuit 115 is converted into an analog voltage by a D / A converter 59, and then the loop filter 73 is turned on. Via A
It is input to the GC control circuit 60. The AGC control circuit 60 outputs control signals for the variable gain amplifiers 10 and 15, respectively, and controls these two variable gain amplifiers 10 and 15.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a diagram showing the configuration of the second embodiment, and the same parts as those in FIG. 1 are denoted by the same reference numerals. Only differences from the configuration of the first embodiment of FIG. 1 will be described. The use of the local signals of the demodulation circuits 1 and 3 and the modulation circuit 2 in common with the output of the voltage controlled oscillator 5 is the same as in the first embodiment of the present invention. A frequency dividing circuit 21 for dividing the output by 出力 is provided, and the local signals of the modulating circuit 2 and the demodulating circuit 3 are operated at a frequency of を the local signal of the demodulating circuit 1.

The output of the voltage controlled oscillator 5 is
Branch. One of the two branches is input to a 1/2 frequency divider 21 and the other is a local signal of the demodulator 1. 1 /
The output of the divide-by-2 circuit 21 is input to the HYB 22 and branched into two. One of the two branches becomes a local signal of the modulation circuit 2, and the other becomes a local signal of the demodulation circuit 3.

The received signal is demodulated by the demodulation circuit 1 and the LPF
When adjacent waves and unnecessary waves are removed and re-modulation is performed in steps 11 and 13, the modulation frequency is set to の of the received signal to prevent interference of the received signal during normal demodulation. There is an advantage that it can be prevented.

FIG. 1 shows a third embodiment of the present invention.
This will be described with reference to FIG. 11, the same parts as those in FIG. 1 are denoted by the same reference numerals. Compared to the first embodiment shown in FIG. 1, a forced sweeping circuit is provided to expand the range for receiving a desired reception signal. Only the changes from the first embodiment of FIG. 1 will be described. The phase information signal output from the loop filter 57 and the output from the sawtooth wave generation circuit 35 are D / A
The difference is that the sawtooth wave converted into an analog signal by the converter 34 is added by the adder 33 and used as a control signal of the voltage controlled oscillator 58.

The control circuit 37 supplies a clock to the counter circuit 36. The counter circuit 36 counts the clock and sends the value to the sawtooth wave generation circuit 35. Sawtooth wave generation circuit 3
5 holds the value and outputs it to the D / A converter 34. The control circuit 37 controls to change or stop the speed of the clock supplied to the counter circuit 36. This control is performed by a determination signal output from the sweep determination circuit 32.

An example of a determination method in the sweep determination circuit 32 will be described. Error pulse 335 obtained from an error correction circuit / level detection circuit in digital processing section 55
(See FIG. 13), the level detection signal 336 is input to the sweep determination circuit 32. In the sweep determination circuit 32, when the level is not detected by the level detection signal 336, the clock frequency is f1 as the sweep, and when the level is detected, the clock frequency generated from the control circuit 37 is f2. Here, it is assumed that f1> f2.

FIG. 16 shows an example of the output waveform of the sawtooth wave generating circuit at the time of sweeping, during synchronization establishment, and at the time of synchronization establishment. Further, the error correction pulses 235 are counted at regular intervals, the number is compared with a predetermined threshold value, and when the number of pulses becomes smaller than this threshold value, the clock generated from the control circuit 37 is stopped.

FIG. 17A shows the control voltage versus voltage output characteristics of the voltage controlled oscillator of the voltage controlled oscillator of the embodiment shown in FIG. 11, and the control voltage vs. voltage of the voltage controlled oscillator in the phase locked loop. 3 shows a control oscillator output frequency characteristic. That is, fc (shown as fi in the figure,
(which can be read as fc) to the extent of ± Δfc, and synchronization can be established. FIG. 17B shows a control voltage vs. voltage controlled oscillator output frequency characteristic in the case of having a forced pull-in function by a sawtooth wave. By increasing the amplitude of the control voltage of the voltage controlled oscillator by the sawtooth wave, the amplitude of the output frequency of the voltage controlled oscillator is expanded, and the pull-in range for a desired received signal is increased. Here, in FIG. 17, ΔV ′> ΔV, Δf
It is assumed that c ′> △ f (shown as fi ′ in the figure, but can be read as fc ′).

Further, a fourth embodiment of the present invention will be described with reference to FIG. 12, the same parts as those in FIGS. 1, 10 and 11 are denoted by the same reference numerals. In the present embodiment, a forced sweep circuit is provided in the second embodiment shown in FIG. 10 in the same manner as in FIG. The operation of this embodiment is equivalent to that of the third embodiment shown in FIG.

[0091]

The first effect of the present invention is that IM (Inte
That is, it is possible to prevent interference with the demodulation operation of a desired reception signal due to intermodulation called rmodulation). The reason why the first effect can be obtained is that since the frequency conversion method is not used, an intermodulation called IM due to saturation of the input level of the mixer due to an adjacent wave other than a desired wave to be received by the mixer does not occur.

The second effect of the present invention is that the effect of removing adjacent waves other than the desired reception signal is high. The reason for this second effect is that the frequency conversion method is not used,
The received signal is demodulated by a demodulation circuit using the same local signal, converted to a baseband signal, then unnecessary waves such as adjacent waves are removed by an LPF, and modulation is performed again using the same local signal. This is because a demodulator having the same function as the BPF can be obtained by demodulating the modulated wave again using the same local signal.

That is, by converting the signal once to a baseband signal, an L signal for removing unnecessary waves such as adjacent waves is used.
PF can be easily realized. Since the configuration is such that unnecessary waves such as adjacent waves are removed by the LPF, the effect of removing unnecessary waves such as adjacent waves other than the signal pass band is large.

A third effect of the present invention is that a similar effect can be obtained for an arbitrary received signal having a desired reception band. The reason that this effect can be obtained is that after demodulating in a demodulation circuit using the same local signal and converting it to a baseband signal, unnecessary waves such as adjacent waves are removed by an LPF and the same local signal is used. By performing modulation again and demodulating the modulated signal again using the same local signal, B
This is because a demodulator having a function equivalent to that of the PF is obtained, and a frequency synthesizer capable of setting a local signal to an arbitrary frequency in the reception band is used for the local signal of the demodulation circuit / modulation circuit.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a four-phase demodulation circuit used in the present invention.

FIG. 3 is a diagram showing an example of a voltage controlled π / 2 phase shifter used in the present invention.

FIG. 4 is a diagram illustrating an example of signals of respective units according to the embodiment of the present invention.

FIG. 5 shows a first-stage receiving filter (VCF1) used in the present invention.
It is a figure which shows the example of a circuit of (13).

FIG. 6 is a diagram showing a setting range of cutoff frequencies of VCFs 11 and 13;

FIG. 7 is a diagram showing a configuration example of a four-phase modulation circuit used in the present invention.

FIG. 8 is a diagram illustrating a circuit example of LPFs 16 and 18;

FIG. 9 is a diagram illustrating each example of a received signal and a received signal when demodulated correctly and not correctly demodulated;

FIG. 10 is a circuit block diagram of a second embodiment of the present invention.

FIG. 11 is a circuit block diagram of a third embodiment of the present invention.

FIG. 12 is a circuit block diagram of a fourth embodiment of the present invention.

FIG. 13 is a diagram illustrating an example of a configuration of a conventional receiver.

14 is a diagram illustrating an example of a digital processing unit 55 in FIG.

FIG. 15 is a diagram illustrating another example of the configuration of the conventional receiver.

FIG. 16 is a diagram illustrating an example of an output waveform of the sawtooth wave generating circuit at the time of sweeping and at the time of establishing synchronization.

FIG. 17 is a diagram showing a relationship between a control voltage of a voltage controlled oscillator and an output frequency.

FIG. 18 is a diagram illustrating an example of an output signal of a frequency conversion circuit.

[Explanation of symbols]

 1,3 demodulation circuit 2 modulation circuit 4,22 HYB (hybrid circuit) 5,58 voltage controlled oscillator 6,57 loop filter 7 phase comparator 8,9 frequency divider 10,15 variable gain amplifier 11,13 VCF 12,14 , 17, 19 Level setting amplifier 16, 18 LPF 21 1/2 frequency divider 32 Sweep control circuit 33 Adder 34, 56, 59 D / A conversion circuit 35 Saw wave generation circuit 36 Counter circuit 37 Control circuit 53, 54 A / D conversion circuit 55 Digital processing unit 60 AGC control circuit

Claims (3)

[Claims] 1. A first demodulation means for demodulating a quadrature-modulated received signal with a quadrature signal of a local signal and converting the demodulated signal into a baseband signal, and an external control unit for removing unnecessary waves from the baseband signal. A cut-off frequency variable low-pass filter means whose cut-off frequency is controllable by a signal; a modulation means for modulating the filter output with a quadrature signal of the local signal; and a demodulator for demodulating the modulation output again with the quadrature signal of the local signal. Two demodulation means, the local signal, including a frequency synthesizer means that can be set in accordance with the frequency of any desired reception signal of the reception signal band,
A demodulation circuit having a band variable band-pass filter function in which a center frequency is variable by the frequency synthesizer. 2. The apparatus according to claim 1, further comprising control means for controlling a reference frequency of said frequency synthesizer means using phase information extracted from demodulated data corresponding to a demodulated output by said second demodulation means. The receiver according to claim 2. 3. The demodulation circuit according to claim 1, wherein the local signals of the modulating means and the second demodulating means have a frequency which is half the frequency of the local signal of the first demodulating means.