JP2002033662A - Digital/analog converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital/analog converter that realizes an analog regenerative signal with suppressed zero cross distortion caused by the inversion of the MSB without the need for taking an arithmetic delay into account. SOLUTION: A bipolar digital signal is limited to a valve of (full scale-1) and divided into two digital data by using a lookup table where the MSB of data has the same sign. By performing analog subtraction of two outputs from the digital/analog converter each other, generation of the analog regenerative signal is realized where zero cross distortion caused by the inversion of the MSB is suppressed without the need for taking an arithmetic delay into account.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter (digital-to-analog converter), and more particularly to a maximum weighting bit suitable for reproducing analog signals of digital audio and waveform shaping in communication. The present invention relates to a D / A converter capable of suppressing distortion called zero crossing that occurs when (hereinafter, referred to as MSB) is inverted.

[0002]

2. Description of the Related Art In D / A conversion used in digital audio and transmitters, a bipolar digital signal having a zero point at half the maximum amplitude is used as data. On the other hand, in the binary weight method, the MSB is inverted when conversion is performed across the zero point, and distortion generally called zero cross is generated. When the amplitude of the two-pole digital signal is small, the number of occurrences of zero crossings increases, which causes a large noise.

FIG. 13 shows a configuration of a D / A converter using a conventional technique. In the figure, 500 is an input detection circuit for detecting the magnitude of the input amplitude, 510 is an offset generator for generating an offset corresponding to the amplitude detected by the input detection circuit 500, and 520 is input data and an offset generator This is a digital adder for aligning the phases of data generated from 510 and adding them. Also, 21
Reference numerals 0 and 220 denote D / A converters (A) and D / A converters (B) for digital-to-analog conversion of data from the digital adder 520 and the offset generator 510, respectively. An analog subtractor for subtracting analog signals output from the / A converters 210 and 220 to generate an analog signal waveform corresponding to the original digital input data.

In the configuration shown in FIG. 13, digital input data is input to an input detection circuit 500, and a reproduction level having a full scale of 0 dB is detected. The offset generator 510 adds an offset to the input digital data according to the absolute value of the reproduction level. That is, the offset is 0 dB when the playback amplitude level is -6 dB or more, the offset is -12 dB when the playback amplitude level is -12 dB or more and less than -6 dB, and the offset is when the playback amplitude level is -18 dB or more and less than -12 dB. Is -18 dB, and thereafter, logarithmic offset subdivision is performed until necessary. Offset generator 510
The offset data generated by the digital adder 52
0, the offset data and the digital input data are added in phase and input to the D / A converter (A) 210. The offset data has the same phase as the input data to the D / A converter (A) 210,
The signal is input to the A converter (B) 220. The signals converted from digital to analog signals by the D / A converter (A) 210 and the D / A converter (B) 220, respectively, are subtracted by the analog subtractor 200 to obtain a reproduced analog signal of digital data. Is output as

As a D / A converter having such a configuration, for example, there is a technique disclosed in Japanese Patent Application Laid-Open No. 1-1198830.

[0006]

However, in the above-mentioned prior art, since the offset is generated in accordance with the absolute value of the reproduction level, the above-mentioned minus level of -6 dB or more, that is, the maximum detection level division However, when reproducing minus data having a large amplitude level, inversion of the MSB occurs. Also, to generate input data to the D / A converter based on the input data and the offset data,
Digital adder 520 and D / A converter (B) 22
Before inputting 0, a configuration that takes into account the delay of the operation is required.

[0007] The present invention has been made in view of the above points,
The purpose is to eliminate the need for considering the delay of the operation, and to realize an analog reproduction signal that suppresses zero-cross distortion generated by inversion of the MSB.
A conversion device is provided.

[0008]

Generally SUMMARY OF THE INVENTION, two-pole digital output D / A converter of n bits is around zero, positive side 2 ^{(n-1) -1,} the negative side is 2 ^{(n-1 )}
Can take values up to. In the present invention, when the D / A converter is actually used, it is assumed that the amplitude is set to be equal to plus or minus about the zero (hereinafter, zero plus minus 2 ^(n-1) is referred to as the actual use range). D / A converter (A) 210, D / A
Considering that the input data to the A converter (B) 220 can be calculated in advance, By using a lookup table to generate input data to the D / A converter (A) 210 and the D / A converter (B) 220 for one input data,
The calculation of the D / A converter input value data by calculation is eliminated, and the D / A converter (A) 210 and the D / A converter (B) 2
1. 20 data can be generated simultaneously; By making the MSBs of the input data to the D / A converter (A) 210 and the D / A converter (B) 220 all the same in the table, the MSB generated when performing the D / A conversion is obtained. A configuration is adopted in which zero cross distortion due to inversion is prevented from occurring in the actual use range.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a D / A converter according to a first embodiment of the present invention. In FIG. 1, reference numerals 210, 220, and 200 denote the components shown in FIG. They are equivalent D / A converter (A), D / A converter (B), and analog subtractor.

In FIG. 1, reference numeral 100 denotes a look-up table.
1 is an address for extracting data in the look-up table, 102 is a memory area for storing data input to the D / A converter (A) 210, and 103 is input to the D / A converter (B) 220 Indicates a memory area for storing data. At this time, the number of bits of digital input data and the D / A output from each data memory area
The operation will be described on the assumption that the number of bits of the converter input data is equal to the number of bits of the digital input data and the digital input data is equal to the address 101 from which the data of the lookup table 100 is extracted.

When digital input data to be reproduced is input to look-up table 100, D / A converter (A) data memory area 102 stored at address 101 of look-up table 100 equal to the digital input data, and , D / A converter (B) The data is read from the data memory area 103, and in the respective D / A converters (A), (B) 210, 220, the read data is converted from the digital signal. It is converted to an analog signal. Two D / A converters (A),
(B) The analog signals output from 210 and 220 are
The digital data is subtracted by the analog subtractor 200 and output as a reproduced analog signal of digital data.

The data of the lookup table 100 used in the present embodiment satisfies the following two conditions. The range of input data is from minus full scale -1 to plus full scale, and the MSB bits of each address and each D / A converter input data memory are all the same; The relationship between the D / A converter (A), the D / A converter (B), and the input data is as follows: (Digital input data) = (D / A converter (A) input data) − (D / A converter ( B) input data).

FIG. 5 shows an example of creating the above-mentioned look-up table 100 for a 4-bit input.

Note that the analog subtractor 200 in FIG. 1 may be replaced with an analog adder. In this case, the data in the lookup table 100 is: The range of input data is from minus full scale -1 to plus full scale, and the MSB bits of each address and each D / A converter input data memory are all the same; The relationship between the D / A converter (A), the D / A converter (B), and the input data is as follows: (Digital input data) = (D / A converter (A) input data) + (D / A converter ( B) Input Data) The above conditions should be satisfied.

Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram illustrating a D / A according to a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a conversion device.

In this embodiment, attention is paid to the fact that each address and the MSB bit of each D / A converter input data memory are all the same, and in order to reduce the memory usage in the look-up table. , The D / A converter (A) 21 which is set equally in the same table
0, MSB of input data to D / A converter (B) 220
Is given as constant data (DC value) from outside the lookup table 100 ′. At this time, the input data to the D / A converter (A) 210 and the D / A converter (B) 220 for the n-bit width digital input data are stored in the memory in the lookup table 100 '. , Each having data of an n-1 bit width excluding the MSB.

In this embodiment having such a configuration, the data supplied to the two D / A converters (A) and (B) are:
Equally, the data depends on the data in the lookup table memory.

Next, a third embodiment of the present invention will be described. FIG. 3 shows a D / A according to a third embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of the conversion apparatus, which is the same as the configuration shown in FIGS. 1 and 2 except for the following points, and therefore only different parts will be described.

In FIG. 3, reference numeral 110 denotes a look-up table capable of outputting two or more data sets for one input data, and 120 denotes a D / A converter (A) immediately before the digital input data. ) 210, a previous input holding register for holding data input to the D / A converter (B) 220, 130 is a lookup table 1
A candidate data storage register 140 for holding the data set output from 10 is a data comparison and determination circuit that determines the current input data by comparing candidate data with the previous input data.

FIG. 6 shows an example of the look-up table 110 shown in FIG. In FIG. 6, 111 is an address corresponding to input data, 112 is a data memory area for storing a first candidate that can be input to the D / A converter (A) 210, and 113 is a D / A converter ( B) 22
A data memory area 114 for storing a first candidate that can be input to 0, a data memory area 114 for storing an m-th candidate that can be input to the D / A converter (A) 210, 1
15 is an m-th m-th input that can be input to the D / A converter (B) 220
The figure shows a data memory area for storing a candidate.

The look-up table 110 has an output data area capable of outputting a plurality of sets of data for one input digital data. Assuming that the data width written to the memory of the lookup table 110 is 4 bits and the number of sets of input data candidates is 2,
FIG. 7 shows an example of the data.

As shown in FIG. 7, the input data set is given a priority in the data memory area so that it can be used in determining candidates. Further, at this time, data that can be input is insufficient because the MSBs in the look-up table are all the same, especially when the amplitude level of the reproduction signal is large. In addition, it is necessary to devise a method such as adding a circuit for preventing the operation when the data is small (in FIG. 7, the data of the first data set and the second data set in the digital input data 1111 and 0001 are used). Sets of data are set equal).

FIG. 8 is a detailed block diagram of the data comparison and decision circuit 140 shown in FIG. In FIG. 8, 600 is a data comparator for comparing input D / A converter input data with data input to the previous D / A converter, and 650 is a current comparator using the comparison data. A decision circuit 660 for deciding data to be applied to the D / A converter is generated from the candidate data and the result from the candidate decision circuit 650 to generate output data to be input to the current D / A converter. The circuit is shown.

FIG. 9 shows a data comparator 600 shown in FIG.
FIG. 3 is a block diagram showing an example of the configuration of FIG. In FIG.
610, 610 are EXOR circuits for performing a logical operation of exclusive OR (hereinafter referred to as EXOR) on the previous input data and the present input candidate data in each D / A converter for each bit, and 620 is a D / A converter. This is a digital addition circuit for adding the EXOR output for each two bits of the / A converter (A) 210 and the D / A converter (B) 220.

The output of the data comparator 600 indicates the total bit change between the previous input data and the current input data. If the occurrence of zero crossing is proportional to the bit weight, when this data is small, the bit change This means that the zero cross generated by the second and lower weight bits generated is small.

The operation of the present embodiment is as follows. A predetermined number of sets of D / A converters (A) 21 in the look-up table 110 are used for input digital data.
0, the data of the D / A converter (B) 220 is input to the candidate data storage register 130, and the immediately preceding data of the target data is stored in the previous input data holding register 120. For each set of input candidates, the data comparator 600
, And compares the result with the previous input data, and inputs the result to the candidate decision circuit 650.

The candidate decision circuit 650 selects (1) a data having a small value from the input comparison data. (2) When there are a plurality of items having the same value in the above (1), the determination is made based on the priority of the data set.

The result of the decision by the candidate decision circuit 650 described above is input to the output generation circuit 660, which selects from the data from the candidate register, and selects the data from the D / A converter (A) 21.
0, output as input data of the D / A converter (B) 220.

Next, a fourth embodiment of the present invention will be described. FIG. 4 shows a D / A according to a fourth embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a conversion device. This embodiment has a configuration in which a circuit for intentionally selecting a different data set when digital input data has the same value continuously is added to the configuration described in the third embodiment. I have.

In FIG. 4, reference numeral 150 denotes an amplitude change detection circuit for inputting a flag to the data comparison and determination circuit 160 when the same continuous data is input for a set number of times or more by observing a change in an input signal. , 160, in addition to the function described in the comparison determination circuit 140 of the third embodiment, when detecting an output flag indicating the continuation of the same data from the amplitude change detection circuit 150, sets a different data set from the last time. This is a comparison determination circuit having a function of giving priority to the output processing.

Regarding the operation, a portion different from the operation of the third embodiment will be described. The input digital data is input to the amplitude change detection circuit 150 at the same time as being input to the look-up table 110. When the amplitude change detection circuit 150 detects the same continuous data equal to or greater than a preset value, it indicates continuation. The flag is sent to the data comparison decision circuit 160. Data comparison circuit 16
In the candidate determination circuit 650 within 0, seeing the establishment of the flag,
A different data set from the previous data set is output, giving priority to the comparison determination procedure of the third embodiment. As a result, a zero-cross is intentionally generated, and a false contour generated from the continuation of the same data is prevented from being generated.

In general, a signal waveform reproduced when an input value does not change continuously has a false contour which is not included in the original waveform. Conventionally, a technique called dither, which eliminates false contours after analog filtering by intentionally adding minute random data of high frequency to digital data, is used. By adopting the configuration of the fourth embodiment, by outputting different data with respect to the same input data, a slight difference in output value caused by zero crossing is generated, and a pseudo dither effect is provided. be able to.

FIG. 10 is a diagram showing the occurrence of a false contour when dither is not considered, and the effect of pseudo-dither when using the present embodiment.

In FIG. 10, reference numeral 800 denotes an ideal reproduced analog signal waveform, and reference numerals 810 and 830 denote a D / A converter output waveform when dither is not considered and a reproduced analog waveform after filtering, respectively. I have. On the other hand, 820 and 840 are the D / A converter output waveforms when the pseudo dither of the present embodiment is performed, respectively.
5 shows a reproduced analog waveform after filtering.

FIGS. 11 and 12 show a D / A converter (A) 2
10. A processing flow according to the fourth embodiment for setting input data to the D / A converter (B) 220 by software is shown for reference.

[0036]

As described above, in the first embodiment of the present invention, zero-cross distortion due to inversion of the MSB does not occur in the range of input data from minus full scale -1 to plus full scale. Since the data from the look-up table to the D / A converter (A) 210 and the D / A converter (B) 220 are provided at the same time, it is not necessary to consider the delay required for the operation. Further, the second embodiment of the present invention has an effect of reducing the amount of memory used in the first embodiment.

In the third embodiment of the present invention, output data is sent to two or more sets of D / A converters (A) 210 and D / A converters (B) 220 for one input data. Has a look-up table capable of outputting the input data to at least one continuous D / A converter (A) 210 and D / A converter (B) 220 before the input data. By comparing a plurality of input candidates with the data of the previous input, it is possible to always take data with less zero crossings, and at the same time, combine the circuit for detecting the same continuous data shown in the fourth embodiment. Thus, a dither effect can be obtained in a pseudo manner. An advantage at this time is that it is not necessary to add random data that causes signal quality degradation in the dither unnecessary area.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a D / A conversion device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a D / A conversion device according to a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a D / A conversion device according to a third embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a D / A conversion device according to a fourth embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an example of the contents of a lookup table according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a configuration of a look-up table in the third and fourth embodiments of the present invention.

FIG. 7 is an explanatory diagram showing an example of the contents of a look-up table in the third and fourth embodiments of the present invention.

FIG. 8 is a block diagram showing details of a data comparison and decision circuit in FIG. 4;

FIG. 9 is a block diagram showing an example of a configuration of a data comparator in FIG.

FIG. 10 is an explanatory diagram showing an effect in the fourth embodiment of the present invention.

FIG. 11 is a processing flowchart for setting input data to a D / A converter according to a fourth embodiment of the present invention.

FIG. 12 is a processing flowchart for setting input data to a D / A converter according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram illustrating a conventional D / A converter for reducing zero crossing due to inversion of MSB.

[Explanation of symbols]

 100, 100 ', 110 Look-up table 200 Analog subtractor 210 D / A converter (A) 220 D / A converter (B) 120 Previous input data holding register 130 Candidate data storage register 140, 160 Data comparison and decision circuit 150 Amplitude change detection circuit 500 Input detection circuit 510 Offset generator 520 Digital adder

Claims (4)

[Claims] 1. An analog signal is reproduced by using two D / A converters and one analog subtractor or analog adder in order to perform D / A conversion (digital-analog conversion) of a two-pole digital signal. In a digital-to-analog converter, the range of digital input data is limited to the full scale of the D / A converter-1, and one set of (digital human data) = (D / A converter (A) input data) − (D / A converter (B) input data) or (digital input data) = (D / A
A converter (A) input data) + (D / A converter (B) input data) can output an input data set to two D / A converters, and can output data sets to the respective D / A converters. A digital-to-analog converter having a look-up table in which the polarities of the largest weight bits of input digital data are all equal. 2. An analog signal is reproduced using two D / A converters and one analog subtractor or analog adder in order to perform D / A conversion (digital-analog conversion) of a two-pole digital signal. In a digital-to-analog converter, the range of digital input data is limited to the full scale of the D / A converter-1, and one set of (digital human data) = (D / A converter (A) input data) − (D / A converter (B) input data) or (digital input data) = (D / A
A lookup table capable of outputting a set of input data to two D / A converters, which is (converter (A) input data) + (D / A converter (B) input data); Digital-to-analog conversion characterized in that the maximum weighting bits for the two D / A converters are applied with an external DC voltage so that the polarities of the maximum weighting bits of the input digital data to the converters are all equal. apparatus. 3. A digital-to-analog converter that reproduces an analog signal using two D / A converters and one analog subtractor or analog adder when D / A converting a two-pole digital signal. , For one set of digital input signals, multiple sets of two D
A look-up table capable of outputting input data candidates to the A / A converter, and a lookup table for the D / A converter for the input data.
A circuit for holding the previous input data and a comparison between the immediately preceding input data to the D / A converter and the input candidate data, and
A data comparison and determination circuit for determining an input value to two D / A converters and outputting one data set. 4. The circuit according to claim 3, wherein a circuit for detecting the same continuous digital input data and two D / A conversions of data different from the previous input data with priority when the same continuous data is detected. A digital-to-analog conversion device comprising: