JP2002033414A - Terminal forming method for wafer level csp - Google Patents

Terminal forming method for wafer level csp

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Publication number
JP2002033414A
JP2002033414A JP2000215535A JP2000215535A JP2002033414A JP 2002033414 A JP2002033414 A JP 2002033414A JP 2000215535 A JP2000215535 A JP 2000215535A JP 2000215535 A JP2000215535 A JP 2000215535A JP 2002033414 A JP2002033414 A JP 2002033414A
Authority
JP
Japan
Prior art keywords
copper foil
electrode
gold
gold bump
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000215535A
Other languages
Japanese (ja)
Other versions
JP3870013B2 (en
Inventor
Naoto Nakatani
直人 中谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Avionics Co Ltd
Original Assignee
Nippon Avionics Co Ltd
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Filing date
Publication date
Application filed by Nippon Avionics Co Ltd filed Critical Nippon Avionics Co Ltd
Priority to JP2000215535A priority Critical patent/JP3870013B2/en
Publication of JP2002033414A publication Critical patent/JP2002033414A/en
Application granted granted Critical
Publication of JP3870013B2 publication Critical patent/JP3870013B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
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Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a terminal of a wafer level CSP by using a pointed gold bump formed by a wire bonding method as it is without leveling and further forming a package electrode directly on the bump. SOLUTION: A sharp gold bump is formed on an aluminum electrode or copper electrode on the top surface of a semiconductor wafer by a conventional method using a wire bonder, and copper foil with resin is laminated by being heated and pressed. Here, the copper foil thickness is about 75 μm and the resin thickness is 50 to 60 μm depending upon the size of the bump, the sharp tip of the gold bump is pressed and crushed by the copper foil, and the gold bump and copper foil are fixed with epoxy resin while electrically connected by press contacting. Then an electrode is formed by etching the copper foil.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体ウェハレベル
ＣＳＰ（チップサイズパッケージ）の製造方法に係り、
端子形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer level CSP (chip size package).
It relates to a terminal forming method.

【０００２】[0002]

【従来の技術】電子機器の高性能化、高機能化、小型化
が進むなかで、半導体部品はウェハレベルでの配線幅、
配線長短縮化と高集積化、パッケージレベルでの配線長
短縮化と小型化が図られ、ウェハレベルとパッケージレ
ベルの双方で急速に半導体部品の高速化、小型化が進ん
でいる。半導体パッケージレベルの進化には、チップ電
極とインタポーザまたは実装基板の電極との接続を目的
とした各種バンプ製造方法および該バンプによる接続方
法の発明、改善が貢献している。このバンプ製造方法の
一つにワイヤボンディングによる方法が広く知られてい
る。従来のワイヤボンディングによるバンプ製造方法の
一例を図３に示す。図３において、ワイヤボンダのキャ
ピラリ先端９から金線１０を所定長だけ出し、該金線１
０先端をトーチ１１からの放電で球状に丸め、その後キ
ャピラリを下降して前記金線１０先端球状部を電極１２
に接触させ、加熱と超音波振動により電極１２に接合す
る。キャピラリを引き上げながら金線１０をクランパ１
３で固定することで金線１０を引きちぎり、先端が尖っ
た金バンプ１４が形成される。図では省略するが、通
常、前記で形成された先端が尖った金バンプ１４は、レ
ベリングツールによって上面を平坦にし、同様に形成し
た複数の金バンプの高さを揃えるレベリングを行なう。2. Description of the Related Art With the advancement of high performance, high functionality, and miniaturization of electronic equipment, semiconductor parts are required to have a wiring width at a wafer level.
Shortening of wiring length and high integration, shortening of wiring length at package level and downsizing have been achieved, and the speed and miniaturization of semiconductor components at both wafer level and package level are rapidly progressing. The invention of the various bump manufacturing methods for connecting the chip electrodes to the electrodes of the interposer or the mounting substrate and the invention and the improvement of the connection method using the bumps have contributed to the evolution of the semiconductor package level. As one of the bump manufacturing methods, a method by wire bonding is widely known. FIG. 3 shows an example of a conventional bump manufacturing method by wire bonding. In FIG. 3, a predetermined length of a gold wire 10 is protruded from a capillary end 9 of a wire bonder.
The tip of the gold wire 10 is rounded into a spherical shape by the discharge from the torch 11, and then the capillary is lowered to connect the spherical portion of the gold wire 10 to the electrode 12.
And joined to the electrode 12 by heating and ultrasonic vibration. Pull up the capillary while pulling up the capillary 1
By fixing at 3, the gold wire 10 is torn off, and a gold bump 14 having a sharp tip is formed. Although not shown in the drawing, the gold bump 14 having a sharp tip formed as described above is usually leveled by using a leveling tool to flatten the upper surface and to make the heights of a plurality of similarly formed gold bumps uniform.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、図３に
示した従来のバンプ製造方法は、金線を引きちぎった時
の先端形状の長さにばらつきが生じることと、尖った先
端をレベリングする時にバンプ形状に歪みが生ずるとい
う欠点がある。また、レベリングを終えた金バンプはそ
のままパッケージ電極にせず、インタポーザ等を介して
パッケージ電極に接続されるのが一般的である。本発明
は、上記課題を解決するためになされたもので、前記の
引きちぎってできた尖った先端の金バンプをレベリング
せずにそのままし使用し、さらに、該バンプに直接パッ
ケージ電極を形成することでウェハレベルＣＳＰの端子
を形成する方法を提供する。However, in the conventional bump manufacturing method shown in FIG. 3, the length of the tip shape when the gold wire is torn off varies, and when the sharp tip is leveled, the bump is not formed. There is a disadvantage that the shape is distorted. In general, the gold bump after leveling is not directly used as a package electrode, but is connected to the package electrode via an interposer or the like. The present invention has been made in order to solve the above-mentioned problems, and it is intended to use the above-mentioned torn gold bumps at the sharp tips without leveling as they are, and to further form a package electrode directly on the bumps. Provides a method of forming a terminal of a wafer level CSP.

【０００４】[0004]

【課題を解決するための手段】請求項１のウェハレベル
ＣＳＰの端子形成方法は、ウェハレベルでの端子形成と
ダイシングによる個体分断で完成するウェハレベルＣＳ
Ｐにおいて、次の工程によることを特徴とする。 イ）半導体ウェハ上の電極にワイヤボンディングで先端
の尖った金バンプを形成し、ロ）樹脂付き銅箔を積層す
ることで該銅箔により前記金バンプ先端を押し潰しなが
ら圧接し、ハ）前記金バンプ上の前記銅箔に電極をエッ
チングで形成し、ニ）前記形成された電極に無電解ニッ
ケルめっきと無電解金めっきを施す。According to a first aspect of the present invention, there is provided a method of forming a terminal of a wafer level CSP, comprising forming a terminal at a wafer level and dividing the individual by dicing.
P is characterized by the following steps. A) forming a gold bump with a sharp tip on the electrode on the semiconductor wafer by wire bonding; b) laminating a copper foil with a resin to crush the gold bump tip with the copper foil and press-contact it; An electrode is formed on the copper foil on the gold bump by etching, and d) the formed electrode is subjected to electroless nickel plating and electroless gold plating.

【０００５】請求項１のウェハレベルＣＳＰの端子形成
方法によれば、先端の尖った金バンプを銅箔押し潰すの
で、複数の金バンプは均一な高さに形成され、同時に、
電極となる銅箔と金バンプは確実に圧接される。また、
電極はエッチングにより形成するので、複数の電極整列
精度がバンプ二段重ね方式よりも安定する。According to the method for forming a terminal of the wafer level CSP of the first aspect, the gold bump having a sharp tip is crushed by a copper foil, so that a plurality of gold bumps are formed at a uniform height.
The copper foil serving as the electrode and the gold bump are securely pressed against each other. Also,
Since the electrodes are formed by etching, the alignment accuracy of the plurality of electrodes is more stable than in the two-stage bump method.

【０００６】請求項２のウェハレベルＣＳＰの端子形成
方法は、ウェハレベルでの端子形成とダイシングによる
個体分断で完成するウェハレベルＣＳＰにおいて、次の
工程によることを特徴とする。 イ）半導体ウェハ上の電極にワイヤボンディングで先端
の尖った金バンプを形成し、ロ）樹脂付き銅箔を積層す
ることで該銅箔により前記金バンプ先端を押し潰しなが
ら圧接し、ハ）前記銅箔を全面エッチングにより除去
し、表面樹脂をエッチバックして前記先端を押し潰され
た金バンプ頭部を露出させ、ニ）表面全面に無電解銅め
っきおよび電解銅めっきを施し前記金バンプ頭部と接続
をとり、ホ）前記金バンプ上の前記銅めっきに電極をエ
ッチングで形成し、ヘ）前記形成された電極に無電解ニ
ッケルめっきと無電解金めっきを施す。According to a second aspect of the present invention, there is provided a method of forming a terminal of a wafer level CSP, wherein the following steps are performed in a wafer level CSP completed by terminal formation at the wafer level and individual separation by dicing. A) forming a gold bump with a sharp tip on the electrode on the semiconductor wafer by wire bonding; b) laminating a copper foil with a resin to crush the gold bump tip with the copper foil and press-contact it; The copper foil is removed by etching over the entire surface, and the surface resin is etched back to expose the head of the gold bump whose tip is crushed. D) The electroless copper plating and the electrolytic copper plating are applied to the entire surface, and the gold bump head is applied. E) forming electrodes by etching on the copper plating on the gold bumps, and f) applying electroless nickel plating and electroless gold plating to the formed electrodes.

【０００７】請求項２のウェハレベルＣＳＰの端子形成
方法によれば、先端の尖った金バンプを銅箔押し潰すの
で、複数の金バンプは均一な高さに形成される。また、
表面樹脂をエッチバックして前記先端を押し潰された金
バンプ頭部を露出させるので、電極となる銅めっきと金
バンプは広い面積でめっき接続される。また、電極はエ
ッチングにより形成するので、複数の電極整列精度がバ
ンプ二段重ね方式よりも安定する。According to the terminal forming method of the wafer level CSP of the second aspect, the gold bump having a sharp tip is crushed by a copper foil, so that a plurality of gold bumps are formed at a uniform height. Also,
Since the surface resin is etched back to expose the head of the gold bump whose top is crushed, the copper plating serving as an electrode and the gold bump are connected by plating over a wide area. Further, since the electrodes are formed by etching, the alignment accuracy of the plurality of electrodes is more stable than in the two-stage bump method.

【０００８】[0008]

【発明の実施の形態】図面を基に本発明を詳細に説明す
る。図１は本発明の一実施形態であるＣＳＰ電極形成工
程を側面模式図で示す。図１（ａ）は、半導体ウェハ１
表面のアルミ電極または銅電極２上に、ワイヤボンダを
使用して従来方法により先端の尖った金バンプ３を形成
した状態を示す。図１（ｂ）は、前記状態のものに、樹
脂付き銅箔（銅箔にエポキシ半硬化樹脂を塗布したも
の）を加熱加圧して積層した状態のものである。銅箔厚
は約７５μｍ、樹脂厚は５０〜６０μｍとし、金バンプ
３の尖った先端部が銅箔５で押し潰され、金バンプ３と
銅箔５が圧接により電気的に接続された状態でエポキシ
樹脂４により固着されるようにする。ここで、使用する
銅箔厚と樹脂厚は、バンプの大きさすなわち電極ピッチ
により上記値から適宜変更して最適値を選定するものと
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic side view showing a step of forming a CSP electrode according to an embodiment of the present invention. FIG. 1A shows a semiconductor wafer 1.
A state in which a gold bump 3 having a sharp tip is formed on a surface of an aluminum electrode or a copper electrode 2 by a conventional method using a wire bonder is shown. FIG. 1B shows a state in which a copper foil with resin (a copper foil coated with an epoxy semi-cured resin) is laminated by heating and pressing on the above-mentioned state. The copper foil thickness is about 75 μm, the resin thickness is 50-60 μm, and the sharp tip of the gold bump 3 is crushed by the copper foil 5, and the gold bump 3 and the copper foil 5 are electrically connected by pressure welding. It is fixed by the epoxy resin 4. Here, the copper foil thickness and the resin thickness to be used are appropriately changed from the above values depending on the size of the bump, that is, the electrode pitch, and the optimum values are selected.

【０００９】次に銅箔５表面にレジストフィルムを貼付
し、電極パターンのマスクフィルムを重ねて露光、現
像、エッチングして図１（ｃ）に示すように銅電極６を
形成する。上記銅電極６に無電解ニッケルめっきおよび
無電解金めっき７を施し、図１（ｄ）に示すように電極
として完成させる。その後、図では省略するが、ダイシ
ングにより個々のＩＣに切断分離してウェハレベルＣＳ
Ｐを完成する。Next, a resist film is stuck on the surface of the copper foil 5, a mask film of an electrode pattern is overlaid, exposed, developed and etched to form a copper electrode 6 as shown in FIG. 1 (c). Electroless nickel plating and electroless gold plating 7 are applied to the copper electrode 6 to complete the electrode as shown in FIG. Thereafter, although omitted in the figure, the wafer level CS is cut and separated into individual ICs by dicing.
Complete P.

【００１０】上記のように金バンプと銅箔を圧接接続す
る方法に対し、金バンプに銅めっきすることで電極を形
成する方法を図２で説明する。図２の（ａ）と（ｂ）
は、図１（ａ）、（ｂ）と同じ工程を採るので説明を省
略する。図２（ｃ）に示すように、積層後銅箔をエッチ
ングにより全て除去し、図２（ｄ）に示すように、エポ
キシ樹脂の一部を粗化、エッチングするエッチバックを
行なう。エッチバックには過マンガン酸などを用いる化
学的方法が容易である。該エッチバックにより、図２
（ｄ）で示すように、先端が潰れた金バンプ頭部が樹脂
から突起して露出するので、後で行なう銅めっきとの接
続面積を増加することができる。図２（ｄ）は、無電解
銅めっき後電解銅めっき８により約７５μｍの銅を付け
た状態を示す。ここで、電極ピッチにより銅めっきの厚
みを減らす方が電極の仕上がり形状が良好になるので、
チップサイズによって最適値を選定することが好まし
い。A method for forming an electrode by plating a copper on a gold bump will be described with reference to FIG. (A) and (b) of FIG.
Adopts the same steps as those in FIGS. 1A and 1B, and thus the description is omitted. As shown in FIG. 2 (c), after lamination, the copper foil is completely removed by etching, and as shown in FIG. 2 (d), etch back is performed to roughen and etch part of the epoxy resin. A chemical method using permanganic acid or the like is easy for etch back. By this etch back, FIG.
As shown in (d), since the head of the gold bump whose tip has been crushed is projected from the resin and exposed, it is possible to increase the connection area with copper plating performed later. FIG. 2D shows a state where about 75 μm of copper is applied by electroless copper plating 8 after electroless copper plating. Here, reducing the thickness of the copper plating by the electrode pitch improves the finished shape of the electrode,
It is preferable to select an optimum value according to the chip size.

【００１１】前記銅めっき後は、図１（ｃ）、（ｄ）の
工程と同様に、レジストフィルム貼付、電極パターン露
光、現像、エッチング、無電解ニッケルめっき、無電解
金めっきを経て電極を形成し、最後にダイシングにより
個々のＩＣに切断分離してウェハレベルＣＳＰを完成す
る。After the copper plating, the electrodes are formed by pasting a resist film, exposing an electrode pattern, developing, etching, electroless nickel plating, and electroless gold plating in the same manner as the steps shown in FIGS. 1 (c) and 1 (d). Finally, the wafer is cut and separated into individual ICs by dicing to complete a wafer level CSP.

【００１２】[0012]

【発明の効果】本発明によれば、ウェハ上の電極に形成
した金バンプが、ＣＳＰを基板へ実装した後の熱ストレ
スに対するストレスリリーフとなるので、接続信頼性の
高い長寿命が保証される。According to the present invention, the gold bump formed on the electrode on the wafer serves as a stress relief against thermal stress after the CSP is mounted on the substrate, so that a long life with high connection reliability is guaranteed. .

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施形態であるＣＳＰ電極形成工程
を側面模式図で示す。FIG. 1 is a schematic side view showing a CSP electrode forming step according to an embodiment of the present invention.

【図２】本発明の二番目の実施例であるＣＳＰ電極形成
工程を側面模式図で示す。FIG. 2 is a schematic side view showing a CSP electrode forming step according to a second embodiment of the present invention.

【図３】従来のワイヤボンディングによるバンプ製造方
法の例を側面模式図で示す。FIG. 3 is a schematic side view showing an example of a conventional bump manufacturing method by wire bonding.

【符号の説明】[Explanation of symbols]

１ 半導体ウェハ ２ アルミ電極または銅電極 ３ 金バンプ ４ エポキシ樹脂 ５ 銅箔 ６ 銅電極 ７ 無電解ニッケルめっきおよび無電解金めっき ８ 無電解銅めっき後電解銅めっき ９ キャピラリ先端 １０ 金線 １１ トーチ １２ 電極 １３ クランパ １４ 金バンプ DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Aluminum electrode or copper electrode 3 Gold bump 4 Epoxy resin 5 Copper foil 6 Copper electrode 7 Electroless nickel plating and electroless gold plating 8 Electroless copper plating after electroless copper plating 9 Capillary tip 10 Gold wire 11 Torch 12 electrode 13 Clamper 14 Gold bump

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 ウェハレベルでの端子形成とダイシング
による個体分断で完成するウェハレベルＣＳＰにおい
て、次の工程によることを特徴とするウェハレベルＣＳ
Ｐの端子形成方法。 イ）半導体ウェハ上の電極にワイヤボンディングで先端
の尖った金バンプを形成し、ロ）樹脂付き銅箔を積層す
ることで該銅箔により前記金バンプ先端を押し潰しなが
ら圧接し、ハ）前記金バンプ上の前記銅箔に電極をエッ
チングで形成し、ニ）前記形成された電極に無電解ニッ
ケルめっきと無電解金めっきを施す。1. A wafer-level CSP completed by individual formation by terminal formation and dicing at the wafer level, wherein the wafer-level CSP is formed by the following steps.
P terminal formation method. A) forming a gold bump with a sharp tip on the electrode on the semiconductor wafer by wire bonding; b) laminating a copper foil with a resin to crush the gold bump tip with the copper foil and press-contact it; An electrode is formed on the copper foil on the gold bump by etching, and d) the formed electrode is subjected to electroless nickel plating and electroless gold plating. 【請求項２】 ウェハレベルでの端子形成とダイシング
による個体分断で完成するウェハレベルＣＳＰにおい
て、次の工程によることを特徴とするウェハレベルＣＳ
Ｐの端子形成方法。 イ）半導体ウェハ上の電極にワイヤボンディングで先端
の尖った金バンプを形成し、ロ）樹脂付き銅箔を積層す
ることで該銅箔により前記金バンプ先端を押し潰しなが
ら圧接し、ハ）前記銅箔を全面エッチングにより除去
し、表面樹脂をエッチバックして前記先端を押し潰され
た金バンプ頭部を露出させ、ニ）表面全面に無電解銅め
っきおよび電解銅めっきを施し前記金バンプ頭部と接続
をとり、ホ）前記金バンプ上の前記銅めっきに電極をエ
ッチングで形成し、ヘ）前記形成された電極に無電解ニ
ッケルめっきと無電解金めっきを施す。2. A wafer-level CSP completed by individual formation by terminal formation and dicing at the wafer level, wherein the wafer-level CSP is formed by the following steps.
P terminal formation method. A) forming a gold bump with a sharp tip on the electrode on the semiconductor wafer by wire bonding; b) laminating a copper foil with a resin to crush the gold bump tip with the copper foil and press-contact it; The copper foil is removed by etching over the entire surface, and the surface resin is etched back to expose the head of the gold bump whose tip is crushed. D) The electroless copper plating and the electrolytic copper plating are applied to the entire surface, and the gold bump head is applied. E) forming electrodes by etching on the copper plating on the gold bumps, and f) applying electroless nickel plating and electroless gold plating to the formed electrodes.
JP2000215535A 2000-07-17 2000-07-17 Wafer level CSP terminal forming method Expired - Fee Related JP3870013B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000215535A JP3870013B2 (en) 2000-07-17 2000-07-17 Wafer level CSP terminal forming method

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Application Number Priority Date Filing Date Title
JP2000215535A JP3870013B2 (en) 2000-07-17 2000-07-17 Wafer level CSP terminal forming method

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JP2002033414A true JP2002033414A (en) 2002-01-31
JP3870013B2 JP3870013B2 (en) 2007-01-17

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004056162A1 (en) * 2002-12-18 2004-07-01 K-Tech Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package
US7964493B2 (en) 2007-12-27 2011-06-21 Shinko Electric Industries Co., Ltd. Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004056162A1 (en) * 2002-12-18 2004-07-01 K-Tech Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package
US7964493B2 (en) 2007-12-27 2011-06-21 Shinko Electric Industries Co., Ltd. Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
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