JP2002033384A - Wiring structure and semiconductor device having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide drastic via wiring connection structure that has superior heat-resistance property, will not depend on the kinds of an insulating film, and can form a reliable wiring system and semiconductor device. SOLUTION: To make a via connected to wide wiring equivalent to connection for narrow wiring near a connection part, and the island of the insulating film is provided near the via in the wide wiring, and the width of wiring connected to the via is narrowed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring structure and a semiconductor device, and more particularly to a wiring structure suitable for high-speed operation and low power consumption and a semiconductor device having the same.

[0002]

2. Description of the Related Art The introduction of copper as a wiring material and the introduction of a low dielectric constant material as an interlayer insulating film have been actively studied in order to miniaturize and speed up semiconductor devices. In addition, for the purpose of flattening at the time of multilayering, CMP (Chemical Mechanical Po
A method of forming a wiring by a damascene method using lishing (chemical mechanical polishing method) is becoming widespread.

FIGS. 1 to 4 are a plan view and a bird's-eye view showing the shape of a copper or aluminum damascene wiring which has been conventionally studied. In an actual device, this wiring is embedded in the insulating film, but the surrounding insulating film is not drawn in this figure.
In the figure, 1 is an upper wiring, 2 is an upper and lower wiring layer connecting portion (via), and 3 is a lower wiring.

[0004]

The number of wiring layers is three to four.
Under the layer or in a state where the wiring size is not very fine (via diameter of about 0.5 μm or more), sufficient characteristics have been obtained even with the wiring structure as shown in FIGS. However, it has been found that there is a problem as multilayering and miniaturization progress. That is, if there is a structure as shown in FIGS. 3 and 4 in which fine vias are connected to a thick (wide) wiring due to the wiring resistance and current density, the above-described connection region is formed in the process of multilayering the wiring. It was found that a problem of preferential deterioration (high resistance) occurred. Even with vias having the same shape, such deterioration hardly occurs in vias connected to thin wirings as shown in FIGS.

In the above-described wiring structure, when the heat treatment method or the method of forming the insulating film or the forming conditions is changed, a change in the quantitative defect rate and the like is observed, but a process capable of obtaining a sufficient margin for obtaining reliable reliability. It was difficult to become. Further, as the miniaturization progresses further, the margin becomes narrower.

An object of the present invention is to provide a drastic improvement which can form a highly reliable wiring structure and a semiconductor device having the same, which are different from the above-mentioned process conditions.

[0007]

The present invention has solved the above-mentioned problems by optimizing a wiring pattern near a via. That is, although the cause of the above-described deterioration phenomenon has not been sufficiently elucidated, there are several possibilities as described below.

(1) The copper in the via is sucked up by the shrinkage of the copper in the wide wiring, a cavity is generated in the via, and the connection portion has a high resistance. That is, shrinkage of copper is a general phenomenon in thin-film metals that, when heat-treated at a high temperature, lattice defects (atomic vacancies / grain boundaries) formed during film formation aggregate to create large defects / voids. However, the ratio of voids formed at this time is constant irrespective of the width of the wiring, but it is considered that the influence of the wide vias on the connected vias is severe because the absolute amount of the voids becomes large.

(2) At the time of heat treatment, the insulating film around the wiring is deformed so as to increase the volume (volume) surrounding the copper wiring, and the copper in the wiring also moves following the deformation to form a void in the via. Form. Here, the deformation phenomenon of the insulating film is particularly remarkable in the case of a film having high stress, and void formation by this mechanism has been reported in aluminum wiring (Reference 1: Y. Sugano et al., Proceedings of International Reliability Physics pp.3
4-38 (1988), Reference 2; K. Hinode et al., IE Trans. On Electron Devices (IEEE Trans. On ED), vol. 36, pp. 1050-1055 (19)
89)). Furthermore, the above-mentioned deformation becomes remarkable in wide wiring,
Alternatively, even with the same amount of deformation, the effect on the electrical characteristics may be significant.

(3) The film quality of copper in a wide wiring or a via connected thereto is poor (many lattice defects), so that deterioration in such a place becomes remarkable.

Although the three possible cases have been described above, the vias connected to the thin wiring have sufficient characteristics. Therefore, even in the via connected to the wide wiring, the narrow wiring is used near the connection with the via. With a structure equivalent to that of the connection, any of the above three possibilities can be dealt with. According to the present invention, an island of an insulating film is provided in the vicinity of a via in a wide wiring to reduce the width of a wiring connected to the via, thereby overcoming a deterioration phenomenon peculiar to the wide wiring.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Embodiment 1> FIGS.
FIG. 3 is a plan view of a wiring structure employing a so-called dual damascene method in which a via 2 and an upper layer (second layer) wiring 1 are simultaneously formed (groove / hole filling and CMP) on a layer copper wiring (not shown). I have.

The interlayer insulating film (not shown) is a typical p-C
VD-SiO ₂ film (Plasma Enhanced Chemical Vapor
Deposition, TEOS (Tetra-Ethoxy Silan)
e) Using a film, p as an etching stop (not shown)
-A CVD-SiN (Silicon Nitride; silicon nitride) film was laminated. The film thickness was set to a via depth of 0.5 μm and a wiring thickness of 0.3 μm.

In the present embodiment, islands 4 of the insulating film are provided in contact with the vias 2 (including a case where a slight gap is formed due to misalignment due to a photo process) as shown in each figure. Although there is no restriction on the shape of the island, it is desirable to form the island as small as possible so that the longitudinal direction in the plan view is parallel to the longitudinal direction of the wiring so that the influence on the wiring resistance is small and the current path is not obstructed as much as possible. .

In the embodiment shown in FIGS. 9 to 12, although not in contact with the via 2, an island 4 of an insulating film having the same shape as the above embodiment is provided near the via 2. FIG. In this embodiment, the degree of high reliability is relatively inferior to the embodiment in which the island 4 is provided in contact with the via 2, but the effect of providing the island 4 on the wiring resistance and the like is smaller than that in the embodiment. Since it can be reduced, it can be used properly according to requirements.

The width of the upper wiring 1 is 5 μm, and the diameter of the via 2 is 3 μm and 0.2 μm.
Table 1 shows the results of evaluating the effects of the present invention by forming TEGs (Test Element Groups; patterns for characteristic evaluation) connected in series.

[0017]

[Table 1]

The above results are summarized as follows. At the initial stage of wiring formation, almost 100% yield is obtained irrespective of the structure. However, when additional heat treatment is performed, a difference in structure becomes apparent. First, the higher the heat treatment temperature and the smaller the via diameter, the more remarkable the deterioration. There are differences depending on how the islands are set up. Although the structure of FIG. 5 has a great improvement effect as compared with the conventional structure, it is not always sufficient for the heat treatment of this time. The larger the area, the closer to the via, the greater the effect.

For this heat treatment, FIGS.
With this structure, sufficient resistance can be ensured. Other structures may be able to cope with lighter heat treatment conditions.

<Embodiment 2> Embodiment of Deterioration by Repeated Heat Treatment In the case where the heat treatment at a high temperature is for a short time or only once or twice, the above structure can be used. However, there are many cases where the wiring is multilayered into five or more layers. Although the wiring structure described in Example 1 is for one layer, this was laminated five times to form a five-layer wiring. That is, the lowermost wiring undergoes at least five heat treatments.

With respect to this heat treatment, the structure shown in FIGS. 6 to 8 described in the first embodiment is significantly deteriorated, and it is necessary to further improve the resistance in an actual device. Therefore, FIG.
As shown in FIGS. 3 to 20, a TEG is formed by stacking five layers of wiring having a structure in which insulating film islands 4 are provided in two or more via directions, and the yield of the first layer via chain is reduced in the same manner as in the previous embodiment. It was measured. Here, each drawing shows a plan view in the case where the via 2 and the second-layer wiring 1 are formed on the first-layer wiring (not shown) as in the above-described embodiment.

Also in this case, a so-called dual damascene method in which a via and an upper wiring are simultaneously formed (groove / hole filling and CMP) is employed. As in Example 1, a TEOS film was used as an interlayer insulating film, and a SiN film was stacked as an etching stop. The thickness of one layer was set to a via depth of 0.5 μm and a wiring thickness of 0.3 μm. Further, in this TEG, a heat treatment is performed at 400 ° C. or less for a total of about 15 minutes at 425 ° C. for about 10 minutes in order to form one layer. No heat treatment was performed before the yield measurement.

In FIGS. 13 to 16, an insulating film island 4 as shown in FIG. 17 to 20 show similar islands of the insulating film 4 provided near the via 2 at a slight distance from the via. FIG.
In the example of FIG. 20, the degree of high reliability is inferior to that in which an island is provided in contact with the via, but the influence of the island on wiring resistance and the like can be further reduced.
In the implementation, it is the same as described above that it can be properly used depending on the request. As in the first embodiment, the width of the upper wiring is set to 5 μm, and the via diameters are set to 0.3 μm and 0.2 μm.
Table 2 shows the results of forming and evaluating a TEG in which 10000 of these were connected in series.

[0024]

[Table 2]

The above results are summarized as follows. As the via diameter is smaller, the deterioration is remarkable and the initial yield is lower.
There is also a difference depending on how the islands are provided, and the structure in FIG. 13 is not much different from the structure in FIG. 6 and does not have sufficient resistance in this process. As shown in FIGS. 14 to 16, the effect is greater for a large-area island placed as close to the via as possible. Sufficient resistance to the heat treatment of this time can be ensured by adopting the structures of FIGS. In some cases, other structures can be used for those having a small number of layers.

<Embodiment 3> FIGS. 21 to 24 are plan views showing a case where a via 2 and a second-layer wiring 1 are formed on a first-layer wiring (not shown), similarly to the above-described embodiment. This embodiment is an example in which, when there are a plurality of vias, islands are provided in as many directions as possible of the vias, and the islands are arranged so as to reduce the influence on the wiring.

A TEG in which five layers of wiring were stacked in the structure shown in FIGS. 21 to 24 was formed, and the yield of the first-layer via chain was measured in the same manner as in the previous embodiment. In this TEG, as a heat treatment for forming a single layer, heat treatment at 400 ° C. or less is performed for a total of about 15 minutes and 425 ° C. for about 10 minutes. No heat treatment was performed before the yield measurement.

Also in this case, a so-called dual damascene method in which a via and an upper wiring are simultaneously formed (groove / hole filling and CMP) is employed. A TEOS film was used as an interlayer insulating film (not shown) as in Example 1, and a SiN film was laminated as an etching stop (not shown). The thickness of one layer was set to a via depth of 0.5 μm and a wiring thickness of 0.3 μm.

The width of the upper wiring 1 is 5 μm, and the diameter of the via 2 is 0.3 μm and 0.2 μm, respectively.
0000 TEGs connected in series were formed and evaluated.
As a result, a yield of about 98% or more was obtained with the structures of FIGS. 20 to 24, and it was confirmed that such an arrangement of islands near the vias was effective for high reliability.

<Embodiment 4> FIGS. 25 to 26 show an example in which, when there are a plurality of vias 2, the islands are arranged so that the deterioration of the electric characteristics due to the formation of the islands is minimized. A plan view in the case where a via 2 and a second-layer wiring 1 are formed on a first-layer wiring (not shown) as in the above-described embodiment is shown. FIGS. 27 to 28 show examples of the arrangement of islands in the case where an insulating film is provided in at least two directions of vias, and one direction is used not as an island but as a wiring end.

A TEG in which five layers of wiring were stacked in the structure shown in FIGS. 25 to 28 was formed, and the yield of the first layer via chain was measured in the same manner as in the previous embodiment. In this TEG, each time one layer is formed, heat treatment is performed at 400 ° C. or less for a total of about 15 minutes and at 425 ° C. for about 10 minutes. No heat treatment was performed before the yield measurement.

Also in this case, a so-called dual damascene method in which a via and an upper layer wiring are simultaneously formed (groove / hole filling and CMP) is employed. As in Example 1, a TEOS film was used as an interlayer insulating film, and a SiN film was stacked as an etching stop. The thickness of one layer was set to a via depth of 0.5 μm and a wiring thickness of 0.3 μm. The width of the upper layer wiring was set to 5 μm, and TEGs in which 10,000 vias having a via diameter of 0.3 μm and 0.2 μm were connected in series were formed and evaluated.

As a result, the structure shown in FIGS.
A yield of 8% or more is obtained, which is extremely high as compared with the case where no island is provided (the yield is 30% or less), and it is confirmed that the arrangement of islands near the vias as in this embodiment is effective for high reliability. did.

Further, as shown in FIGS. 29 to 32, it is needless to say that the effect of the present invention can be obtained even if the side surface of the wiring is deformed instead of providing the island.

<Embodiment 5> With the same TEG as in Embodiment 1,
Table 3 shows the results of making and changing the width of the upper layer wiring, measuring the yield, and comparing.

[0036]

[Table 3]

As a result of this example, it is found that when the width of the upper layer wiring is narrower than the diameter of the via, deterioration hardly occurs, but when the wiring width exceeds about 10 times the diameter of the via, deterioration due to heat treatment becomes remarkable. . This tendency is maintained even when the dimensions of the wiring and the via are changed, but the ratio of about 10 times the via diameter obtained this time is hardly considered to be universal. It is considered that the influence of the combination of the wiring material and the insulating film material may be remarkable from about several times.

<Embodiment 6> Dependency on island size (length) TEG similar to that in FIG. 6 of Embodiment 1 was prepared by changing the length of the island, and the yield was measured and compared. It is shown in Table 4.

[0039]

[Table 4]

The above results indicate that, although the islands in the upper wiring are easily deteriorated when the length of the islands in the upper wiring is shorter than the diameter of the vias, high reliability can be obtained if the islands are sufficiently long and the diameter exceeds about 10 times the via diameter. Is shown. This tendency is maintained even when the wiring size or via size changes, but this ratio of about 10 times obtained this time is not necessarily considered to be universal. It is thought that a sufficient reliability may be obtained with a combination of the wiring and the insulating film of about several times. Table 4
The above shows the results of studying only the length of the island, but it is considered that it depends on the width of the island. The shape having the least adverse effect on the electrical characteristics of the wiring and the greatest effect may be obtained and optimized for each individual case.

<Embodiment 7> The embodiments of the present invention have all described the wiring formed by the damascene method. In this method, a metal (copper in this embodiment) is buried in an insulating film in which a groove and a hole are formed, an unnecessary portion of copper is removed by a CMP method, and the remaining portion is used as a wiring. When copper is embedded, thick copper is formed by electrolytic plating on a thin layer of copper (approximately 1/10 of the final wiring thickness) formed by sputtering as a base layer called a seed.

However, in the above-described process, the optimum condition is often different between the condition for filling a relatively deep via hole and the condition for filling a shallow wiring groove. In this regard, a technique of changing the applied current condition during plating film formation is generally used, but does not necessarily provide a sufficient effect. This is because the width of the wiring connected to the via is different, and the shape (aspect) in which the hole and the groove are integrally formed has a wide distribution when the dual damascene method is buried.

If the method of providing the insulating film islands near the vias is adopted this time, the aspect of all the vias can be kept within a narrow range, so that the optimal plating conditions for the shape (aspect) can be selected.

Based on the above concept, two copper plating chambers using a plating solution containing copper sulfate as a main component were prepared, and plating solutions having compositions shown in Table 5 were prepared.

[0045]

[Table 5]

The plating is (1) formed to the final thickness only in the chamber A, (2) formed to the final thickness in the chamber B,
(3) First, after forming a 1/5 film thickness in the chamber A, the wafer was re-installed in the chamber B, and the remaining film thicknesses were evaluated for the three cases of formation, and the film thickness uniformity and the embedding property were evaluated and compared. Table 6 shows the results.

[0047]

[Table 6]

Although there is a disadvantage that the process becomes complicated, the method (3) in Table 6 is superior to the method (1) or (2) in that the embedding property and the film thickness uniformity can be realized simultaneously. Is evident. By unifying the apparent shape (aspect) of the via, such a two-stage embedding becomes possible, and it is possible to form a film suitable for manufacturing LSI wiring.

[0049]

According to the present invention, by providing the island of the insulating film in the wiring near the via, the yield and reliability of the multilayer wiring can be improved, and a high-performance LSI can be realized.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a conventional via connection method for multilayer wiring.

FIG. 2 is a bird's-eye view showing an example of a conventional via connection method for multilayer wiring.

FIG. 3 is a plan view showing an example of a conventional via connection method of a multilayer wiring.

FIG. 4 is a bird's-eye view showing an example of a conventional via connection method for multilayer wiring.

FIG. 5 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 6 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 7 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 8 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 9 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 10 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 11 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 12 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 13 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 14 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 15 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 16 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 17 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 18 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 19 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 20 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 21 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 22 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 23 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 24 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 25 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 26 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 27 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 28 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 29 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 30 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 31 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

FIG. 32 is a plan view showing an example of a via connection method for a multilayer wiring according to the present invention.

[Explanation of symbols]

1 upper wiring, 2 upper and lower wiring connection holes, 3 lower wiring,
4: islands of insulating film provided in wiring.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kenichi Takeda 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo F-term in Central Research Laboratory, Hitachi, Ltd. 5F033 HH08 HH11 JJ01 JJ08 JJ11 MM01 MM02 MM21 MM22 PP15 PP27 QQ25 RR04 RR06 SS04 SS15 XX00

Claims (9)

[Claims] 1. A wiring connected to a via and having copper or aluminum as a main component and having a width larger than the via diameter and having a region (hereinafter simply referred to as an island) buried with an insulating film inside the wiring near the via. Characteristic wiring structure. 2. A wiring connected to a via without a boundary of a conductive material such as a barrier and having copper or aluminum as a main component having a width larger than the via diameter, wherein an island is present inside the wiring near the via. Wiring structure. 3. A connection to a dual damascene via,
A wiring structure mainly composed of copper or aluminum having a width larger than a via diameter and having an island inside the wiring near the via. 4. In a plan view, there are islands substantially in contact with the vias (overlapping or closely spaced below the lithographic minimum dimension).
The wiring structure according to any one of the above. 5. The wiring structure according to claim 1, wherein there are islands in a direction substantially equal to or more than half of the via in a plan view. 6. The wiring structure according to claim 1, wherein, in a plan view, an island or a wiring end is provided in a direction substantially equal to or more than half of the via. 7. A wiring connected to a via and mainly composed of copper or aluminum having a width larger than 10 times the via diameter,
7. The wiring structure according to claim 1, wherein there is an island inside the wiring near the via. 8. A semiconductor device having the wiring structure according to claim 1. 9. A semiconductor device having four or more wiring layers, at least a part of which has the wiring structure according to claim 1. Description: